Design and implementation of a monolithic bipolar read-out system

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PROCEEDINGS SUPPLEMENTS

Nuclear Physics B (Proc. Suppl.) 44 (1995) 617-620

Design and implementation

of a

monolithic bipolar read-out system

A. Baschirotto '2, R. Castello 12, A. Gola 3, G. Pessina', P. G. Rancoita 1, M. Redaelli', A. Seidman ~, M. VolpP 1 _ I . N . F . N . - Via Celoria, 16 - 20133 M i l a n o - I T A L I A 2 _ D i p a r t i m e n t o di Elettronica - U n i v e r s i t a ' di Pavia - Via Abbiategrasso, 209 - 2 7 1 0 0 Pavia - I T A L I A 3 _ S . G . S . - T h o m s o n M i c r o e l e c t r o n i c s - Via Tolcnneo, 1 - 2 0 1 0 0 M i l a n o - I T A L I A 4 _ D e p t . o f P h y s i c a l Electronics, T e l A v i v U n i v e r s i t y , R a m a t - A v i v 6 9 9 7 8 - I S R A E L

Design and implementation issues regarding a bipolar high-speed read-out system to be used at future high luminosity colliders, such as LHC, are presented. The entire system consists of two blocks (the preamplifier and the RC-CR shaper) to be located in separate positions. For this purpose different monolithic solutions were realized for testing. Noise and speed considerations led to use of bipolar technology. Preliminary experimental results in good agreement with simulations, are given for one of the realized electronic chains. 1.

INTRODUCTION

The purpose of elementary particle physics e x p e r i m e n t s at future high luminosity colliders such as LHC (Large Hadron Collider at CERN - Geneva) is to look for energetic physics phenomena which are forecast to occur at a small probability. Therefore, a very high number of candidate events (a beam interaction rate of 108 sec -1) m u s t be generated to assure the collection process under investigation. Moreover, to achieve an adequate precision and accuracy a very large n u m b e r of sensors (106-107 ) have to be implemented in the overall structure [1]. Suitable read-out electronics should be developed to satisfy stringent requirements of speed, noise, dynamic range, power dissipation, and radiation hardness [1]. To avoid stray capacitance, the read-out is located as close as possible to the detectors. In this location the space occupation of each read-out system is minimised, by adopting monolithic electronics implementation. Fig. 1 shows a typical electronics read-out channel, consisting of a preamplifier, shaping filter, and ADC [1-5]. incoming particles generate charge in the detector which is integrated by the preamplifier and filtered by the shaper, in order to obtain the proper time evolution. Then, the ADC converts the signal amplitude for the successive storing in a computer. We developed monolithic Charge Sensitive Preamplifiers (CSP) with different circuit configuration for testing. In this paper one of © 1995 Elsevier Science B.V, All rights reserved. 0920-5632(95)00594-3

0920-5632/95/$09.50 SSDI

CSPs and a RC-CR shaper for the monolithic read-out system to be used in the silicon hadron calorimeter experiment of RD35 [5] are reported. Both circuits operate with large input and output (up to 5V) signals and are required to process the signal in very short time slot (of the order of tens of ns). The needed short shaping time requires a CSP with low series input noise [3]. An input NPN bipolar transistor satisfies well this requirement. For this reason the chosen technology for the silicon realization of the electronics is 2~m BiCMOS (HF2CMOS p r o d u c e d by SGSThomson) which features a 6GHz NPN device and a 2GHz vertical-isolated PNP device. R

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Fig. ? - Typical read-out

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2. READ-OUT CHANNEL ARCHITECTURE AND REQUIREMENTS The RD35 silicon h a d r o n calorimeter structure [5] consists of several parallel planes each presenting a matrix of detectors: each one connected to a monolithic CSP. To reduce space occupancy a quad preamplifier chip (4 CSPs on a single chip), to be placed at

618

A. Baschirotto et al./Nuclear Physics B (Proc. Suppl.) 44 (1995) 61 ~ 6 2 0

levels for the input device, modifying the noise performance, in order to save power when the CSP is used under less stringent noise requirements. The required features for the shaper are: 20ns shaping time, large input and output signal amplitude (up to 5V), capability of summing up several input signals, and 100f2 output drive capability.

the center of each 2x2 detector arrays, is realized. Fig. 2 shows a mini-tower structure. A number (2 in the example) of CSPs, having the same longitudinal position in the corresponding planes, are summed up, after driving a terminated coaxial cable, at the input of the shaper, located on the service plane. The shaper has also to drive a 50f2 cable to feed the following A / D converter. Detectors on different / planes . CSPs Shaperon the ~ / 2 __ serviceplane '

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3. CHARGE SENSITIVE PREAMPLIFIER The design of the CSP must satisfy the fundamental trade-off between noise and slew-rate performance. To obtain low series input noise (= 1/2gin), high input transconductance is needed, thus, requiring large compensation capacitance, since emitter degeneration of the input transistor is not permitted. Fig. 3 shows one of the four realized CSPs. The CSP operation is based on a dominant pole amplifying stage consisting of Q1 to Q4 and the output buffer (QB4 to QB22). An auxiliary circuit (QSR1 to QSR4 and Csr), added to the main network, causes a gain degeneration only for small input signals (reducing the compensation capacitance), not being active for large signals (increasing the slew-rate performance).

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connection Fig. 2 - Structure to be implemented in RD35 experiment

The requested specifications for the CSP are: rise time lower than 10ns for a 5V output signal amplitude (slew-rate larger than 400V/I.tS), 100dB dynamic range, and 50f2 driving capability. It is also required to have the possibility, by varying a suitable external component (resistor) to set different current charge sensitive preamplifier

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Fig. 5 - CSP transient response

The preamplifier bias circuit, on the right of the figure, e n a b l e s n o i s e p e r f o r m a n c e adjustment, by regulating the input device current, to w h i c h the CSP noise is inversely proportional, in order to save power when the CSP is used with less stringent S / N ratio requirements. A single external resistance, REXT (Fig. 3) sets the bias, to fix the proper i n p u t d e v i c e c u r r e n t level. A n external capacitance CEXT filters the biasing node at high-frequency. Fig. 4 shows the preamplifier chip layout. Fig. 5 shows the response to a small signal. For a large one, with a 3mA input d e v i c e c u r r e n t , a slew-rate larger than 1000V/fts is achieved, g i v i n g a rise time smaller than 4ns.

network is very large, of the order of fT of the output transistor if the Miller effect of the o u t p u t transistor is kept low, a n d p r o p e r biasing current is adjusted for Q1 and Q2. The cell is also used as a unity gain buffer in the output stage, (Q4, Q5 and Q6).

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Fig. 6 - Basic cell structure of the shaper

RC-CR SHAPING FILTER

The s h a p i n g filter allows to optimise the signal-to-noise ratio b y setting a suitable frequency bandwidth, and giving to the signal a p r o p e r shape in the time d o m a i n . Two additional features are required to the shaper: the capability of s u m m i n g up several input signals a n d low i n p u t noise. A m o d u l a r solution was employed. For the case of a single input signal, the proposed basic cell, implementing the RC-CR s h a p i n g response, is given in Fig. 6. Q1 operates at a constant current. This forces the base-emitter voltage constant, giving very large i n p u t i m p e d a n c e (Rin). The s t r u c t u r e consisting of Q1 and Q2, operates as a voltage buffer (from vin to vig). The voltage gain from VIN to the collector of Q2 (Fig. 6) equals -Z2/ZI: the use of the Q2-Q3 Darlington configuration reduces the error due to the 13effect, from 1/[3 to 1/132. The b a n d w i d t h of the amplifying

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The feedback action of Q4 lowers the o u t p u t impedance of Q5, Q6. The output PNP buffer is able to drive a 50f2 terminated coaxial cable. The response of the n e t w o r k to an i n p u t 1

RB

current pulse Qi 8(t) is: Vo(t) - 2CF RA (l+s x) 2"

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(with ~=RA CA=RC CC, and RF CF>>x). A n i m p o r t a n t result r e g a r d s the total RMS noise. It can be d e m o n s t r a t e d [11] that the series noise c o n t r i b u t i o n of the filter is lower than thai of the classical structure based on an o p e r a t i o n a l a m p l i f i e r . T h i s c i r c u i t is v e r y convenient w h e n it is n e e d e d to s u m u p signals from several detectors [5], in o r d e r to reduce t h e n u m b e r of c a b l e c o n n e c t i o n s . The i m p l e m e n t a t i o n of the s u m is s h o w n in Fig. 7. The circuit is based on the use of m a n y input cells, like the one described in Fig. 6, where the currents are s u m m e d u p across the impedance ( C A / / R A ) . In a d d i t i o n this a r r a n g e m e n t e n a b l e s to s a v e area, by s h a r i n g the filter capacitors, CA, a m o n g all i n p u t cells. This is i m p o r t a n t since the actual i m p l e m e n t a t i o n of the circuit (Fig. 7) s h o u l d not a d d noise to its i n p u t , r e q u e s t i n g the u s e of s m a l l v a l u e s resistors R1, R2 a n d RB, a n d , hence, h i g h values capacitance C A a n d CB, for obtaining = C A RA = CB RB = 20nsec. The small values of R1, R2 and RB p e r m i t to maintain low their thermal noise. The r e s p o n s e of the circuit, w h e n l o a d e d w i t h a 100f2 i m p e d a n c e , for a small o u t p u t signal, is given in Fig. 8. 240

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5.

CONCLUSIONS

In this p a p e r the design, implementation and experimental r e s u l t s of a h i g h - s p e e d m o n o l i t h i c r e a d - o u t s y s t e m for h i g h - e n e r g y physics e x p e r i m e n t s (RD35) w e r e presented. The r e a d - o u t channel consists of two separate i n t e g r a t e d c i r c u i t s (a p r e a m p l i f i e r a n d a

shaping filter) interconnected b y a 50f2 coaxial cable. The high-rate of events i m p o s e s the use of bipolar technology, in o r d e r to reduce highfrequency noise contribution. The use of such a read-out channel, in radiation exposed regions, requires the characterisation of the technology b e h a v i o u r after irradiation and, therefore, the d e s i g n of circuits w h i c h takes into a c c o u n t possible radiation damage effects. Experimental results of the realized electronics after irradiation are being investigated. ACKNOWLEDG EMENTS The authors wish to a c k n o w l e d g e the help of C. O n a d o a n d G. P i n z a n for the d e v i c e characterisation. 6.

[1]

REFERENCE

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