- Email: [email protected]
Design and performance of a threshold-based load balancing scheme in an ATM switch
ISDN SYSTWS Computer Networks and ISDN Systems 29 ( 1997) 157-164
ELSEVIER
Design and performance of a threshold-based load balancing scheme in an ATM switch Shyamal Chowdhury a~1,Bhaskar Senguptab,* a IBM
Corporation, h C&C
11400 Burner Rd, Internal Mail Code 9633, Room 3BOl6/Bldg. 906, Austin, Research Laboratories. NEC USA, 4 Independence Way, Princeton, NJ 08540, Accepted
20 February
7X 78758. USA
USA
1996
Abstract We consider an ATh4 switch consisting of a number of output-buffered ATM switch elements operating in parallel. Such an architecture may lead to uneven distribution of cells over the parallel switch element buffers, if no modifications to the design is made. ‘With this motivation, we propose a threshold based load balancing method to evenly distribute the cells
over the parallel switch element buffers. We present the details of how the load balancing method can be implemented. Our computer simulations show that the proposed load balancing method significantly reduces the cell loss probability. The study is done wi1.h two input traffic models: random traffic and bursty traffic. Keywords: ATM switches; Load
balancing
1. Introduction
Asynchronous Transfer Mode (Am) is a connection-oriented switching and multiplexing principle. In an ATM network, fixed size short packets called cells are used to transfer information across the network. An N x N ATM switch is an ATM Layer equipment connected to N input lines and N output lines. An ATM switch transfers a cell from any one of the input lines to any one of the output lines. An important class of ATM switch architectures is the output buffered switch architecture [ 3,4,6]. Recently an output buffered ATM switch called the ATOM switch has been proposed by Suzuki et al. [lo]. An * Corresponding
author.
Email:
[email protected].
’ This work was done while the author was visiting the C&C Research Laboratories of NEC USA Inc. during the summer of 1992.
8 x 8 prototype of the switch has been built [5]. Another architecture that has a number of ATOM switch elements operating in parallel has been proposed by Aramaki et al. [ 11. The line speed for this architecture can be S times the possible line speed for the architecture presented in [ lo], S being the degree of parallelism. A second advantage of this architecture is that it is capable of providing more’buffer per output line than the architecture described in [ lo]. The architecture described in [ 1] may lead to uneven disc tribution of cells in the buffers of the switch elements that operate in parallel. In this paper, we propose a threshold-based method for load balancing in the buffers of the parallel switch elements. Our simulation results show that the proposed load balancing method reduces the cell loss probability significantly. The proposed method is simple and easy to implement. We observe that the subject of load balancing
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has been studied often in the engineering literature and remains a vital force that guides many design decisions. Some examples of this (mainly relating to interconnection networks, call setup times in telecommunications and distributed computing systems) may be found in [ 7-91. The organization of the paper is as follows. In Section 2, we describe the switch architecture under study. In Section 3, we describe the operation of the switch using mathematical notations. In Section 4, we describe the threshold-based load balancing method. In Section 5, we present our results.
2. Description
of the switch
We describe an ATM switch consisting of a number of ATOM switch elements operating in parallel [ lo]. The structure of the ATOM switch is depicted in Fig. 1. This is basically an output buffered switch and the reader is referred to [4] for a general description of these and other types of switches. For the operation of the switch, time is assumed to be slotted. Our unit of time is the duration of a slot. Cells arrive at the switch input lines at the beginning of a slot. It takes the duration of a slot for the arrival of a complete cell. At each input line, only one cell can arrive in one time slot. A cell in an input line is converted from the serial form to the parallel form by a S/P converter shown in Fig. 1. The heart of the switch is a multi-bit bus. The input cells are broadcast on the bus. Time division multiplexing technique is used by the N input lines to access the bus to broadcast cells on the bus. For each output line there is a dedicated buffer. The buffer is necessary since more than one cell that arrive in the input lines in the same slot can have the same output line as destination. There is an address filter (AF) for each output line. The address filter for output line j allows every cell broadcast on the bus and having output line j as destination to queue in the buffer for output line j. The address filter for output line j prevents cells having destinations other than output line j from queueing in the buffer for output line j. Each output buffer is followed by a P/S converter that converts a cell from the parallel form to the serial form for transmission on the output line. Since there are N input lines, at most N cells can arrive in one slot. If the number of bits in a cell is L
and
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then the maximum possible number of parallel lines in the bus is L. Consequently, if the speed of each input line is V, the required speed of the bus is NVL. If the physically attainable maximum bus speed is Rmax, then the input/outputline speed is limited to V = LR,,,/N. Thus the switch architecture presented in Fig. 1 is not suitable for input/output linespeeds beyond LR,,,/N. Fig. 2 depicts a switch architecture that can support a higher input/output line speed by having a number of ATOM switch elements which operate in parallel. The number of switch elements is denoted by S. For each input line, there is a distributor. A distributor cyclically distributes the incoming cells to the S switch elements. The precise meaning of cyclical distribution is explained later in Section 3. The operation of a switch element is exactly as described above. This architecture makes it possible to support a maximum line speed of V = SLR,,,/N. For each output line there is a cell transmitter. Since cells with a particular output line as destination are now queued in each of the S ATOM switch elements, the cell transmitter has to pick up cells from S distinct buffers. As explained later in Section 3, the cells are to be removed from the buffers and transmitted in a particular order. Otherwise, the cells will leave the switch in a sequence different from the sequence in which they arrived. In Section 3 we describe the operation of the switch in detail. The switch architecture depicted in Fig. 2 has another important advantage over the switch architecture depicted in Fig. 1. There is a limit to the size of buffer per line that the switch depicted in Fig. 1 can have since the switch is built as a set of VLSI chips [5]. The switch depicted in Fig. 2 has a number of parallel switch elements, and so the total size of buffer per line is the sum of the buffer sizes per line per switch element. Thus, we can have a substantially larger buffer per line in the architecture depicted in Fig. 2 compared to the architecture depicted in Fig. 1.
3. Description
of the switch
operation
It is convenient to think of each distributor (see Fig. 2) as operating in cycles whose duration is S time units. The cycles are numbered 1,2,3,. . . . If cycle k begins at time x, then at time x + i - 1, 1 < i 6 S, the distributor for input line j, 1 ,< j < N, would send a
S. Chowdhury,
B. Sengupta/Computer
Networks
Tiia-division
Fig. I. The structure
Distributor For Input 1
and ISDN
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157-164
159
Bus
of the ATOM
ATOM Switch Element
switch.
Transmitter
1
1
Output Lines
N
Distributor
For Input N
Fig. 2. An ATM
switch
Transmitter
ATOM Switch Element S
architecture
with S switch
cell to switch element i if a cell is available at input line j. Switch ,element i does not receive any ceI1 from the distributors at any other time during cycle k. A cell is distributed immediately after its arrival at the input. Thus, at each distributor, the cells are distributed on a first-come-first-served (FCFS) basis, regardless of the destination. The switch elements are scheduled to receive cells in a cyclic round-robin manner. Whether the elements actually receive cells in a round-robin manner depends on the availability of cells for distribution. If we have a newly arrived cell in every slot then the switch elements will receive cells in a roundrobin manner. However, in reality there will be no cell arrivals in some slots. For this reason, the switch el-
elements
operating
N
in parallel.
ements do not receive cells in a strictly round-robin manner. Hence we say that the switch elements receive cells in a quasi-round-robin (QRR) manner. An output buffer of a switch element receives cells after intervals of length S units (assuming cells are available). The cell arrival process at an output buffer of a switch element can be described as follows. The arrivals occur in a sequence of cycles numbered 1,2,3 ,.... Each cycle is of length S time units. If cycle k begins at time x, then at time x + i - 1, cells arrive at the output buffers of switch element i. The number of cell arrivals in cycle k at output buffer j of switch element i is denoted by Akij where 0 < Akij < N. The set of cells that arrive in cycle k at
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Networks
output buffer j of switch element i is denoted by Ckii. The Cells in Set Ckii and those in Ck,i+t,,i arrive in their respective buffers after an interval of one time unit. Let US consider the operation of the transmitter for output line 1. The transmitter for output line 1 is responsible for picking up cells from the output buffers for output line 1 in the switch elements and transmit them on output line 1. Assume that the operation of the transmitter begins at time 0. At time 0, cells belonging to the set Ct t t are available in output buffer 1 of switch element 1. At time 0, no cell is available at the output buffers of the other switch elements. The transmitter can immediately begin to act. If the set Ct t t is nonempty then in one time slot the transmitter transmits one cell. At time 1, cells belonging to the set Ctzt become available at output buffer 1 of switch element 2. But, the transmitter must transmit all cells belonging to the set Ct t t before it can transmit any cell belonging to the set Cizt. This is to ensure that cells leave the switch in the same sequence as they arrive at the switch. Depending on the value of A,,1 and on the value of S, it is possible that the cells belonging to the set Czt t would arrive at output buffer 1 of switch element 1 before the transmitter has transmitted all the cells belonging to the set Ct 11. The transmitter, however, must transmit all cells belonging to the sets ~121,~131~. . . 3 Ctst in that order before it can transmit any cells belonging to the set Cztt. So the sets of cells are transmitted by the transmitter for output line 1 in the following order: ~I1I~~121~~131~..~~
CJSl,
c211,
c221,
c231,.
. * , c2SI,
~311~~321~~331~...~
c3S1,
c411,
c421,
c431 I . . . , c4S1.
Thus, the transmitter is implementing a re-sequencing function. For a given input line and a given output line, cells leave the ,switch in tlie same sequenceas they arrive. i L 4. The threshold-based load balancing method Each buffer for an output line is consideredto be in one of two states: lightly-loaded state and heavilyloaded state.qAbuffer is saidto be lightly-loaded if the number of cells in the buffer is lessthan or equal to a threshold T. A buffer is saidto be heavily-loaded if the number of cells in the buffer is greater than a threshold T. There is a load matrix consistingof a total of S x N
and ISDN
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Buffer
NC
Buffer
OC
/57-164
(Switch Element No)
Decision Fig. 3. The above figure explains the generation of two signals, lmo and lmn, used by the decision circuit. The signal Imn gives the load matrix entry for a newly arrived cell in buffer NC. The signal lmo gives the load matrix entry for a cell stored in the buffer OC. To generate these signals, a load matrix row is selected by a counter that gives the number i of the switch element that is scheduled to receive a cell in the slot under consideration. The destination field of the cell in buffer OC selects a column of the load matrix. The selected load matrix entry is the signal lmo which gives the state of the destination output buffer in the switch element i. Similarly, the signal lmn is generated. The main outputs of the decision circuit are two signals that indicate what to do with the cells in buffers NC and OC (see Algorithm 1 in Fig. 4).
bits. The load matrix has S rows and N columns. We denote the load matrix by L. The matrix element Li,i gives the state of the output buffer for line j in switch element i. The matrix element Lij takes one of two values: 0 and 1. The value 0 standsfor a lightly-loaded buffer. The value 1 standsfor a heavily-loaded buffer. A matrix element is changed (or written) by a switch element, and used (or read) by a distributor. A bit representingthe stateof a buffer is fed back to the load matrix by the switch elements.The feed-back is provided only when there is a change of state for an output buffer. In the load balancing method, when all the buffers are lightly-loaded, the cell service discipline in a distributor is FCFS. When some of the buffers are heavily-loaded, we attempt to direct cells away from the buffers that are heavily-loaded and towardsthe buffers that are lightly-loaded. This leadsto a non-FCFS service discipline in a distributor. However, the switch elementsstill receive cells in a QRR manner. This is accomplishedas follows. Each distributor hastwo finite buffers each of size 1 (Fig. 3).
S. Chowdhury,
E. Senguptu/Cmpurer
Networks
Algorithm for decision if (there IS a cell in OC) { generate signal Imo; if (lmo == 0) { send cell in OC; if (there is an arriving cell) store arriving cell in OC; I else { /‘: Imo== I */ if (there is a newly arriving cell) { generate signal Imn; if (Imn == 0) send arriving cell; else { /* Imn== I */ send cell in OC; store arriving cell in OC; > I 1 return; I /* there is no cell in OC */ If (there is no newly arriving cell) return; I* there is a newly arriving cell */ generate Imn if (Imn == 0) send newly arriving cell; else stcre arriving cell in OC; return; .~ Fig. 4. Algorithm 1. Distributor algorithm to make a decision about sending a newly arriving cell in buffer NC or a cell in buffer OC to a switch element in a slot.
One buffer is for a newly arrived input cell, called NC. The other buffer is for a cell which has arrived in an earlier slot but whose distribution to a switch element has been postponed for the purpose of load balancing. This buffer is called OC. Each of the buffers NC and OC can store: only one ATM cell. At the time of arrival of a new cell, the buffer OC is either empty or has a cell in it. For making a cell distribution decision, we use two signals Imn and Imo. The method used to generate the two signals is explained in Fig. 3. The decision to send the cell in buffer NC or the cell in buffer Of: to a switch element is made according to the algori,thm given in Algorithm 1 (Fig. 4). The algorithm has been written using the syntax of the C language. A significant portion of the algorithm can be executed by a lookahead circuit. In particular, if there is a cell in buffer OC then the signal lmo can be
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generated before the beginning of the slot for which the decision is being made.
5. Simulation
results
We simulated the ATM switch described in Section 3 for 150 million slots. We considered an 8 x 8 switch with 8 parallel switch elements. In Tables I and 2, we present our main performance metric: number of cells lost per million of incoming cells. We evaluated the performance of the switch in two cases: without load balancing and with threshold-based load balancing. We first discuss the random traffic model. In this model, we assume that a cell arrives in a slot at the input line with probability p independently of other slots and lines. Each output line is equally likely to be a destination of an arriving cell, independently of other cells. For this model, the line utilization u = p. The values of the number of cells lost per million of incoming cells for various values of u are presented in Table I. It is listed under the headings “no load balancing” and “load balancing”. We find from Table 1 that the threshold-basedload balancing method significantly reducesthe number of cells lost. The effectiveness of the load balancing method dependson the value of the threshold. For N = 8, S = 8, B = 8, and u = 0.9, the best results are obtained when the threshold T = 4. We now consider the bursty traffic model. We assume that traffic on each input line is bursty and that it consistsof a sequenceof cycles. Each cycle has an active and an inactive period. The length of an active period is geometrically distributed with mean 1/q. The length of an inactive period is also geometrically distributed with mean l/r. On each input line during an active period, a cell arrives in a slot with probability p independently of other slots and input lines. No cell arrives during an inactive period. The active and inactive periods are assumedto be independent. For this model, the line utilization u = pr/( q + r). In Table 2, we present the number of cells lost per million of incoming cells for the bursty traffic model. In our simulationsaveragecycle length 1/q + 1/r was set to 20. In Table 2, p = 1.0. That is, in an active period, we have a cell arrival in every slot. We find that the number of cells lost is significantly reduced by load balancing. We observe that the number of cells lost
162
S. Chowdhury, Table 1 Random traffic: N
number
B. Sengupta/Computer
B
8 8 8 8
8 8 8 8 8
8 8 8 8 8
0.90 0.90 0.90 0.90 0.85
8 8 8 8 8 8 8
8 8 8 8 8 8 8
8 8 8 8 8 8 8
0.85 0.85 0.85 0.80 0.80 0.80 0.80
Table 2 Bursty traffic:
number
and ISDN Systems 29 (1997)
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of cells lost per million
S
8
Network
u
No load balancing
T
Load balancing
49.49
3.44
5 4 3 -
15.500 10.200 10.600
5 4 3
1.290 0.720 0.470
5 4 3
0.180 0.100 0.056
0.33 -
of cells lost per million
N
S
B
P
8 8
8
1.0 1.0 I.0 1.0 1.0 I.0 I.0 I .o 1.0 I.0 I.0 1.0 1.0
0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.90 0.90 0.90 0.90 0.90 0.90
I.0
0.90
8 8 8 8 8 8 8 8 8 8 8
8 8 8 8 8 8 8 8 8 8 8 8
I2 I2 I2 I2 I2 I2 I2 I2 I2 I2 12 I2 I2
8
8
I2
u
depends on the threshold value, and is minimized by a particular threshold value. We now present a study which is aimed at classifying the cells buffered in a distributor in an attempt to understand which type of cells may get lost and vice versa. To understand the dynamics of the thresholdbased load balancing method, we divided into four classes the cells that are stored in the buffer OC in a distributor. The cells that would have gone to a heavily loaded buffer on arrival, but are eventually redirected to a lightly loaded buffer by the load balancing method are called well-directed cells. The cells that would have gone to a heavily loaded buffer on arrival, and are eventually sent to a heavily loaded buffer are called one-one cells. The cells that would have gone to a lightly loaded buffer on arrival and are eventually sent to a lightly loaded buffer are called zerozero cells. The cells that would have gone to a lightly
No load balancing
T
0.0147
6 7 8 9 IO II
Load balancing 0.0000 0.0000 0.0020 0.0020 0.0069 0.0127 -
0.508
-
0.0213 0.0185 0.0148 0.0333 0.0889 0.2454
loaded buffer on arrival and are eventually sent to a heavily loaded buffer are called ill-directed cells. In Tables 3 and 4, the percentage of the different classes of cells obtained by simulation are presented. We observe that the well-directed cells are the ones that are possibly saved from being lost. A significant percentage of cells that are buffered in OC are zerozero cells. This can be explained as follows. Suppose a cell Xt arriving at time t is stored in OC because its destination buffer switch element i is heavily loaded. Suppose at time t + 1 a cell X2 arrives, and the destination buffers of Xt and X2 in switch element i+ 1 are lightly loaded, We send Xt to switch element i + 1. So XI is a well-directed cell. Suppose X2 is immediately followed by a number of cells X3, X4,. . . , X, which arrive at consecutive time slots. Suppose the buffers for the destination of these cells in all the switches are lightly loaded. In this case each of the cells X2, . . . , X,,
S. Chowdhury, Table 3 Random traffic:
classification
3--
s
B
-i8 8 8 8 8 8 8 -
8 8 8 8 8 8 8 8
8 8 8 8 8 8 8 8
Table 4 Bursty traffic: i-S 7
-
8 8 8 8
12 12 I2 I2 12
Networks
of the cells buffered u
T
0.90 0.90 0.90 0.85 0.85 0.85 0.80 0.80
classification B
8 8 8 8 8
B. Sengupra/Compuler
5 4 3 5 4 3 4 3
0.90 0.90 0.90 0.85 0.85
Ill-directed
10.63 10.99 II.50 15.21 15.29 15.55 20.13 20.2 I
P
T
I.0 I .o 1.0 1.0 1.0
5 7 10 6 8
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163
in a distributor
Well-directed
of the cells buffered u
and ISDN Systems 29 (1997)
Zero-zero
0.08 0.13 0.20 0.03 0.05 0.07 0.02 0.03
89.19 88.7 I 88.04 84.73 84.59 84.26 79.81 79.7 I
One-one 0.09 0.17 0.26 0.04 0.07 0.12 0.04 0.05
in a distributor Well-directed
are zero-zero cells. Each of them spend one time unit in buffer OC after arrival and then they are sent to a switch element. As we save XI from a possible loss due to switch element buffer overflow by buffering it temporarily in. OC, we increase by a time unit the delay suffered by each of the cells X2, X3,. . . , X,, which arrive in consecutive slots immediately after X1. It appears that the, above scenario is very common. This explains why a very high percentage of cells are zerozero cells. It is interesting to observe that in all our simulations we have a few ill-directed cells. An illdirected cell faces the following scenario as it passes through a distributor. Consider an ill-directed cell XI. As Xl an-ive:s there is a cell in OC. The switch element destination buffer of X1 is lightly loaded and so is the switch element destination buffer of the cell in OC. The cell in OC is sent and X1 is stored in OC. In subsequent slots, we attempt to send X1 to a switch element buffer that is lightly loaded. However, no lightly loaded buffer is found. Eventually a new cell arrives whose switch element destination buffer is heavily loaded. So we are forced to send X1 to a heavily loaded buffer. In addition to the results discussed in this section, we have developed analytical models to find the delays for the random traffic model as well as the bursty traffic model. We have simulated the switch and found the delays through the switch for both the random and
Ill-directed
6.39 6.03 5.87 6.14 5.90
0.10 0.05 0.03 0.02 0.00
Zero-zero 93.42 93.88 94.10 93.83 94.10
One-one 0.09 0.04 0.00 0.01 0.00
the bursty traffic models. The results from the analysis are very close to the results from the simulation (for both the mean delay and the coefficient of variation of delay). Further, we have simulated the delay suffered by a cell in a switch element and observe that there is hardly any difference between the load balancing case and the case without load balancing. Finally, we have also studied the mean delay suffered by a cell in a distributor buffer. We observe that this delay is relatively small. The details of these results are shown in [2].
6. Discussion
One way to reduce the number of cells lost further is to increase the size of the buffer OC in a distributor. This will reduce the number of ill-directed cells and the number of one-one cells. However, in Section 5 we find that the percentages of ill-directed cells and of one-one cells are very small. So the improvement in system performance by increasing the size of OC is expected to be marginal. From our numerical results, we find that the cell loss probably varies with the value of the threshold. Therefore, for any given traffic scenario, there is an optimal threshold value. Since the pattern of network traffic has a time varying nature, the threshold value should be set dynamically, as changes occur in the net-
164
S. Chowdhury,
B. Sengupu/Computer
Networks
work traffic. Such a dynamic assignmentof the threshold requires a mechanismfor detection of changesin the network traffic. In an ATM network, an admission controller knows both the number and types of caIls currently in progress.Therefore, it may be natural to usethis information to decide the optimal value of the threshold. It is also true that the number and range of traffic scenariosis an ATM network could be very large indeed. Thus some research is needed to break this down into a small number of classes,so that the task of dynamic assignmentdoesnot become too overwhelming. We leave this problem as an item for future research. An alternative to threshold-basedload balancing is to distribute the cells to the switch element buffer that has the smallestnumber of cells. An implementation of sucha load balancing method is much morecomplicated than an implementation of the threshold-based method. Optimal or near-optimal load balancingmethods are unsuitable for high speedswitchesbecauseof implementation problems. The threshold-basedload balancing method with one-cell buffer OC in eachdistributor can be implemented in a practical switch. References [ 11 T. Aramaki, H. Suzuki, S. Hayano and T. Takeuchi, Parallel “ATOM” switch architecture for high speed ATM networks, in: Proc. IEEE ICC’92 (1992) 250-254. [Z] S. Chowdhury and B. Sengupta, Threshold based load balancing in an ATM switch consisting of parallel output buffered switch elements. NEC USA Tech. Rept. No. 93coo7-4-5007-l. 1993. [ 3 1 M.G. Hluchyj and M.J. Karol, Queueing in high-performance packet switching, IEEE J. Selected Areas Commun. 6 (9) (1988) 1587-1597. 141 J.Y. Hui, Switching and Trujic Theory for Integrured Broadband Networks (Kluwer, Boston, MA, 1990). [5] A. Itoh, W. Takahashi, H. Nagano, M. Kurisaka and S. Iwasaki, Practical implementation and packaging technologies for a large-scale ATM switching system,lEEE J. Selected Areas Commun. 9 (8) (1991) 1280-1288.
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29 (I 997) 157-164
161M.J. Karol, M.G. Hluchyj and S.P. Morgan, Input versus output queueing on a space division packet switch, IEEE Truns. Cornmun. 35 (12) (1987) 1347-1356. (71 K. Qiu and S.G. Akl, Load balancing and selection on the star and pancake networks, in: Proc. 26th Hawaii fniernut. Con$ on S~vstems Science, Vol. 2 ( 1993) 235-242. 181R. Simha and J.F. Kurose, On-line minimization of call setup time via load balancing: A stochastic approximation approach, IEEE Trans. Gmmnn. 42 (2-4) ( 1994) I14111.52. 191 M.G. Sriram and M. Singhal, Measures of the potential for load sharing in distributed computing systems,IEEE Trans. Sojiiare Engineering 21 (5) 1995) 468-475. 1101 H. Suzuki, H. Nagano, T. Suzuki, T. Takeuchi and S. Iwasaki, Output-buffer switch architecture for asynchronous transfer mode, in: Proc. IEEE ICC’89 (1989) 99-103.
ShyamalChowdhury is a computer sci-
entist at IBM Corporation, Austin, Texas. He received a Ph.D. degree in computer science fromthe Universityof Arizona, Tucson, Arizona, in 1990. His research interests include high speed networking and multimedia networking.
Bhaskar Sengupta obtained his doctoral
degreefrom the Operations Research
Department of Columbia University in 19%. He was a faculty member in the department of Applied Mathematics and
,%&tics in theStateUniversityof New YorkatStonyBrookfrom I976to 1981.
Subsequently, he worked in AT&T Bell Laboratories and was a Distinguished
Memberof Technical Staffwhenheleft
in 1990. He has been an adjunct faculty member in Columbia University and has consulted with many companies in New York. He is currently the Head of the Perfor&ncd Analysis Department at the C&C Laboratories, NEC USA. His research interests are in queueing theory and its applications to computer and communications problems.
ELSEVIER
Design and performance of a threshold-based load balancing scheme in an ATM switch Shyamal Chowdhury a~1,Bhaskar Senguptab,* a IBM
Corporation, h C&C
11400 Burner Rd, Internal Mail Code 9633, Room 3BOl6/Bldg. 906, Austin, Research Laboratories. NEC USA, 4 Independence Way, Princeton, NJ 08540, Accepted
20 February
7X 78758. USA
USA
1996
Abstract We consider an ATh4 switch consisting of a number of output-buffered ATM switch elements operating in parallel. Such an architecture may lead to uneven distribution of cells over the parallel switch element buffers, if no modifications to the design is made. ‘With this motivation, we propose a threshold based load balancing method to evenly distribute the cells
over the parallel switch element buffers. We present the details of how the load balancing method can be implemented. Our computer simulations show that the proposed load balancing method significantly reduces the cell loss probability. The study is done wi1.h two input traffic models: random traffic and bursty traffic. Keywords: ATM switches; Load
balancing
1. Introduction
Asynchronous Transfer Mode (Am) is a connection-oriented switching and multiplexing principle. In an ATM network, fixed size short packets called cells are used to transfer information across the network. An N x N ATM switch is an ATM Layer equipment connected to N input lines and N output lines. An ATM switch transfers a cell from any one of the input lines to any one of the output lines. An important class of ATM switch architectures is the output buffered switch architecture [ 3,4,6]. Recently an output buffered ATM switch called the ATOM switch has been proposed by Suzuki et al. [lo]. An * Corresponding
author.
Email:
[email protected].
’ This work was done while the author was visiting the C&C Research Laboratories of NEC USA Inc. during the summer of 1992.
8 x 8 prototype of the switch has been built [5]. Another architecture that has a number of ATOM switch elements operating in parallel has been proposed by Aramaki et al. [ 11. The line speed for this architecture can be S times the possible line speed for the architecture presented in [ lo], S being the degree of parallelism. A second advantage of this architecture is that it is capable of providing more’buffer per output line than the architecture described in [ lo]. The architecture described in [ 1] may lead to uneven disc tribution of cells in the buffers of the switch elements that operate in parallel. In this paper, we propose a threshold-based method for load balancing in the buffers of the parallel switch elements. Our simulation results show that the proposed load balancing method reduces the cell loss probability significantly. The proposed method is simple and easy to implement. We observe that the subject of load balancing
0169-7552/97/$17.00Copyright @ 1997Elsevier ScienceB.V. All rights reserved. SO169-7SZ2(96)00081-5
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has been studied often in the engineering literature and remains a vital force that guides many design decisions. Some examples of this (mainly relating to interconnection networks, call setup times in telecommunications and distributed computing systems) may be found in [ 7-91. The organization of the paper is as follows. In Section 2, we describe the switch architecture under study. In Section 3, we describe the operation of the switch using mathematical notations. In Section 4, we describe the threshold-based load balancing method. In Section 5, we present our results.
2. Description
of the switch
We describe an ATM switch consisting of a number of ATOM switch elements operating in parallel [ lo]. The structure of the ATOM switch is depicted in Fig. 1. This is basically an output buffered switch and the reader is referred to [4] for a general description of these and other types of switches. For the operation of the switch, time is assumed to be slotted. Our unit of time is the duration of a slot. Cells arrive at the switch input lines at the beginning of a slot. It takes the duration of a slot for the arrival of a complete cell. At each input line, only one cell can arrive in one time slot. A cell in an input line is converted from the serial form to the parallel form by a S/P converter shown in Fig. 1. The heart of the switch is a multi-bit bus. The input cells are broadcast on the bus. Time division multiplexing technique is used by the N input lines to access the bus to broadcast cells on the bus. For each output line there is a dedicated buffer. The buffer is necessary since more than one cell that arrive in the input lines in the same slot can have the same output line as destination. There is an address filter (AF) for each output line. The address filter for output line j allows every cell broadcast on the bus and having output line j as destination to queue in the buffer for output line j. The address filter for output line j prevents cells having destinations other than output line j from queueing in the buffer for output line j. Each output buffer is followed by a P/S converter that converts a cell from the parallel form to the serial form for transmission on the output line. Since there are N input lines, at most N cells can arrive in one slot. If the number of bits in a cell is L
and
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then the maximum possible number of parallel lines in the bus is L. Consequently, if the speed of each input line is V, the required speed of the bus is NVL. If the physically attainable maximum bus speed is Rmax, then the input/outputline speed is limited to V = LR,,,/N. Thus the switch architecture presented in Fig. 1 is not suitable for input/output linespeeds beyond LR,,,/N. Fig. 2 depicts a switch architecture that can support a higher input/output line speed by having a number of ATOM switch elements which operate in parallel. The number of switch elements is denoted by S. For each input line, there is a distributor. A distributor cyclically distributes the incoming cells to the S switch elements. The precise meaning of cyclical distribution is explained later in Section 3. The operation of a switch element is exactly as described above. This architecture makes it possible to support a maximum line speed of V = SLR,,,/N. For each output line there is a cell transmitter. Since cells with a particular output line as destination are now queued in each of the S ATOM switch elements, the cell transmitter has to pick up cells from S distinct buffers. As explained later in Section 3, the cells are to be removed from the buffers and transmitted in a particular order. Otherwise, the cells will leave the switch in a sequence different from the sequence in which they arrived. In Section 3 we describe the operation of the switch in detail. The switch architecture depicted in Fig. 2 has another important advantage over the switch architecture depicted in Fig. 1. There is a limit to the size of buffer per line that the switch depicted in Fig. 1 can have since the switch is built as a set of VLSI chips [5]. The switch depicted in Fig. 2 has a number of parallel switch elements, and so the total size of buffer per line is the sum of the buffer sizes per line per switch element. Thus, we can have a substantially larger buffer per line in the architecture depicted in Fig. 2 compared to the architecture depicted in Fig. 1.
3. Description
of the switch
operation
It is convenient to think of each distributor (see Fig. 2) as operating in cycles whose duration is S time units. The cycles are numbered 1,2,3,. . . . If cycle k begins at time x, then at time x + i - 1, 1 < i 6 S, the distributor for input line j, 1 ,< j < N, would send a
S. Chowdhury,
B. Sengupta/Computer
Networks
Tiia-division
Fig. I. The structure
Distributor For Input 1
and ISDN
Systems 29 (1997)
157-164
159
Bus
of the ATOM
ATOM Switch Element
switch.
Transmitter
1
1
Output Lines
N
Distributor
For Input N
Fig. 2. An ATM
switch
Transmitter
ATOM Switch Element S
architecture
with S switch
cell to switch element i if a cell is available at input line j. Switch ,element i does not receive any ceI1 from the distributors at any other time during cycle k. A cell is distributed immediately after its arrival at the input. Thus, at each distributor, the cells are distributed on a first-come-first-served (FCFS) basis, regardless of the destination. The switch elements are scheduled to receive cells in a cyclic round-robin manner. Whether the elements actually receive cells in a round-robin manner depends on the availability of cells for distribution. If we have a newly arrived cell in every slot then the switch elements will receive cells in a roundrobin manner. However, in reality there will be no cell arrivals in some slots. For this reason, the switch el-
elements
operating
N
in parallel.
ements do not receive cells in a strictly round-robin manner. Hence we say that the switch elements receive cells in a quasi-round-robin (QRR) manner. An output buffer of a switch element receives cells after intervals of length S units (assuming cells are available). The cell arrival process at an output buffer of a switch element can be described as follows. The arrivals occur in a sequence of cycles numbered 1,2,3 ,.... Each cycle is of length S time units. If cycle k begins at time x, then at time x + i - 1, cells arrive at the output buffers of switch element i. The number of cell arrivals in cycle k at output buffer j of switch element i is denoted by Akij where 0 < Akij < N. The set of cells that arrive in cycle k at
160
S. Chowdhuty,
B. Sengupta/Compuler
Networks
output buffer j of switch element i is denoted by Ckii. The Cells in Set Ckii and those in Ck,i+t,,i arrive in their respective buffers after an interval of one time unit. Let US consider the operation of the transmitter for output line 1. The transmitter for output line 1 is responsible for picking up cells from the output buffers for output line 1 in the switch elements and transmit them on output line 1. Assume that the operation of the transmitter begins at time 0. At time 0, cells belonging to the set Ct t t are available in output buffer 1 of switch element 1. At time 0, no cell is available at the output buffers of the other switch elements. The transmitter can immediately begin to act. If the set Ct t t is nonempty then in one time slot the transmitter transmits one cell. At time 1, cells belonging to the set Ctzt become available at output buffer 1 of switch element 2. But, the transmitter must transmit all cells belonging to the set Ct t t before it can transmit any cell belonging to the set Cizt. This is to ensure that cells leave the switch in the same sequence as they arrive at the switch. Depending on the value of A,,1 and on the value of S, it is possible that the cells belonging to the set Czt t would arrive at output buffer 1 of switch element 1 before the transmitter has transmitted all the cells belonging to the set Ct 11. The transmitter, however, must transmit all cells belonging to the sets ~121,~131~. . . 3 Ctst in that order before it can transmit any cells belonging to the set Cztt. So the sets of cells are transmitted by the transmitter for output line 1 in the following order: ~I1I~~121~~131~..~~
CJSl,
c211,
c221,
c231,.
. * , c2SI,
~311~~321~~331~...~
c3S1,
c411,
c421,
c431 I . . . , c4S1.
Thus, the transmitter is implementing a re-sequencing function. For a given input line and a given output line, cells leave the ,switch in tlie same sequenceas they arrive. i L 4. The threshold-based load balancing method Each buffer for an output line is consideredto be in one of two states: lightly-loaded state and heavilyloaded state.qAbuffer is saidto be lightly-loaded if the number of cells in the buffer is lessthan or equal to a threshold T. A buffer is saidto be heavily-loaded if the number of cells in the buffer is greater than a threshold T. There is a load matrix consistingof a total of S x N
and ISDN
Systems 29 (1997)
Buffer
NC
Buffer
OC
/57-164
(Switch Element No)
Decision Fig. 3. The above figure explains the generation of two signals, lmo and lmn, used by the decision circuit. The signal Imn gives the load matrix entry for a newly arrived cell in buffer NC. The signal lmo gives the load matrix entry for a cell stored in the buffer OC. To generate these signals, a load matrix row is selected by a counter that gives the number i of the switch element that is scheduled to receive a cell in the slot under consideration. The destination field of the cell in buffer OC selects a column of the load matrix. The selected load matrix entry is the signal lmo which gives the state of the destination output buffer in the switch element i. Similarly, the signal lmn is generated. The main outputs of the decision circuit are two signals that indicate what to do with the cells in buffers NC and OC (see Algorithm 1 in Fig. 4).
bits. The load matrix has S rows and N columns. We denote the load matrix by L. The matrix element Li,i gives the state of the output buffer for line j in switch element i. The matrix element Lij takes one of two values: 0 and 1. The value 0 standsfor a lightly-loaded buffer. The value 1 standsfor a heavily-loaded buffer. A matrix element is changed (or written) by a switch element, and used (or read) by a distributor. A bit representingthe stateof a buffer is fed back to the load matrix by the switch elements.The feed-back is provided only when there is a change of state for an output buffer. In the load balancing method, when all the buffers are lightly-loaded, the cell service discipline in a distributor is FCFS. When some of the buffers are heavily-loaded, we attempt to direct cells away from the buffers that are heavily-loaded and towardsthe buffers that are lightly-loaded. This leadsto a non-FCFS service discipline in a distributor. However, the switch elementsstill receive cells in a QRR manner. This is accomplishedas follows. Each distributor hastwo finite buffers each of size 1 (Fig. 3).
S. Chowdhury,
E. Senguptu/Cmpurer
Networks
Algorithm for decision if (there IS a cell in OC) { generate signal Imo; if (lmo == 0) { send cell in OC; if (there is an arriving cell) store arriving cell in OC; I else { /‘: Imo== I */ if (there is a newly arriving cell) { generate signal Imn; if (Imn == 0) send arriving cell; else { /* Imn== I */ send cell in OC; store arriving cell in OC; > I 1 return; I /* there is no cell in OC */ If (there is no newly arriving cell) return; I* there is a newly arriving cell */ generate Imn if (Imn == 0) send newly arriving cell; else stcre arriving cell in OC; return; .~ Fig. 4. Algorithm 1. Distributor algorithm to make a decision about sending a newly arriving cell in buffer NC or a cell in buffer OC to a switch element in a slot.
One buffer is for a newly arrived input cell, called NC. The other buffer is for a cell which has arrived in an earlier slot but whose distribution to a switch element has been postponed for the purpose of load balancing. This buffer is called OC. Each of the buffers NC and OC can store: only one ATM cell. At the time of arrival of a new cell, the buffer OC is either empty or has a cell in it. For making a cell distribution decision, we use two signals Imn and Imo. The method used to generate the two signals is explained in Fig. 3. The decision to send the cell in buffer NC or the cell in buffer Of: to a switch element is made according to the algori,thm given in Algorithm 1 (Fig. 4). The algorithm has been written using the syntax of the C language. A significant portion of the algorithm can be executed by a lookahead circuit. In particular, if there is a cell in buffer OC then the signal lmo can be
and
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161
generated before the beginning of the slot for which the decision is being made.
5. Simulation
results
We simulated the ATM switch described in Section 3 for 150 million slots. We considered an 8 x 8 switch with 8 parallel switch elements. In Tables I and 2, we present our main performance metric: number of cells lost per million of incoming cells. We evaluated the performance of the switch in two cases: without load balancing and with threshold-based load balancing. We first discuss the random traffic model. In this model, we assume that a cell arrives in a slot at the input line with probability p independently of other slots and lines. Each output line is equally likely to be a destination of an arriving cell, independently of other cells. For this model, the line utilization u = p. The values of the number of cells lost per million of incoming cells for various values of u are presented in Table I. It is listed under the headings “no load balancing” and “load balancing”. We find from Table 1 that the threshold-basedload balancing method significantly reducesthe number of cells lost. The effectiveness of the load balancing method dependson the value of the threshold. For N = 8, S = 8, B = 8, and u = 0.9, the best results are obtained when the threshold T = 4. We now consider the bursty traffic model. We assume that traffic on each input line is bursty and that it consistsof a sequenceof cycles. Each cycle has an active and an inactive period. The length of an active period is geometrically distributed with mean 1/q. The length of an inactive period is also geometrically distributed with mean l/r. On each input line during an active period, a cell arrives in a slot with probability p independently of other slots and input lines. No cell arrives during an inactive period. The active and inactive periods are assumedto be independent. For this model, the line utilization u = pr/( q + r). In Table 2, we present the number of cells lost per million of incoming cells for the bursty traffic model. In our simulationsaveragecycle length 1/q + 1/r was set to 20. In Table 2, p = 1.0. That is, in an active period, we have a cell arrival in every slot. We find that the number of cells lost is significantly reduced by load balancing. We observe that the number of cells lost
162
S. Chowdhury, Table 1 Random traffic: N
number
B. Sengupta/Computer
B
8 8 8 8
8 8 8 8 8
8 8 8 8 8
0.90 0.90 0.90 0.90 0.85
8 8 8 8 8 8 8
8 8 8 8 8 8 8
8 8 8 8 8 8 8
0.85 0.85 0.85 0.80 0.80 0.80 0.80
Table 2 Bursty traffic:
number
and ISDN Systems 29 (1997)
1.57-164
of cells lost per million
S
8
Network
u
No load balancing
T
Load balancing
49.49
3.44
5 4 3 -
15.500 10.200 10.600
5 4 3
1.290 0.720 0.470
5 4 3
0.180 0.100 0.056
0.33 -
of cells lost per million
N
S
B
P
8 8
8
1.0 1.0 I.0 1.0 1.0 I.0 I.0 I .o 1.0 I.0 I.0 1.0 1.0
0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.90 0.90 0.90 0.90 0.90 0.90
I.0
0.90
8 8 8 8 8 8 8 8 8 8 8
8 8 8 8 8 8 8 8 8 8 8 8
I2 I2 I2 I2 I2 I2 I2 I2 I2 I2 12 I2 I2
8
8
I2
u
depends on the threshold value, and is minimized by a particular threshold value. We now present a study which is aimed at classifying the cells buffered in a distributor in an attempt to understand which type of cells may get lost and vice versa. To understand the dynamics of the thresholdbased load balancing method, we divided into four classes the cells that are stored in the buffer OC in a distributor. The cells that would have gone to a heavily loaded buffer on arrival, but are eventually redirected to a lightly loaded buffer by the load balancing method are called well-directed cells. The cells that would have gone to a heavily loaded buffer on arrival, and are eventually sent to a heavily loaded buffer are called one-one cells. The cells that would have gone to a lightly loaded buffer on arrival and are eventually sent to a lightly loaded buffer are called zerozero cells. The cells that would have gone to a lightly
No load balancing
T
0.0147
6 7 8 9 IO II
Load balancing 0.0000 0.0000 0.0020 0.0020 0.0069 0.0127 -
0.508
-
0.0213 0.0185 0.0148 0.0333 0.0889 0.2454
loaded buffer on arrival and are eventually sent to a heavily loaded buffer are called ill-directed cells. In Tables 3 and 4, the percentage of the different classes of cells obtained by simulation are presented. We observe that the well-directed cells are the ones that are possibly saved from being lost. A significant percentage of cells that are buffered in OC are zerozero cells. This can be explained as follows. Suppose a cell Xt arriving at time t is stored in OC because its destination buffer switch element i is heavily loaded. Suppose at time t + 1 a cell X2 arrives, and the destination buffers of Xt and X2 in switch element i+ 1 are lightly loaded, We send Xt to switch element i + 1. So XI is a well-directed cell. Suppose X2 is immediately followed by a number of cells X3, X4,. . . , X, which arrive at consecutive time slots. Suppose the buffers for the destination of these cells in all the switches are lightly loaded. In this case each of the cells X2, . . . , X,,
S. Chowdhury, Table 3 Random traffic:
classification
3--
s
B
-i8 8 8 8 8 8 8 -
8 8 8 8 8 8 8 8
8 8 8 8 8 8 8 8
Table 4 Bursty traffic: i-S 7
-
8 8 8 8
12 12 I2 I2 12
Networks
of the cells buffered u
T
0.90 0.90 0.90 0.85 0.85 0.85 0.80 0.80
classification B
8 8 8 8 8
B. Sengupra/Compuler
5 4 3 5 4 3 4 3
0.90 0.90 0.90 0.85 0.85
Ill-directed
10.63 10.99 II.50 15.21 15.29 15.55 20.13 20.2 I
P
T
I.0 I .o 1.0 1.0 1.0
5 7 10 6 8
157-164
163
in a distributor
Well-directed
of the cells buffered u
and ISDN Systems 29 (1997)
Zero-zero
0.08 0.13 0.20 0.03 0.05 0.07 0.02 0.03
89.19 88.7 I 88.04 84.73 84.59 84.26 79.81 79.7 I
One-one 0.09 0.17 0.26 0.04 0.07 0.12 0.04 0.05
in a distributor Well-directed
are zero-zero cells. Each of them spend one time unit in buffer OC after arrival and then they are sent to a switch element. As we save XI from a possible loss due to switch element buffer overflow by buffering it temporarily in. OC, we increase by a time unit the delay suffered by each of the cells X2, X3,. . . , X,, which arrive in consecutive slots immediately after X1. It appears that the, above scenario is very common. This explains why a very high percentage of cells are zerozero cells. It is interesting to observe that in all our simulations we have a few ill-directed cells. An illdirected cell faces the following scenario as it passes through a distributor. Consider an ill-directed cell XI. As Xl an-ive:s there is a cell in OC. The switch element destination buffer of X1 is lightly loaded and so is the switch element destination buffer of the cell in OC. The cell in OC is sent and X1 is stored in OC. In subsequent slots, we attempt to send X1 to a switch element buffer that is lightly loaded. However, no lightly loaded buffer is found. Eventually a new cell arrives whose switch element destination buffer is heavily loaded. So we are forced to send X1 to a heavily loaded buffer. In addition to the results discussed in this section, we have developed analytical models to find the delays for the random traffic model as well as the bursty traffic model. We have simulated the switch and found the delays through the switch for both the random and
Ill-directed
6.39 6.03 5.87 6.14 5.90
0.10 0.05 0.03 0.02 0.00
Zero-zero 93.42 93.88 94.10 93.83 94.10
One-one 0.09 0.04 0.00 0.01 0.00
the bursty traffic models. The results from the analysis are very close to the results from the simulation (for both the mean delay and the coefficient of variation of delay). Further, we have simulated the delay suffered by a cell in a switch element and observe that there is hardly any difference between the load balancing case and the case without load balancing. Finally, we have also studied the mean delay suffered by a cell in a distributor buffer. We observe that this delay is relatively small. The details of these results are shown in [2].
6. Discussion
One way to reduce the number of cells lost further is to increase the size of the buffer OC in a distributor. This will reduce the number of ill-directed cells and the number of one-one cells. However, in Section 5 we find that the percentages of ill-directed cells and of one-one cells are very small. So the improvement in system performance by increasing the size of OC is expected to be marginal. From our numerical results, we find that the cell loss probably varies with the value of the threshold. Therefore, for any given traffic scenario, there is an optimal threshold value. Since the pattern of network traffic has a time varying nature, the threshold value should be set dynamically, as changes occur in the net-
164
S. Chowdhury,
B. Sengupu/Computer
Networks
work traffic. Such a dynamic assignmentof the threshold requires a mechanismfor detection of changesin the network traffic. In an ATM network, an admission controller knows both the number and types of caIls currently in progress.Therefore, it may be natural to usethis information to decide the optimal value of the threshold. It is also true that the number and range of traffic scenariosis an ATM network could be very large indeed. Thus some research is needed to break this down into a small number of classes,so that the task of dynamic assignmentdoesnot become too overwhelming. We leave this problem as an item for future research. An alternative to threshold-basedload balancing is to distribute the cells to the switch element buffer that has the smallestnumber of cells. An implementation of sucha load balancing method is much morecomplicated than an implementation of the threshold-based method. Optimal or near-optimal load balancingmethods are unsuitable for high speedswitchesbecauseof implementation problems. The threshold-basedload balancing method with one-cell buffer OC in eachdistributor can be implemented in a practical switch. References [ 11 T. Aramaki, H. Suzuki, S. Hayano and T. Takeuchi, Parallel “ATOM” switch architecture for high speed ATM networks, in: Proc. IEEE ICC’92 (1992) 250-254. [Z] S. Chowdhury and B. Sengupta, Threshold based load balancing in an ATM switch consisting of parallel output buffered switch elements. NEC USA Tech. Rept. No. 93coo7-4-5007-l. 1993. [ 3 1 M.G. Hluchyj and M.J. Karol, Queueing in high-performance packet switching, IEEE J. Selected Areas Commun. 6 (9) (1988) 1587-1597. 141 J.Y. Hui, Switching and Trujic Theory for Integrured Broadband Networks (Kluwer, Boston, MA, 1990). [5] A. Itoh, W. Takahashi, H. Nagano, M. Kurisaka and S. Iwasaki, Practical implementation and packaging technologies for a large-scale ATM switching system,lEEE J. Selected Areas Commun. 9 (8) (1991) 1280-1288.
rend ISDN Sysrenrs
29 (I 997) 157-164
161M.J. Karol, M.G. Hluchyj and S.P. Morgan, Input versus output queueing on a space division packet switch, IEEE Truns. Cornmun. 35 (12) (1987) 1347-1356. (71 K. Qiu and S.G. Akl, Load balancing and selection on the star and pancake networks, in: Proc. 26th Hawaii fniernut. Con$ on S~vstems Science, Vol. 2 ( 1993) 235-242. 181R. Simha and J.F. Kurose, On-line minimization of call setup time via load balancing: A stochastic approximation approach, IEEE Trans. Gmmnn. 42 (2-4) ( 1994) I14111.52. 191 M.G. Sriram and M. Singhal, Measures of the potential for load sharing in distributed computing systems,IEEE Trans. Sojiiare Engineering 21 (5) 1995) 468-475. 1101 H. Suzuki, H. Nagano, T. Suzuki, T. Takeuchi and S. Iwasaki, Output-buffer switch architecture for asynchronous transfer mode, in: Proc. IEEE ICC’89 (1989) 99-103.
ShyamalChowdhury is a computer sci-
entist at IBM Corporation, Austin, Texas. He received a Ph.D. degree in computer science fromthe Universityof Arizona, Tucson, Arizona, in 1990. His research interests include high speed networking and multimedia networking.
Bhaskar Sengupta obtained his doctoral
degreefrom the Operations Research
Department of Columbia University in 19%. He was a faculty member in the department of Applied Mathematics and
,%&tics in theStateUniversityof New YorkatStonyBrookfrom I976to 1981.
Subsequently, he worked in AT&T Bell Laboratories and was a Distinguished
Memberof Technical Staffwhenheleft
in 1990. He has been an adjunct faculty member in Columbia University and has consulted with many companies in New York. He is currently the Head of the Perfor&ncd Analysis Department at the C&C Laboratories, NEC USA. His research interests are in queueing theory and its applications to computer and communications problems.