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Performance comparison criteria for ATM switch models
Computer Networks 34 (2000) 85±95
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Performance comparison criteria for ATM switch models q M. Becker a,b,*, A.-L. Beylot c a
c
Institut National des T el ecommunications, 9, rue Charles Fourier, F-91011 Evry Cedex, France b LIP6 Lab, 5 place Jussieu, F-75230 Paris Cedex, France Laboratoire PRiSM, Universit e de Versailles-St-Quentin, 45 Avenue des Etats-Unis, F-78035 Versailles Cedex, France
Abstract Performance of ATM networks will depend on switch performance and architecture. In this paper a set of 11 questions is presented in order to be able to study performance. It is necessary to clearly identify the main characteristics of switch architecture and trac which are considered so as to be able to derive relevant comparisons. The questions concern the level of study, the placement of the memory, the monopath or multipath architecture, the uniformity of input stream, the destination hypotheses, the routing rules inside the switch, the eventual resequencing, etc. In case of cell level study and output buers, the answers to the six main questions lead to a tree including 14 realistic switch and trac types. A survey of the modelling method for these cases is then presented. In order to illustrate the methodology, few results are given in some of the realistic cases and some general conclusions appear to be pertinent: importance of trac asymmetry, best performance for multipath switches, use of path reservations inside the switch. Ó 2000 Published by Elsevier Science B.V. All rights reserved. Keywords: ATM; Switches; Interconnection networks; Analytic models; Bursty trac; Finite capacity queues; Performance evaluation
1. Introduction When dimensioning ATM switches, a model has to be realised and studied in order to evaluate the switch performance. Several studies were realised [2,12,30]. It is not always easy to compare the results, because there are many switch architectures, many switch operations, and many kinds of trac hypotheses. The aim of this paper is to prepare a comparison of the performance results. It is necessary to classify the most common switch architectures, the trac assumptions and the modelling hypotheses. q
This work was partly supported by a CNET grant. Corresponding author. E-mail addresses: [email protected] (M. Becker), [email protected] (A.-L. Beylot). *
This study is not a survey of existing switches. It is a survey of the main questions that have to be asked in order to characterize the performance model parameters. Section 2 presents a set of questions that have to be answered so as to know the placement of the switch model inside the tree of the possible switches and trac. Section 3 presents a subtree of this tree. Section 4 explains what are the most common cases of modelling problems and methods. Finally, a set of the most common switches and some of their performance results are presented in Section 5. Let us repeat that we do not intend to classify the architectures of ATM switches but to identify the characteristics which are important for performance results. It was proved that performance results are dependent on whether the network is monopath or multipath. So, for us, an important
1389-1286/00/$ - see front matter Ó 2000 Published by Elsevier Science B.V. All rights reserved. PII: S 1 3 8 9 - 1 2 8 6 ( 0 0 ) 0 0 0 9 8 - 0
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question will be to ask whether the network is monopath or not. So we shall present a monopath switch that is a Delta network and a multipath switch that is a Clos network. The results might be dierent for another architecture, but the main modelling problems would probably be the same. 2. Description of the questions 2.1. Question A: level of study The ®rst question to be asked concerns the level of study. Question A: Is the study at the cell level, at the burst level or at the call level? It is well known that in ATM networks, there are dierent levels corresponding to dierent time scales. A call can be considered as a set of bursts. A burst is a set of cells (see Fig. 1). When studying a switch at the cell level, an event occurs during one slot. During a call, there will be a huge number of cells, so, when studying a switch at the cell level, the times that will be considered will be very large, when compared with those of a cell level study. It is not possible to consider at the same time two dierent levels of study, such as call level and cell level [25], because an event at the call level implies too many events at the cell level. The dierent levels will lead to dierent conclusions: While a cell level study will help dimen-
Fig. 1. The three dierent levels.
sioning the switch, a burst level study will lead to source policing or congestion avoidance and a call level study will lead to call acceptance control (CAC) and network planning. 2.2. Questions B and C: memory placement The second and third questions to be asked concern the switch architecture [12,32]. Where are the buers placed? There are several types of switch architectures: external buers [19,29,33] or internal buers [15,20]. In case of internal buers (which seems to be the most common choice) there are dierent technologies. If in one slot one switching element can switch only one cell, input buers are necessary [20,21,35], if in one slot several cells arriving on several inputs may be simultaneously switched, then output buers are necessary [21]. Another possibility, which leads to better performance but higher cost, is a common shared memory in the switch [16,17,27]. Question B: Are buers internal or external? Question C: In case of internal buers, in a switching element are the buers output buers or input buers, or is there a common shared memory? 2.3. Question D: monopath versus multipath switch The next very important question, concerns the number of paths that exist between each input and each output. Question D: Is the switch monopath or multipath? The congestion problems will be very dierent if the switch is monopath, or if it is multipath. Delta symmetric networks are well-known examples of monopath networks. Each switching element has n input ports and n output ports. Fig. 2 represents a two-stage Delta network. Let N be the global number of input/output ports and e the number of stages. The following relation holds: N ne . Let us note D N ; n for such a switch. Figure 3 represents an example of a multipath network: a 3 stage Clos network [14]. If it is multipath, each time there is a high load on one path, the load may be split over several paths. A Clos network can be described by the total number of
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2.4. Questions E, F and G: input stream laws
Fig. 2. Example of a two-stage Delta network.
Fig. 3. Example of a three-stage Clos network.
input/output ports N, the number of input ports of the ®rst stage switching elements a and the number b of paths for one origin/destination pair. Let us note C N ; a; b for such a con®guration. In the case of a monopath network, two different paths may have a common link and if two bursts arrive at the same time on the two dierent paths, there will be a serious problem on the common link. On the other hand, a multipath switch may need resequencing. Since several cells of the same call may use dierent paths, they may arrive in the output link out of order. They will have to be reordered.
The input stream law has to be de®ned. Question E: What is the input stream law? This is one of the most dicult problems when designing ATM networks: the future ATM trac is unknown. There are some hints about source models for ATM trac, but trac coming into one switch will not mostly come from sources, it will mostly come from the output of other switches. There are long term correlations, but for studies at the cell level, the time period is short enough not to take care of long term correlations. It is often assumed that source trac is bursty. Let us consider a Markov model with two states: silence and burst. Silences are geometrically distributed with parameter q (mean Ls ), bursts are geometrically distributed with parameter p (mean Lb ). A worst case trac is the case when during one burst there is one cell in each slot. Let us call this trac interrupted deterministic process trac (IDP). The output stream from a switch with IDP input stream is not simple [4]. It can be sometimes approximated by an interrupted Bernoulli process (IBP) trac [5]. This trac can be viewed as a IDP for which in a burst there are cells which constitute a Bernoulli process with parameter a. In case of a study at the cell level, which does not need to take into account long term correlations [26], a reasonable hypothesis for input stream is IDP or IBP. Question F: Are input streams independent? Question G: Are input stream loads uniform? Let us assume for example that the input stream is IBP trac on each link. It is important to know whether those input streams are independent, and whether their parameters are the same. 2.5. Questions H, I and J: destination distributions The next three questions concern the distribution of destinations. From them and from the answer to question F, the output loads will be deduced. Question H: Are destinations uniformly distributed? Even if the destination is uniform when the average is made over a long enough period of time,
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it is not necessarily uniform when averaged over a relatively short time. When studying congestion problems so as to dimension a switch, it may be important to consider the case when, during some time period, the load can be asymmetric. Question I: Do the cells of a same burst have the same destination or not? The answer to this question depends on whether the bursts on the input links come from the same source or not. If an input burst is a superposition of many dierent calls, those cells may go to different output links. In the following let us name those two cases, correlated destinations and uncorrelated destinations. Question J: In case of correlated destinations, are there eventual con¯icts between bursts? If the cells of a same burst go to the same output, and if it happens that two bursts go to the same output, there will be a serious problem. This should be very rare, because of the reservation. Reallistically the answer to this question will be no, except in the case when bursts consist of a superposition of several bursts corresponding to dierent calls. Let us present four cases of non-uniform load, non-uniform-destinations and correlated-destinations trac. During a time interval that is large when compared to a slot the trac is asymmetric. We considered four types of asymmetric trac for this paper: single source to single destination (SSSD), SSSD embedded in uniform trac, multiple source to single destination (MSSD) and multiple source to multiple destination (MSMD). SSSD means that cells belonging to a given burst are assumed to be directed to the same output port and that only one burst can be directed to a given output port. Fig. 4 shows heavy SSSD trac embedded in uniform trac ¯ows. MSSD will be the case when several input links send trac to the same output link, which will be heavily loaded. In case of bursty trac, the answer to question J is yes. MSMD will be the case when there are several high load trac outputs corresponding to several high load trac inputs. This comes from the fact that high load input stream may correspond to a superposition of several bursts.
Fig. 4. SSSD trac + uniform trac.
2.6. Question K: correlated versus uncorrelated routing The last important question concerns the routing inside the switch. It is valid for multipath switches. Question K: In case of multipath switches, how are cells routed? How are paths chosen? Will the cells of a burst be distributed among the dierent possible paths or not? It might seem that if the cells of the same burst follow the same path, a multipath switch is not very useful. There are two reasons why this is not true: · If the cells of the same burst follow the same path, there is no need to resequence and the resequencing cost of the multipath switch is avoided. · The problem with monopath networks, even if reservations are properly done and origin/destination pairs are dierent, is due to the fact that two dierent paths may have a common link [8], so two bursts may use the same inside link. This problem may be avoided if the switch is multipath and if the cells of the same burst are uniformly distributed among the dierent possible paths. In fact, it would appear that multipath switches are useful in case of asymmetric trac. The case of correlated routing (burst routing) and the case of uncorrelated routing (cell routing) are both important. They lead to dierent models, dierent performance results and dierent complexities of implementation.
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3. The subtree of the realistic cases for cell level study, output internal dedicated buers and given input streams laws The answers to questions A to K generate a tree of eventual switch and trac types (Fig. 5). Let us consider a subtree of realistic cases. In Section 5, Table 1 will give some numerical results for a set of examples named {1}±{11}. Let us assume that the answer to question A is: cell level study and that it is intended to dimension the switch. Let us assume that buers are internal and output dedicated buers, which is a compromise between performance needs and hardware complexity. Let us assume that input streams are independent and input stream laws are given. For cell level study, output internal dedicated buers, and given trac laws, Fig. 5 presents the tree of the main cases that lead to dierent modelling methods and problems and dierent types of solutions. It takes into account questions D, I and K (if the network is multipath). When averaging over a very large period, the trac load is probably uniform. But when averaging over a shorter time, this is probably not true. The asymmetry does not introduce a major diculty in modelling problems. It increases the computation complexity. Several types of queues have to be studied in each stage. The solutions are
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not very dierent, but mostly dierent values of the parameters have to be considered. So Fig. 5 does not present in each case, the answer to question G. It will present some cases of asymmetric trac. This leads to 14 cases. 4. Description of the modelling methods in some of the realistic cases The usual method is the following: ®nd what is Markov and solve the Markov chain. What is Markov may be rather complex, and the solution may be dicult to get. Usually the solution is ®rst derived for a ®rst stage element, the law of the output stream is derived from the input stream law, then the law of the input stream into the second stage has to be computed from the output stream of the ®rst stage, by superposition. 4.1. Uniform trac case (uniform input load and non-correlated destinations) This case was the most studied. Input trac is assumed to be independent, input load is uniform and cells of a given burst are assumed to be uniformly directed over all the output ports of the switch. This trac case may be both studied in the monopath [1,27,28,31] or in the multipath case [5].
Fig. 5. Tree of the main questions, for a cell level study, internal, output, dedicated buers and a given input stream laws.
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In the multipath case, uniform assumption automatically leads to cell routing (no call identi®cation). In this trac case, the resequencing cost is negligible for multipath switches since the time interval between two consecutive cells directed to the same output port is high. The same models are consequently used in both cases. Those studies are mainly based on [21]. In this paper, a comparison of input and output buering strategies is proposed. In the output buer case, an exact model of a switching element is proposed; input streams are assumed to be of Bernoulli type and queues to be in®nite. It leads to the study of a n ÿ Geo/D/1 queue with arrival before departure. Extensions of this work were then presented in the ®nite capacity queue with a dispatching discipline wherein queued cells are sent before arriving cells are added to the queue in order to take into account the switching time itself. Approximate models were then proposed for the whole switch by approximating the output stream of such queues by simple Bernoulli processes [6,23]. The bursty trac input case is a direct extension of the previous model. If the input stream is of IDP or IBP type, an exact model of a switching element can be derived from the study of a n ÿ IBP/D/1/M queue [5]. More generally, if the input process is a discrete Markov arrival process (DMAP), a model of a switching element can be derived from a DBMAP/D/1/M queue [10]. It has been shown that the output process of such queues is of DMAP type but the model of the whole switch cannot be solved. The main problem comes from the characterization of the interstage trac. Approximations of those processes were presented in the literature. Bernoulli, IDP or IBP approximations were proposed, the parameters of those processes are ®tted from the study of the actual output process (interdeparture time, busy and idle period duration). Those approximations lead to good results. However, it was shown that even if the input process into a switching element is Bernoulli, the busy period duration is not geometrically distributed [11]. Consequently new approximations were proposed: a three-state Markov chain with two states for the busy period and one state for the idle period [16,31]. It leads to the same results as the previous models. This
comes from the fact that this output process is not the input process of a given queue of the following stage. This process will be split and even if the output process is bursty, the input process for the following stage will be less bursty. This trac case seems to be quite optimistic since the burstiness of the input stream will mostly be absorbed by the random choice of the output port. Consequently, the performance results do not really depend on the burst length. At the cell level scale, it should be better to consider that most of the input stream oered to a given input port will be directed to one (or a few) output port. We shall now present models for some examples of such asymmetric trac cases. 4.2. Non-uniform trac Let us consider some typical cases when trac is asymmetric. 4.2.1. SSSD trac This trac type was mostly studied for unbuffered switches [22]. A model of a ®rst stage switching element can be derived [8] for monopath networks. In the IBP input stream case, a Markov chain is the vector of the following numbers: · the number of cells in the queue, · the number of `ON' sources, · the number of bursts directed to a given output port of a ®rst stage switching element, · the number of active sources in the other switching elements, · the numbers of bursts in such switching elements directed to the output ports of the switch which can be accessed by the tagged output port. In the multipath case, two solutions may be considered (question K). In the Clos network case, if cells belonging to a given burst use the same path and if the number of paths b is greater than or equal to 2a ÿ 1 (where a is the number of input ports of a ®rst stage switching element), the results are straightforward (cell delay will be 3 units of time (i.e., 3 slot period) and the cell loss probability 0). The proof of this result is the same as the circuit switching's one. If the routing is uncorre-
M. Becker, A.-L. Beylot / Computer Networks 34 (2000) 85±95
lated, a model can be derived [9]. The ®rst two stage models look like the SSSD models embedded in a uniform trac (see Section 4.2.2). The model proposed for the third stage represents a constant service time queue with ®nite capacity, whose source is the output stream from the model of the two ®rst stages. This source model is an IBP=Geo D=b=b queue in the IBP input stream case, b is the number of paths, the parameter of the geometric law is ®tted to the response time of the ®rst two stages obtained by the previous models. So, SSSD trac leads to models that can be solved. 4.2.2. SSSD trac embedded in a uniform trac This trac case was ®rst considered for unbuered switches or for input buers switches [13,22,28]. Multipath switches are studied in [7]. In this paper, only the uncorrelated routing case has been investigated. Approximate models can be derived using the same kind of models as in the uniform trac case. In fact, the parameters have to be computed for the dierent trac types, it leads to the study of IBP1 n ÿ IBP2 =D=1=M queues. The performance criteria are derived for the dierent classes of customers. This trac case has been investigated neither in the monopath case nor in the multipath case with correlated routing since it is not easy to characterize the high trac inside the switch. The problem comes from the superposition of other trac streams. 4.2.3. MSSD trac For monopath switches, a model has been presented in [8]. A Markov chain is the vector of the following numbers: · the number of cells in the queue, · the number of `ON' sources, · the number of bursts directed to a given output port of a ®rst stage switching element. 4.2.4. MSMD trac In fact, it is more realistic to consider MSMD trac for which the input stream corresponds to the superposition of several bursts [1,13,34]. A ®rst study has been presented in [3]. In this study, some input links are oered a high load that will be di-
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rected to few output ports. This MSMD trac is embedded in a uniform trac. Only the uncorrelated routing multipath case has been investigated. An analytical model has been proposed, it leads to the study of IBP1 n ÿ IBP2 =D=1=M queues. The performance criteria are derived for high load trac and for the low load trac. This trac case should be studied in the monopath case and other MSMD trac cases have to be determined and studied in order to properly dimension ATM switches. 5. Results A few performance results are presented in Table 1. The delay unit is a slot period. Results were derived from analytical solutions when it was possible ({1},{5},{6},{9}), from event driven simulations when it was not. Simulation lengths were chosen so that relative con®dence intervals were less or equal to 10%. Lb and Ls are the mean burst length and silence length. a is the probability in one slot to get a cell during a burst. M i means the memory size at stage i. Delay shows the mean delay time and Loss the cell loss probability. The switch hardware is easier to design and less expensive if switching elements are identical. In the monopath case, it was shown that in the uniform trac case, the best performance results were obtained when the buer size of the dierent stages are equal [18]. This is not true in non-uniform trac cases. However, in those cases, performance results are so bad that it is not possible to dimension the buers in order to lead to convenient performance. Consequently, for monopath cases, only the case when all the buer sizes are identical has been studied. Results are presented for Delta networks with a global number of input ports N equal to 64 and switching elements with 4 input ports and 4 output ports D 64; 4. The number of stages is consequently equal to 3. In the multipath case, performance results heavily depend on the placement of the memory in the dierent cases. Considering a global amount of memory, we tried to obtain the best placement of this memory among the 3 stages of a Clos network. Consequently in Table 1 results are presented for the best value for the memory
Structure
D 64; 4
D 64; 4
D 64; 4 D 64; 4 C 128; 4; 8
C 128; 4; 8
C 128; 4; 8
C 128; 4; 8
C 128; 4; 8
C 256; 4; 8 C 128; 4; 8
No.
{1}
{2}
{3} {4} {5}
{6}
{7}
{8}
{9}
{10} {11}
Table 1 Performance Results 5
1.25
66.7 800 25 1.05 1.33
20 4
±
25
12.5
25 25 1.25
12.5
Ls
100 100 100
±
100
100
100 100 5
100
Lb
±
a
1. 1.
0.9 0.9 0.9
0.9
0.9
0.9 0.9 1
0.9
1
Uniform (Bern) Uniform (IBP) SSSD MSSD Uniform (Bern) Uniform (IBP) SSSD Uncor. rout. SSSD Corr. rout. SSSD + Uniform SSSD Uniform MSSD MSMD (Bern) High trac Low trac
Trac type
±
3 6
5
8
10
400 400 10
30
30
M(1)
±
2 7
5
7
10
400 400 10
30
30
M(2)
56 46
28
±
6
32
400 400 32
30
30
M(3)
11.65 4.89
5.73 3.12 12.67
3
4.14
5.45
208.50 288.00 5.33
8.04
7.63
Delay
2:6 10ÿ4 1:4 10ÿ5
4:9 10ÿ6 5:0 10ÿ7 2:8 10ÿ2
0
7:7 10ÿ7
1:8 10ÿ7
2:8 10ÿ2 5:6 10ÿ2 9:4 10ÿ8
6:6 10ÿ7
5:6 10ÿ8
Loss
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M. Becker, A.-L. Beylot / Computer Networks 34 (2000) 85±95
size on the three stages (the best value is the one that leads to the lowest loss probability, the memory size is a number of cells). In the multipath case, several parameters were chosen. In most of the results presented in this paper, the switch has 128 input ports and 128 output ports. In [5], it was shown that the best performance results are obtained when the number of input ports of the switching elements of the ®rst stage have 4 input ports and 8 output ports. The con®guration which is studied in the present paper is consequently a C 128; 4; 8 Clos switch. 5.1. Monopath switch analysis In the uniform trac case [8], it is shown that even with small buer sizes the cell loss probability is quite low. In the SSSD trac case [8], performance results are quite bad even with large buer size. This is due to the fact that as soon as two bursts are directed to the same output port of a given switching element, the queue length increases and cells will be lost. In the MSSD trac case [8], performance results are bad even with large buers for the same reasons as in the previous trac case. 5.2. Multipath switch analysis In the uniform trac case [5,6], the resequencing cost is negligible since the time interval between two consecutive cells coming from the same input port and directed to the same output port of the switch is large. In this trac case, performance results are quite good even with small buers. In the SSSD trac case, in case of non-correlated routing [6], the resequencing cost is not too high [24]. Expected resequencing delay is 1.2 slots and the resequencing loss rate is 10ÿ7 . This trac case is quite optimistic but leads to good performance results even with small buers. If the switch is large enough, and correlated routing is implemented, the performance is still better of course. In the SSSD trac (high trac) embedded in a uniform trac (low trac) case, the performance criteria are estimated for the two kinds of trac. The cell loss probability of the high trac depends
93
on the input load and on the mean burst length. The cell loss for high trac is larger than for the low trac. The resequencing cost is negligible for the low trac and for the high trac if the burst length and the cell loss probability are not too high. Estimation of the number of desequenced cells is 2% of the number of cells, in this trac case [7]. In the MSSD trac case, simulations results were presented in [18] for multipath switches with uncorrelated routing. Performance is better than in the monopath case. However the cell loss probability is still very high even with large buers. Most of the memory size should be placed in the last stage since bursts are split in the ®rst stage switching elements. Consequently, the performance criteria are quite good in the ®rst two stages. But as soon as two bursts are directed to the same output port of a third stage switching element, the queue length increases and cells will be lost. Let us hope that VC allocation will avoid this problem. In the correlated routing case, the performance results should mainly depend on the routing algorithm. However, the cell loss probability will be high even with large buers. In the MSMD trac case presented in this paper [3], only Bernoulli trac has been assumed. It is shown that in this trac case the performance results highly depend on the input load. The cell loss for the heavy trac is larger than for the low trac. The resequencing cost is negligible for low trac and should be estimated in a bursty trac case for high trac (in the Bernoulli case presented in this paper and for large switch this cost is negligible). 6. Conclusion A set of questions has been presented which may help to position the performance study of a switch when compared with others. Some questions appeared to be more important than others. In order to dimension a switch, performance has to be studied at the cell level. For the time scale that is useful for this study, trac asymmetry may be important. Then the most important question is to ask whether the network is multipath or not.
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When trac is uniform, monopath or multipath switches lead to good performance. When trac is asymmetric a monopath switch leads to unacceptable performance. Of course a multipath switch is more expensive because of the resequencing cost and because of the hardware cost, but it is the only reasonable choice. This was proved, by studying the performance of some Clos networks, and some Delta networks. In case the switch architecture is dierent, but is either multipath or monopath, the main performance problems would be the same. For multipath switches, the results that were presented correspond mostly to non-correlated routing. A quite good solution, in case of burst or call path reservation is implemented inside the switch (i.e., ABT), would be of course correlated routing. Performance models in those cases would be tractable, but have not been solved yet. A methodology has been presented. Further experiments would be valuable. It is necessary to design such methodology, because when designing a new switch, the comparison of its performance with other switch performance depends upon so many input parameters, that it is rather unsafe to reach a conclusion. A set of questions was presented in order to try to be fair when comparing performance. In order to illustrate the methodology a few results were presented, but this was not the objective of the paper. There is still a lot of work to do. There are still a lot of switches that might be designed. For example, switches with more than three stages might be compared with the switches that were studied. The routing inside the switch is very important and other routing ways might be designed, so that answers to question J might be improved. References [1] S. Bassi, M. Decina, A. Pattavina, Performance analysis of the ATM shueout switching architecture under nonuniform trac patterns, in: Proceedings IEEE Infocom'92, Florence, Italy, 1992. [2] M. Becker, A.L. Beylot, A. Ziram, Switching networks for ATM, Invited Tutorial, in: Proceedings Fourth Open Workshop on High Speed Networks ENST/Stuttgart University, Brest, France, 1994, pp. 1±22.
[3] A.L. Beylot, I. Kohlenberg, M. Becker, Performance analysis of an ATM switch based on a three-stage Clos interconnection network under non-uniform trac patterns, in: S. Thome, A. Casaca (Eds.), Proceedings IFIP Broadband Communications BC-94, Paris, France, NorthHolland, Amsterdam, 1994, pp. 205±224. [4] A.L. Beylot, I. Kohlenberg, M. Becker, A performance analysis of an ATM Clos switch under bursty trac, in: D. Kouvatsos (Ed.), Proceedings IFIP Workshop on Performance Modelling and Evaluation of ATM Networks, Bradford, UK, 1994, pp. 245±260. [5] A.L. Beylot, M. Becker, Performance analysis of an ATM Clos switch under bursty trac (symmetric IBP arrivals), in: Proceedings IEEE Conference BSS'95, Poznan, Poland, 1995, pp. 108±117. [6] A.L. Beylot, M. Becker, Dimensioning an ATM switch based on a three-stage Clos interconnection network, Annals of Telecommunications 50 (7±8) (1995) 652±666. [7] A.L. Beylot, I. Kohlenberg, H. Yaiche, M. Becker, Performance analysis of an ATM Clos switch under asymmetric bursty trac, in: Proceedings of IFIP Conference WATM'95, Paris, France, December 1995, pp. 255±262. [8] A.L. Beylot, I. Harfouche, M. Becker, Performance analysis of monopath ATM switches under correlated and uncorrelated trac patterns, in: Proceedings 5th Open Workshop on High Speed Networks ENST/Stuttgart University, Paris, France, 1994, pp. 7.1±7.10. [9] A.L. Beylot, I. Harfouche, M. Becker, Performance analysis of multipath ATM switches under bursty single source to single destination trac, RR Prism, no 97003, January 1997. [10] C. Blondia, O. Casals, Statistical multiplexing of VBR sources: a matrix-analytic approach, Performance Evaluation 16 (13) (1992) 5±20. [11] F. Bonomi, S. Montagna, R. Paglino, Busy period for an ATM switching element output line, in: Proceedings IEEE Infocom'92, Paper 4C.2, Florence, Italy, 1992. [12] C. Dhas, V.K. Konangi, M. Sreetharan, Broadband Switching, Architectures, Protocols, Design, and Analysis, IEEE Computer Society Press Tutorial, 1951±1991, 513 pp. [13] D. Chen, J. Mark, A buer management scheme for the SCOQ switch under nonuniform trac loading, in: Proceedings IEEE Infocom'92, Florence, Italy, 1992. [14] C. Clos, A study of non-blocking switching networks, Bell System Tech. 32 (1953) 406±424. [15] M. D'Ambrosio, R. Melen, Performances analysis of ATM switching architecture: a review, in: COST 224, Final seminar, Paris, France, 1991. [16] M. De Marco, A. Pattavina, Performance analysis of ATM multistage networks with shared queueing under correlated trac, in: Proceedings ITC'14, Antibes Juan les Pins, France, 1994, pp. 601±610. [17] A. Eckberg, T. Hou, Eects of output buer sharing on buer requirements in an ATDM packet switch, in: Proceedings IEEE Infocom'88, paper 5A.4. [18] I. Harfouche, Comparaison de plusieurs types d'architectures de commutateurs ATM, DEA Report Conception
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[19] [20] [21] [22] [23]
[24]
[25]
[26] [27]
[28] [29] [30] [31]
des Systemes Informatiques Avances, CNAM August 1995, pp. 1±43. A. Huang, S. Knauer, Starlite: a wideband digital switch, in: Proceedings Globecom'84, pp. 5.3.1±5.3.5. H. Jenq, Performance analysis of a packet switch based on single-buered Banyan network, IEEE J. Selected Areas Commun. 1(6) (1983). M. Karol, M. Hluchyj, S. Morgan, Input vs. output queueing on a space-division packet switch, IEEE Trans. Commun. 35(12) (1987). H.S. Kim, A.L. Garcia, Performance of buered banyan networks under non-uniform trac patterns, in: Proceedings IEEE Infocom'88, pp. 344±353. H. Kim, M.G. Widjaja, A. Leon-Garcia, Performance analysis of output buered banyan networks with arbitrary buer sizes, in: Proceedings of IEEE Infocom'91, Bal Harbour, FL, 1991. J. Kohlenberg, Caracterisation du tra®c ATM. Performances des commutateurs ATM dans des conditions nonuniformes de fonctionnement, PhD report, Paris VI University, 1996. P. K uhn, Performance modelling and trac engineering for broadband communications networks, in: S. Thome, A. Casaca (Eds.), IFIP Broadband Communications, Paris, France, 1994, pp. 245±274 (Invited paper). W. Leland, M. Taqqu, W. Willinger, D. Wilson, On the self-similar nature of Ethernet trac, in: Proceedings ACM Sigcomm'93, San Francisco, CA, 1993. A. Monterosso, A. Pattavina, Performance analysis of multistage inter-connection networks with shared-buered switching elements for ATM switching, in: Proceedings IEEE Infocom'92, Florence, Italy, 1992. T. Morris, H. Perros, Performance modelling of a multibuered banyan switch under bursty trac, in: Proceedings IEEE Infocom'92, Florence, Italy, 1992 (Paper 3D.2). J. Patel, Performance of processor-memory interconnections for multi-processors, IEEE Trans. Comput. 30 (10) (1981) 542±545. S. Rao (Ed.), State of the Art Issues in ATM Trac, Telecommun. Syst. 5 (1996). T. Theimer, A new model for the analysis of multistage ATM fabrics, in: Proceedings of ITC'14, Antibes Juan-lesPins, France, 1994.
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[32] F. Tobagi, Fast packet switch architectures for broadband integrated service digital networks, in: Proceedings of the IEEE 78(1) (1990). [33] F. Tobagi, T. Kwok, The tandem banyan switching fabric: a simple high-performance fast packet switch, in: Proceedings of IEEE Infocom'91, Bal Harbor, FL, 1991 (Paper 11A.2). [34] H. Yamashita, H. Perros, S. Hong, Performance analysis of a shared buer ATM switch under bursty arrivals, in: Proceedings of ITC'13, Copenhagen, Denmark, 1991. [35] H. Yoon, K. Lee, M. Liu, Performance analysis of multibuered packet-switching networks on multiprocessor systems, IEEE Trans. Comput. 39 (3) (1990) 319±327. Monique Becker graduated from Ecole Normale Superieure de Jeunes Filles in 1968, passed the mathematics ``agregation'' and received the State Doctorate degree from the University of Paris VI in 1976. She joined the National Center of Scienti®c Research were she had the responsibility for a group of researchers working on performance evaluation. In 1987, she joined France Telecom University where she got the position of Professor and Chairman of the Computer Science Department. She is managing a group of researchers (including professors and Ph.D. students) working on performance evaluation of computer and telecommunication networks. Their main interest concerns ATM, IP and satellite networks. AndreÂ-Luc Beylot received the engineer degree from the Institut d'Informatique d'Entreprise in 1989 and the Ph.D. degree in computer science from the University of Paris VI in 1993. From 1993 to 1995 he works at the Institut National des Telecommunications (France Telecom University), and from 1995 to 1996 at CNET (France Telecom Research Laboratory) in Rennes. Since 1996, he is an associate professor at PRiSM Laboratory of the University of Versailles. His interests are in the performance of communication networks, especially with regard to ATM and mobile networks.
www.elsevier.com/locate/comnet
Performance comparison criteria for ATM switch models q M. Becker a,b,*, A.-L. Beylot c a
c
Institut National des T el ecommunications, 9, rue Charles Fourier, F-91011 Evry Cedex, France b LIP6 Lab, 5 place Jussieu, F-75230 Paris Cedex, France Laboratoire PRiSM, Universit e de Versailles-St-Quentin, 45 Avenue des Etats-Unis, F-78035 Versailles Cedex, France
Abstract Performance of ATM networks will depend on switch performance and architecture. In this paper a set of 11 questions is presented in order to be able to study performance. It is necessary to clearly identify the main characteristics of switch architecture and trac which are considered so as to be able to derive relevant comparisons. The questions concern the level of study, the placement of the memory, the monopath or multipath architecture, the uniformity of input stream, the destination hypotheses, the routing rules inside the switch, the eventual resequencing, etc. In case of cell level study and output buers, the answers to the six main questions lead to a tree including 14 realistic switch and trac types. A survey of the modelling method for these cases is then presented. In order to illustrate the methodology, few results are given in some of the realistic cases and some general conclusions appear to be pertinent: importance of trac asymmetry, best performance for multipath switches, use of path reservations inside the switch. Ó 2000 Published by Elsevier Science B.V. All rights reserved. Keywords: ATM; Switches; Interconnection networks; Analytic models; Bursty trac; Finite capacity queues; Performance evaluation
1. Introduction When dimensioning ATM switches, a model has to be realised and studied in order to evaluate the switch performance. Several studies were realised [2,12,30]. It is not always easy to compare the results, because there are many switch architectures, many switch operations, and many kinds of trac hypotheses. The aim of this paper is to prepare a comparison of the performance results. It is necessary to classify the most common switch architectures, the trac assumptions and the modelling hypotheses. q
This work was partly supported by a CNET grant. Corresponding author. E-mail addresses: [email protected] (M. Becker), [email protected] (A.-L. Beylot). *
This study is not a survey of existing switches. It is a survey of the main questions that have to be asked in order to characterize the performance model parameters. Section 2 presents a set of questions that have to be answered so as to know the placement of the switch model inside the tree of the possible switches and trac. Section 3 presents a subtree of this tree. Section 4 explains what are the most common cases of modelling problems and methods. Finally, a set of the most common switches and some of their performance results are presented in Section 5. Let us repeat that we do not intend to classify the architectures of ATM switches but to identify the characteristics which are important for performance results. It was proved that performance results are dependent on whether the network is monopath or multipath. So, for us, an important
1389-1286/00/$ - see front matter Ó 2000 Published by Elsevier Science B.V. All rights reserved. PII: S 1 3 8 9 - 1 2 8 6 ( 0 0 ) 0 0 0 9 8 - 0
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question will be to ask whether the network is monopath or not. So we shall present a monopath switch that is a Delta network and a multipath switch that is a Clos network. The results might be dierent for another architecture, but the main modelling problems would probably be the same. 2. Description of the questions 2.1. Question A: level of study The ®rst question to be asked concerns the level of study. Question A: Is the study at the cell level, at the burst level or at the call level? It is well known that in ATM networks, there are dierent levels corresponding to dierent time scales. A call can be considered as a set of bursts. A burst is a set of cells (see Fig. 1). When studying a switch at the cell level, an event occurs during one slot. During a call, there will be a huge number of cells, so, when studying a switch at the cell level, the times that will be considered will be very large, when compared with those of a cell level study. It is not possible to consider at the same time two dierent levels of study, such as call level and cell level [25], because an event at the call level implies too many events at the cell level. The dierent levels will lead to dierent conclusions: While a cell level study will help dimen-
Fig. 1. The three dierent levels.
sioning the switch, a burst level study will lead to source policing or congestion avoidance and a call level study will lead to call acceptance control (CAC) and network planning. 2.2. Questions B and C: memory placement The second and third questions to be asked concern the switch architecture [12,32]. Where are the buers placed? There are several types of switch architectures: external buers [19,29,33] or internal buers [15,20]. In case of internal buers (which seems to be the most common choice) there are dierent technologies. If in one slot one switching element can switch only one cell, input buers are necessary [20,21,35], if in one slot several cells arriving on several inputs may be simultaneously switched, then output buers are necessary [21]. Another possibility, which leads to better performance but higher cost, is a common shared memory in the switch [16,17,27]. Question B: Are buers internal or external? Question C: In case of internal buers, in a switching element are the buers output buers or input buers, or is there a common shared memory? 2.3. Question D: monopath versus multipath switch The next very important question, concerns the number of paths that exist between each input and each output. Question D: Is the switch monopath or multipath? The congestion problems will be very dierent if the switch is monopath, or if it is multipath. Delta symmetric networks are well-known examples of monopath networks. Each switching element has n input ports and n output ports. Fig. 2 represents a two-stage Delta network. Let N be the global number of input/output ports and e the number of stages. The following relation holds: N ne . Let us note D N ; n for such a switch. Figure 3 represents an example of a multipath network: a 3 stage Clos network [14]. If it is multipath, each time there is a high load on one path, the load may be split over several paths. A Clos network can be described by the total number of
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2.4. Questions E, F and G: input stream laws
Fig. 2. Example of a two-stage Delta network.
Fig. 3. Example of a three-stage Clos network.
input/output ports N, the number of input ports of the ®rst stage switching elements a and the number b of paths for one origin/destination pair. Let us note C N ; a; b for such a con®guration. In the case of a monopath network, two different paths may have a common link and if two bursts arrive at the same time on the two dierent paths, there will be a serious problem on the common link. On the other hand, a multipath switch may need resequencing. Since several cells of the same call may use dierent paths, they may arrive in the output link out of order. They will have to be reordered.
The input stream law has to be de®ned. Question E: What is the input stream law? This is one of the most dicult problems when designing ATM networks: the future ATM trac is unknown. There are some hints about source models for ATM trac, but trac coming into one switch will not mostly come from sources, it will mostly come from the output of other switches. There are long term correlations, but for studies at the cell level, the time period is short enough not to take care of long term correlations. It is often assumed that source trac is bursty. Let us consider a Markov model with two states: silence and burst. Silences are geometrically distributed with parameter q (mean Ls ), bursts are geometrically distributed with parameter p (mean Lb ). A worst case trac is the case when during one burst there is one cell in each slot. Let us call this trac interrupted deterministic process trac (IDP). The output stream from a switch with IDP input stream is not simple [4]. It can be sometimes approximated by an interrupted Bernoulli process (IBP) trac [5]. This trac can be viewed as a IDP for which in a burst there are cells which constitute a Bernoulli process with parameter a. In case of a study at the cell level, which does not need to take into account long term correlations [26], a reasonable hypothesis for input stream is IDP or IBP. Question F: Are input streams independent? Question G: Are input stream loads uniform? Let us assume for example that the input stream is IBP trac on each link. It is important to know whether those input streams are independent, and whether their parameters are the same. 2.5. Questions H, I and J: destination distributions The next three questions concern the distribution of destinations. From them and from the answer to question F, the output loads will be deduced. Question H: Are destinations uniformly distributed? Even if the destination is uniform when the average is made over a long enough period of time,
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it is not necessarily uniform when averaged over a relatively short time. When studying congestion problems so as to dimension a switch, it may be important to consider the case when, during some time period, the load can be asymmetric. Question I: Do the cells of a same burst have the same destination or not? The answer to this question depends on whether the bursts on the input links come from the same source or not. If an input burst is a superposition of many dierent calls, those cells may go to different output links. In the following let us name those two cases, correlated destinations and uncorrelated destinations. Question J: In case of correlated destinations, are there eventual con¯icts between bursts? If the cells of a same burst go to the same output, and if it happens that two bursts go to the same output, there will be a serious problem. This should be very rare, because of the reservation. Reallistically the answer to this question will be no, except in the case when bursts consist of a superposition of several bursts corresponding to dierent calls. Let us present four cases of non-uniform load, non-uniform-destinations and correlated-destinations trac. During a time interval that is large when compared to a slot the trac is asymmetric. We considered four types of asymmetric trac for this paper: single source to single destination (SSSD), SSSD embedded in uniform trac, multiple source to single destination (MSSD) and multiple source to multiple destination (MSMD). SSSD means that cells belonging to a given burst are assumed to be directed to the same output port and that only one burst can be directed to a given output port. Fig. 4 shows heavy SSSD trac embedded in uniform trac ¯ows. MSSD will be the case when several input links send trac to the same output link, which will be heavily loaded. In case of bursty trac, the answer to question J is yes. MSMD will be the case when there are several high load trac outputs corresponding to several high load trac inputs. This comes from the fact that high load input stream may correspond to a superposition of several bursts.
Fig. 4. SSSD trac + uniform trac.
2.6. Question K: correlated versus uncorrelated routing The last important question concerns the routing inside the switch. It is valid for multipath switches. Question K: In case of multipath switches, how are cells routed? How are paths chosen? Will the cells of a burst be distributed among the dierent possible paths or not? It might seem that if the cells of the same burst follow the same path, a multipath switch is not very useful. There are two reasons why this is not true: · If the cells of the same burst follow the same path, there is no need to resequence and the resequencing cost of the multipath switch is avoided. · The problem with monopath networks, even if reservations are properly done and origin/destination pairs are dierent, is due to the fact that two dierent paths may have a common link [8], so two bursts may use the same inside link. This problem may be avoided if the switch is multipath and if the cells of the same burst are uniformly distributed among the dierent possible paths. In fact, it would appear that multipath switches are useful in case of asymmetric trac. The case of correlated routing (burst routing) and the case of uncorrelated routing (cell routing) are both important. They lead to dierent models, dierent performance results and dierent complexities of implementation.
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3. The subtree of the realistic cases for cell level study, output internal dedicated buers and given input streams laws The answers to questions A to K generate a tree of eventual switch and trac types (Fig. 5). Let us consider a subtree of realistic cases. In Section 5, Table 1 will give some numerical results for a set of examples named {1}±{11}. Let us assume that the answer to question A is: cell level study and that it is intended to dimension the switch. Let us assume that buers are internal and output dedicated buers, which is a compromise between performance needs and hardware complexity. Let us assume that input streams are independent and input stream laws are given. For cell level study, output internal dedicated buers, and given trac laws, Fig. 5 presents the tree of the main cases that lead to dierent modelling methods and problems and dierent types of solutions. It takes into account questions D, I and K (if the network is multipath). When averaging over a very large period, the trac load is probably uniform. But when averaging over a shorter time, this is probably not true. The asymmetry does not introduce a major diculty in modelling problems. It increases the computation complexity. Several types of queues have to be studied in each stage. The solutions are
89
not very dierent, but mostly dierent values of the parameters have to be considered. So Fig. 5 does not present in each case, the answer to question G. It will present some cases of asymmetric trac. This leads to 14 cases. 4. Description of the modelling methods in some of the realistic cases The usual method is the following: ®nd what is Markov and solve the Markov chain. What is Markov may be rather complex, and the solution may be dicult to get. Usually the solution is ®rst derived for a ®rst stage element, the law of the output stream is derived from the input stream law, then the law of the input stream into the second stage has to be computed from the output stream of the ®rst stage, by superposition. 4.1. Uniform trac case (uniform input load and non-correlated destinations) This case was the most studied. Input trac is assumed to be independent, input load is uniform and cells of a given burst are assumed to be uniformly directed over all the output ports of the switch. This trac case may be both studied in the monopath [1,27,28,31] or in the multipath case [5].
Fig. 5. Tree of the main questions, for a cell level study, internal, output, dedicated buers and a given input stream laws.
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In the multipath case, uniform assumption automatically leads to cell routing (no call identi®cation). In this trac case, the resequencing cost is negligible for multipath switches since the time interval between two consecutive cells directed to the same output port is high. The same models are consequently used in both cases. Those studies are mainly based on [21]. In this paper, a comparison of input and output buering strategies is proposed. In the output buer case, an exact model of a switching element is proposed; input streams are assumed to be of Bernoulli type and queues to be in®nite. It leads to the study of a n ÿ Geo/D/1 queue with arrival before departure. Extensions of this work were then presented in the ®nite capacity queue with a dispatching discipline wherein queued cells are sent before arriving cells are added to the queue in order to take into account the switching time itself. Approximate models were then proposed for the whole switch by approximating the output stream of such queues by simple Bernoulli processes [6,23]. The bursty trac input case is a direct extension of the previous model. If the input stream is of IDP or IBP type, an exact model of a switching element can be derived from the study of a n ÿ IBP/D/1/M queue [5]. More generally, if the input process is a discrete Markov arrival process (DMAP), a model of a switching element can be derived from a DBMAP/D/1/M queue [10]. It has been shown that the output process of such queues is of DMAP type but the model of the whole switch cannot be solved. The main problem comes from the characterization of the interstage trac. Approximations of those processes were presented in the literature. Bernoulli, IDP or IBP approximations were proposed, the parameters of those processes are ®tted from the study of the actual output process (interdeparture time, busy and idle period duration). Those approximations lead to good results. However, it was shown that even if the input process into a switching element is Bernoulli, the busy period duration is not geometrically distributed [11]. Consequently new approximations were proposed: a three-state Markov chain with two states for the busy period and one state for the idle period [16,31]. It leads to the same results as the previous models. This
comes from the fact that this output process is not the input process of a given queue of the following stage. This process will be split and even if the output process is bursty, the input process for the following stage will be less bursty. This trac case seems to be quite optimistic since the burstiness of the input stream will mostly be absorbed by the random choice of the output port. Consequently, the performance results do not really depend on the burst length. At the cell level scale, it should be better to consider that most of the input stream oered to a given input port will be directed to one (or a few) output port. We shall now present models for some examples of such asymmetric trac cases. 4.2. Non-uniform trac Let us consider some typical cases when trac is asymmetric. 4.2.1. SSSD trac This trac type was mostly studied for unbuffered switches [22]. A model of a ®rst stage switching element can be derived [8] for monopath networks. In the IBP input stream case, a Markov chain is the vector of the following numbers: · the number of cells in the queue, · the number of `ON' sources, · the number of bursts directed to a given output port of a ®rst stage switching element, · the number of active sources in the other switching elements, · the numbers of bursts in such switching elements directed to the output ports of the switch which can be accessed by the tagged output port. In the multipath case, two solutions may be considered (question K). In the Clos network case, if cells belonging to a given burst use the same path and if the number of paths b is greater than or equal to 2a ÿ 1 (where a is the number of input ports of a ®rst stage switching element), the results are straightforward (cell delay will be 3 units of time (i.e., 3 slot period) and the cell loss probability 0). The proof of this result is the same as the circuit switching's one. If the routing is uncorre-
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lated, a model can be derived [9]. The ®rst two stage models look like the SSSD models embedded in a uniform trac (see Section 4.2.2). The model proposed for the third stage represents a constant service time queue with ®nite capacity, whose source is the output stream from the model of the two ®rst stages. This source model is an IBP=Geo D=b=b queue in the IBP input stream case, b is the number of paths, the parameter of the geometric law is ®tted to the response time of the ®rst two stages obtained by the previous models. So, SSSD trac leads to models that can be solved. 4.2.2. SSSD trac embedded in a uniform trac This trac case was ®rst considered for unbuered switches or for input buers switches [13,22,28]. Multipath switches are studied in [7]. In this paper, only the uncorrelated routing case has been investigated. Approximate models can be derived using the same kind of models as in the uniform trac case. In fact, the parameters have to be computed for the dierent trac types, it leads to the study of IBP1 n ÿ IBP2 =D=1=M queues. The performance criteria are derived for the dierent classes of customers. This trac case has been investigated neither in the monopath case nor in the multipath case with correlated routing since it is not easy to characterize the high trac inside the switch. The problem comes from the superposition of other trac streams. 4.2.3. MSSD trac For monopath switches, a model has been presented in [8]. A Markov chain is the vector of the following numbers: · the number of cells in the queue, · the number of `ON' sources, · the number of bursts directed to a given output port of a ®rst stage switching element. 4.2.4. MSMD trac In fact, it is more realistic to consider MSMD trac for which the input stream corresponds to the superposition of several bursts [1,13,34]. A ®rst study has been presented in [3]. In this study, some input links are oered a high load that will be di-
91
rected to few output ports. This MSMD trac is embedded in a uniform trac. Only the uncorrelated routing multipath case has been investigated. An analytical model has been proposed, it leads to the study of IBP1 n ÿ IBP2 =D=1=M queues. The performance criteria are derived for high load trac and for the low load trac. This trac case should be studied in the monopath case and other MSMD trac cases have to be determined and studied in order to properly dimension ATM switches. 5. Results A few performance results are presented in Table 1. The delay unit is a slot period. Results were derived from analytical solutions when it was possible ({1},{5},{6},{9}), from event driven simulations when it was not. Simulation lengths were chosen so that relative con®dence intervals were less or equal to 10%. Lb and Ls are the mean burst length and silence length. a is the probability in one slot to get a cell during a burst. M i means the memory size at stage i. Delay shows the mean delay time and Loss the cell loss probability. The switch hardware is easier to design and less expensive if switching elements are identical. In the monopath case, it was shown that in the uniform trac case, the best performance results were obtained when the buer size of the dierent stages are equal [18]. This is not true in non-uniform trac cases. However, in those cases, performance results are so bad that it is not possible to dimension the buers in order to lead to convenient performance. Consequently, for monopath cases, only the case when all the buer sizes are identical has been studied. Results are presented for Delta networks with a global number of input ports N equal to 64 and switching elements with 4 input ports and 4 output ports D 64; 4. The number of stages is consequently equal to 3. In the multipath case, performance results heavily depend on the placement of the memory in the dierent cases. Considering a global amount of memory, we tried to obtain the best placement of this memory among the 3 stages of a Clos network. Consequently in Table 1 results are presented for the best value for the memory
Structure
D 64; 4
D 64; 4
D 64; 4 D 64; 4 C 128; 4; 8
C 128; 4; 8
C 128; 4; 8
C 128; 4; 8
C 128; 4; 8
C 256; 4; 8 C 128; 4; 8
No.
{1}
{2}
{3} {4} {5}
{6}
{7}
{8}
{9}
{10} {11}
Table 1 Performance Results 5
1.25
66.7 800 25 1.05 1.33
20 4
±
25
12.5
25 25 1.25
12.5
Ls
100 100 100
±
100
100
100 100 5
100
Lb
±
a
1. 1.
0.9 0.9 0.9
0.9
0.9
0.9 0.9 1
0.9
1
Uniform (Bern) Uniform (IBP) SSSD MSSD Uniform (Bern) Uniform (IBP) SSSD Uncor. rout. SSSD Corr. rout. SSSD + Uniform SSSD Uniform MSSD MSMD (Bern) High trac Low trac
Trac type
±
3 6
5
8
10
400 400 10
30
30
M(1)
±
2 7
5
7
10
400 400 10
30
30
M(2)
56 46
28
±
6
32
400 400 32
30
30
M(3)
11.65 4.89
5.73 3.12 12.67
3
4.14
5.45
208.50 288.00 5.33
8.04
7.63
Delay
2:6 10ÿ4 1:4 10ÿ5
4:9 10ÿ6 5:0 10ÿ7 2:8 10ÿ2
0
7:7 10ÿ7
1:8 10ÿ7
2:8 10ÿ2 5:6 10ÿ2 9:4 10ÿ8
6:6 10ÿ7
5:6 10ÿ8
Loss
92 M. Becker, A.-L. Beylot / Computer Networks 34 (2000) 85±95
M. Becker, A.-L. Beylot / Computer Networks 34 (2000) 85±95
size on the three stages (the best value is the one that leads to the lowest loss probability, the memory size is a number of cells). In the multipath case, several parameters were chosen. In most of the results presented in this paper, the switch has 128 input ports and 128 output ports. In [5], it was shown that the best performance results are obtained when the number of input ports of the switching elements of the ®rst stage have 4 input ports and 8 output ports. The con®guration which is studied in the present paper is consequently a C 128; 4; 8 Clos switch. 5.1. Monopath switch analysis In the uniform trac case [8], it is shown that even with small buer sizes the cell loss probability is quite low. In the SSSD trac case [8], performance results are quite bad even with large buer size. This is due to the fact that as soon as two bursts are directed to the same output port of a given switching element, the queue length increases and cells will be lost. In the MSSD trac case [8], performance results are bad even with large buers for the same reasons as in the previous trac case. 5.2. Multipath switch analysis In the uniform trac case [5,6], the resequencing cost is negligible since the time interval between two consecutive cells coming from the same input port and directed to the same output port of the switch is large. In this trac case, performance results are quite good even with small buers. In the SSSD trac case, in case of non-correlated routing [6], the resequencing cost is not too high [24]. Expected resequencing delay is 1.2 slots and the resequencing loss rate is 10ÿ7 . This trac case is quite optimistic but leads to good performance results even with small buers. If the switch is large enough, and correlated routing is implemented, the performance is still better of course. In the SSSD trac (high trac) embedded in a uniform trac (low trac) case, the performance criteria are estimated for the two kinds of trac. The cell loss probability of the high trac depends
93
on the input load and on the mean burst length. The cell loss for high trac is larger than for the low trac. The resequencing cost is negligible for the low trac and for the high trac if the burst length and the cell loss probability are not too high. Estimation of the number of desequenced cells is 2% of the number of cells, in this trac case [7]. In the MSSD trac case, simulations results were presented in [18] for multipath switches with uncorrelated routing. Performance is better than in the monopath case. However the cell loss probability is still very high even with large buers. Most of the memory size should be placed in the last stage since bursts are split in the ®rst stage switching elements. Consequently, the performance criteria are quite good in the ®rst two stages. But as soon as two bursts are directed to the same output port of a third stage switching element, the queue length increases and cells will be lost. Let us hope that VC allocation will avoid this problem. In the correlated routing case, the performance results should mainly depend on the routing algorithm. However, the cell loss probability will be high even with large buers. In the MSMD trac case presented in this paper [3], only Bernoulli trac has been assumed. It is shown that in this trac case the performance results highly depend on the input load. The cell loss for the heavy trac is larger than for the low trac. The resequencing cost is negligible for low trac and should be estimated in a bursty trac case for high trac (in the Bernoulli case presented in this paper and for large switch this cost is negligible). 6. Conclusion A set of questions has been presented which may help to position the performance study of a switch when compared with others. Some questions appeared to be more important than others. In order to dimension a switch, performance has to be studied at the cell level. For the time scale that is useful for this study, trac asymmetry may be important. Then the most important question is to ask whether the network is multipath or not.
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When trac is uniform, monopath or multipath switches lead to good performance. When trac is asymmetric a monopath switch leads to unacceptable performance. Of course a multipath switch is more expensive because of the resequencing cost and because of the hardware cost, but it is the only reasonable choice. This was proved, by studying the performance of some Clos networks, and some Delta networks. In case the switch architecture is dierent, but is either multipath or monopath, the main performance problems would be the same. For multipath switches, the results that were presented correspond mostly to non-correlated routing. A quite good solution, in case of burst or call path reservation is implemented inside the switch (i.e., ABT), would be of course correlated routing. Performance models in those cases would be tractable, but have not been solved yet. A methodology has been presented. Further experiments would be valuable. It is necessary to design such methodology, because when designing a new switch, the comparison of its performance with other switch performance depends upon so many input parameters, that it is rather unsafe to reach a conclusion. A set of questions was presented in order to try to be fair when comparing performance. In order to illustrate the methodology a few results were presented, but this was not the objective of the paper. There is still a lot of work to do. There are still a lot of switches that might be designed. For example, switches with more than three stages might be compared with the switches that were studied. The routing inside the switch is very important and other routing ways might be designed, so that answers to question J might be improved. References [1] S. Bassi, M. Decina, A. Pattavina, Performance analysis of the ATM shueout switching architecture under nonuniform trac patterns, in: Proceedings IEEE Infocom'92, Florence, Italy, 1992. [2] M. Becker, A.L. Beylot, A. Ziram, Switching networks for ATM, Invited Tutorial, in: Proceedings Fourth Open Workshop on High Speed Networks ENST/Stuttgart University, Brest, France, 1994, pp. 1±22.
[3] A.L. Beylot, I. Kohlenberg, M. Becker, Performance analysis of an ATM switch based on a three-stage Clos interconnection network under non-uniform trac patterns, in: S. Thome, A. Casaca (Eds.), Proceedings IFIP Broadband Communications BC-94, Paris, France, NorthHolland, Amsterdam, 1994, pp. 205±224. [4] A.L. Beylot, I. Kohlenberg, M. Becker, A performance analysis of an ATM Clos switch under bursty trac, in: D. Kouvatsos (Ed.), Proceedings IFIP Workshop on Performance Modelling and Evaluation of ATM Networks, Bradford, UK, 1994, pp. 245±260. [5] A.L. Beylot, M. Becker, Performance analysis of an ATM Clos switch under bursty trac (symmetric IBP arrivals), in: Proceedings IEEE Conference BSS'95, Poznan, Poland, 1995, pp. 108±117. [6] A.L. Beylot, M. Becker, Dimensioning an ATM switch based on a three-stage Clos interconnection network, Annals of Telecommunications 50 (7±8) (1995) 652±666. [7] A.L. Beylot, I. Kohlenberg, H. Yaiche, M. Becker, Performance analysis of an ATM Clos switch under asymmetric bursty trac, in: Proceedings of IFIP Conference WATM'95, Paris, France, December 1995, pp. 255±262. [8] A.L. Beylot, I. Harfouche, M. Becker, Performance analysis of monopath ATM switches under correlated and uncorrelated trac patterns, in: Proceedings 5th Open Workshop on High Speed Networks ENST/Stuttgart University, Paris, France, 1994, pp. 7.1±7.10. [9] A.L. Beylot, I. Harfouche, M. Becker, Performance analysis of multipath ATM switches under bursty single source to single destination trac, RR Prism, no 97003, January 1997. [10] C. Blondia, O. Casals, Statistical multiplexing of VBR sources: a matrix-analytic approach, Performance Evaluation 16 (13) (1992) 5±20. [11] F. Bonomi, S. Montagna, R. Paglino, Busy period for an ATM switching element output line, in: Proceedings IEEE Infocom'92, Paper 4C.2, Florence, Italy, 1992. [12] C. Dhas, V.K. Konangi, M. Sreetharan, Broadband Switching, Architectures, Protocols, Design, and Analysis, IEEE Computer Society Press Tutorial, 1951±1991, 513 pp. [13] D. Chen, J. Mark, A buer management scheme for the SCOQ switch under nonuniform trac loading, in: Proceedings IEEE Infocom'92, Florence, Italy, 1992. [14] C. Clos, A study of non-blocking switching networks, Bell System Tech. 32 (1953) 406±424. [15] M. D'Ambrosio, R. Melen, Performances analysis of ATM switching architecture: a review, in: COST 224, Final seminar, Paris, France, 1991. [16] M. De Marco, A. Pattavina, Performance analysis of ATM multistage networks with shared queueing under correlated trac, in: Proceedings ITC'14, Antibes Juan les Pins, France, 1994, pp. 601±610. [17] A. Eckberg, T. Hou, Eects of output buer sharing on buer requirements in an ATDM packet switch, in: Proceedings IEEE Infocom'88, paper 5A.4. [18] I. Harfouche, Comparaison de plusieurs types d'architectures de commutateurs ATM, DEA Report Conception
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des Systemes Informatiques Avances, CNAM August 1995, pp. 1±43. A. Huang, S. Knauer, Starlite: a wideband digital switch, in: Proceedings Globecom'84, pp. 5.3.1±5.3.5. H. Jenq, Performance analysis of a packet switch based on single-buered Banyan network, IEEE J. Selected Areas Commun. 1(6) (1983). M. Karol, M. Hluchyj, S. Morgan, Input vs. output queueing on a space-division packet switch, IEEE Trans. Commun. 35(12) (1987). H.S. Kim, A.L. Garcia, Performance of buered banyan networks under non-uniform trac patterns, in: Proceedings IEEE Infocom'88, pp. 344±353. H. Kim, M.G. Widjaja, A. Leon-Garcia, Performance analysis of output buered banyan networks with arbitrary buer sizes, in: Proceedings of IEEE Infocom'91, Bal Harbour, FL, 1991. J. Kohlenberg, Caracterisation du tra®c ATM. Performances des commutateurs ATM dans des conditions nonuniformes de fonctionnement, PhD report, Paris VI University, 1996. P. K uhn, Performance modelling and trac engineering for broadband communications networks, in: S. Thome, A. Casaca (Eds.), IFIP Broadband Communications, Paris, France, 1994, pp. 245±274 (Invited paper). W. Leland, M. Taqqu, W. Willinger, D. Wilson, On the self-similar nature of Ethernet trac, in: Proceedings ACM Sigcomm'93, San Francisco, CA, 1993. A. Monterosso, A. Pattavina, Performance analysis of multistage inter-connection networks with shared-buered switching elements for ATM switching, in: Proceedings IEEE Infocom'92, Florence, Italy, 1992. T. Morris, H. Perros, Performance modelling of a multibuered banyan switch under bursty trac, in: Proceedings IEEE Infocom'92, Florence, Italy, 1992 (Paper 3D.2). J. Patel, Performance of processor-memory interconnections for multi-processors, IEEE Trans. Comput. 30 (10) (1981) 542±545. S. Rao (Ed.), State of the Art Issues in ATM Trac, Telecommun. Syst. 5 (1996). T. Theimer, A new model for the analysis of multistage ATM fabrics, in: Proceedings of ITC'14, Antibes Juan-lesPins, France, 1994.
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[32] F. Tobagi, Fast packet switch architectures for broadband integrated service digital networks, in: Proceedings of the IEEE 78(1) (1990). [33] F. Tobagi, T. Kwok, The tandem banyan switching fabric: a simple high-performance fast packet switch, in: Proceedings of IEEE Infocom'91, Bal Harbor, FL, 1991 (Paper 11A.2). [34] H. Yamashita, H. Perros, S. Hong, Performance analysis of a shared buer ATM switch under bursty arrivals, in: Proceedings of ITC'13, Copenhagen, Denmark, 1991. [35] H. Yoon, K. Lee, M. Liu, Performance analysis of multibuered packet-switching networks on multiprocessor systems, IEEE Trans. Comput. 39 (3) (1990) 319±327. Monique Becker graduated from Ecole Normale Superieure de Jeunes Filles in 1968, passed the mathematics ``agregation'' and received the State Doctorate degree from the University of Paris VI in 1976. She joined the National Center of Scienti®c Research were she had the responsibility for a group of researchers working on performance evaluation. In 1987, she joined France Telecom University where she got the position of Professor and Chairman of the Computer Science Department. She is managing a group of researchers (including professors and Ph.D. students) working on performance evaluation of computer and telecommunication networks. Their main interest concerns ATM, IP and satellite networks. AndreÂ-Luc Beylot received the engineer degree from the Institut d'Informatique d'Entreprise in 1989 and the Ph.D. degree in computer science from the University of Paris VI in 1993. From 1993 to 1995 he works at the Institut National des Telecommunications (France Telecom University), and from 1995 to 1996 at CNET (France Telecom Research Laboratory) in Rennes. Since 1996, he is an associate professor at PRiSM Laboratory of the University of Versailles. His interests are in the performance of communication networks, especially with regard to ATM and mobile networks.