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Design and procurement of eutectic SnPb solder-bumped flip chip test die and organic substrates
550
World abstracts on microelectronics and reliability
facilitates faster product qualification to ensure time-to-market advantage. Together with these more cost-effective qualification techniques, the proper reliability-monitoring features must be installed. Only then can the true vision of ALR be accomplished, namely ensuring recognition, by both customers and competitors, as a Company that continuously manufactures defect-free parts. The effect of wirebond geometry and die setting on wire sweep. A. A. O. TAY, K. S. YEO and J. H. WU. IEEE Transactions on Components, Packagin O and Manufacturing Technology, Part B, 18(1), 201 (February 1995). An effective and convenient method is presented for describing wirebond geometry. The method employs a minimum number of geometric parameters which are directly related to the IC package design. Computational simulation of wirebond behavior with in-plane flow load is carried out. A 2D creep flow model is used to predict the velocity distribution and the flow load acting on the wirebond. A finite element method, which allows for plastic deformation and large deflection, is used to predict the deformation of and stress distribution in the wirebond, Comparative analyses of wirebond behavior with different die settings and loop profiles are carried out. The buckling of wirebonds with in-plane flow load is also studied. Very interesting results have been obtained. The numerical results will be useful for the optimal design of IC packages. An efficient multi-layer diagonal router for multiterminal printed circuit boards. KETAN MODY and ANURA JAYASUMANA. Computers Electronic Engineering, 21(3), 147 (1995). This paper presents a grid-based multi-layer, multi-terminal autorouter with the unique feature of diagonal routing. The router is suitable for routing memory boards and highly congested printed circuit boards. Diagonal routing is extremely useful in minimizing vias and in obtaining a high rate of completion with total route length reduced by up to 20~o comparatively. The router employs an improved maze algorithm to incorporate multi-layer diagonal routing. The cost function used in the algorithm is complicated, but can be easily modified to meet specific needs. The algorithm models multi-terminal routing as a minimum spanning tree problem to use the least amount of wiring which is most desirable in the electronic industry. Intelligent net ordering and dynamic data structures reduce memory requirement and total route time by up to 30~o compared to recently developed routers. The algorithm described in this paper was extensively tested against standard benchmarks and very inspiring results were achieved. Thermoeompression bonding effects on bump-pad adhesion. YOUNG-GON G. KIM et al. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(1), 192 (February 1995). In the wafer bumping process, metal bumps are
deposited on aluminum pads and are later used to bond the silicon die to the I/O connections. The bump strength is important for the mechanical integrity and overall reliability of the interconnect. In this paper the effects of the following thermocompression bonding parameters on the bump-pad adhesion of TAB (tape automated bonding) bonds are experimentally determined and analytically explained: thermode temperature, base temperature, bonding pressure, and bonding duration. Experiments were performed on a 328-lead TAB device (gold bump on four-mil pitch) and were based upon a four-parameter, three-level, Taguchi orthogonal array. The experimental results are compared with results obtained from finite element analyses. A consistent increase in the bump strength was observed after thermocompression bonding. Applied thermode pressure and bonding duration were found to be the most significant parameters that affect bump-pad adhesion. Design and procurement of eutectic Sn/Pb solderbumped flip chip test die and organic substrates. J. LAU, M. HEYDINGER, J. GLAZER and D. UNO. Circuit World, 21(3), 20 (1995). A case study was conducted to investigate the issues associated with the design and procurement of flip chip test die and corresponding organic substrates. Test wafers were fabricated by an IC supplier and bumped with electroplated eutectic Sn/Pb by a third party. Issues associated with transferring integrated circuit data to printed circuit design software were identified. The bare and bumped wafers were characterized to identify possible criteria for lot qualification. A reliability study of fuzz button interconnects. D. B. HARRIS and M. G. PECHT. Circuit World, 21(2), 1l (1995). This paper presents the methods and results of load, deflection and electrical contact resistance experiments for reliable electronic module design using fuzz button technology. Both beryllium copper (BeCu) and molybdenum (Mo) fuzz button contacts were examined, as a function of wire diameter, button diameter and button density. Electrical characterization of the innerconnected mesh power system (IMPS) MCM topology. L. W. SCHAPER, S. ANG, YEE L. LOW and DANNY R. L. OLDHAM. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(1), 99 (February 1995). A significant decrease in MCM substrate production cost can be achieved by reducing the number of substrates layers from the conventional four or five (power, ground, X signal, Y signal, pad) to two or three. Besides reducing direct processing steps, yield will also increase as defect producing operations are eliminated. This paper describes the Interconnected Mesh Power System (IMPS), a new interconnection topology which leverages the production technologies of fine line lithography and batch via generation to allow planar power and ground distribution, and dense signal
World abstracts on microelectronics and reliability
facilitates faster product qualification to ensure time-to-market advantage. Together with these more cost-effective qualification techniques, the proper reliability-monitoring features must be installed. Only then can the true vision of ALR be accomplished, namely ensuring recognition, by both customers and competitors, as a Company that continuously manufactures defect-free parts. The effect of wirebond geometry and die setting on wire sweep. A. A. O. TAY, K. S. YEO and J. H. WU. IEEE Transactions on Components, Packagin O and Manufacturing Technology, Part B, 18(1), 201 (February 1995). An effective and convenient method is presented for describing wirebond geometry. The method employs a minimum number of geometric parameters which are directly related to the IC package design. Computational simulation of wirebond behavior with in-plane flow load is carried out. A 2D creep flow model is used to predict the velocity distribution and the flow load acting on the wirebond. A finite element method, which allows for plastic deformation and large deflection, is used to predict the deformation of and stress distribution in the wirebond, Comparative analyses of wirebond behavior with different die settings and loop profiles are carried out. The buckling of wirebonds with in-plane flow load is also studied. Very interesting results have been obtained. The numerical results will be useful for the optimal design of IC packages. An efficient multi-layer diagonal router for multiterminal printed circuit boards. KETAN MODY and ANURA JAYASUMANA. Computers Electronic Engineering, 21(3), 147 (1995). This paper presents a grid-based multi-layer, multi-terminal autorouter with the unique feature of diagonal routing. The router is suitable for routing memory boards and highly congested printed circuit boards. Diagonal routing is extremely useful in minimizing vias and in obtaining a high rate of completion with total route length reduced by up to 20~o comparatively. The router employs an improved maze algorithm to incorporate multi-layer diagonal routing. The cost function used in the algorithm is complicated, but can be easily modified to meet specific needs. The algorithm models multi-terminal routing as a minimum spanning tree problem to use the least amount of wiring which is most desirable in the electronic industry. Intelligent net ordering and dynamic data structures reduce memory requirement and total route time by up to 30~o compared to recently developed routers. The algorithm described in this paper was extensively tested against standard benchmarks and very inspiring results were achieved. Thermoeompression bonding effects on bump-pad adhesion. YOUNG-GON G. KIM et al. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(1), 192 (February 1995). In the wafer bumping process, metal bumps are
deposited on aluminum pads and are later used to bond the silicon die to the I/O connections. The bump strength is important for the mechanical integrity and overall reliability of the interconnect. In this paper the effects of the following thermocompression bonding parameters on the bump-pad adhesion of TAB (tape automated bonding) bonds are experimentally determined and analytically explained: thermode temperature, base temperature, bonding pressure, and bonding duration. Experiments were performed on a 328-lead TAB device (gold bump on four-mil pitch) and were based upon a four-parameter, three-level, Taguchi orthogonal array. The experimental results are compared with results obtained from finite element analyses. A consistent increase in the bump strength was observed after thermocompression bonding. Applied thermode pressure and bonding duration were found to be the most significant parameters that affect bump-pad adhesion. Design and procurement of eutectic Sn/Pb solderbumped flip chip test die and organic substrates. J. LAU, M. HEYDINGER, J. GLAZER and D. UNO. Circuit World, 21(3), 20 (1995). A case study was conducted to investigate the issues associated with the design and procurement of flip chip test die and corresponding organic substrates. Test wafers were fabricated by an IC supplier and bumped with electroplated eutectic Sn/Pb by a third party. Issues associated with transferring integrated circuit data to printed circuit design software were identified. The bare and bumped wafers were characterized to identify possible criteria for lot qualification. A reliability study of fuzz button interconnects. D. B. HARRIS and M. G. PECHT. Circuit World, 21(2), 1l (1995). This paper presents the methods and results of load, deflection and electrical contact resistance experiments for reliable electronic module design using fuzz button technology. Both beryllium copper (BeCu) and molybdenum (Mo) fuzz button contacts were examined, as a function of wire diameter, button diameter and button density. Electrical characterization of the innerconnected mesh power system (IMPS) MCM topology. L. W. SCHAPER, S. ANG, YEE L. LOW and DANNY R. L. OLDHAM. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(1), 99 (February 1995). A significant decrease in MCM substrate production cost can be achieved by reducing the number of substrates layers from the conventional four or five (power, ground, X signal, Y signal, pad) to two or three. Besides reducing direct processing steps, yield will also increase as defect producing operations are eliminated. This paper describes the Interconnected Mesh Power System (IMPS), a new interconnection topology which leverages the production technologies of fine line lithography and batch via generation to allow planar power and ground distribution, and dense signal