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Design and study of programmable ring oscillator using IDUDGMOSFET
Solid-State Electronics xxx (2015) xxx–xxx
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Design and study of programmable ring oscillator using IDUDGMOSFET Sagar Mukherjee ⇑, Swarnil Roy, Kalyan Koley, Arka Dutta, Chandan Kumar Sarkar Jadavpur University, Kolkata, West Bengal, India
a r t i c l e
i n f o
Article history: Available online xxxx Keywords: Symmetric DGMOS Lateral straggle Ring oscillator Total Harmonic Distortion Programmable circuit
a b s t r a c t In this paper, a novel RF range programmable ring oscillator is designed using independently driven underlap double gate (IDUDG) MOSFET and its performance is studied. The study also presents the variation in analog parameters of the designed oscillator circuit considering different source/drain (S/D) lateral straggle lengths of the IDUDGMOS device. The primary objective behind the programmable oscillator design is the variation of frequency with number of inverter stages and the back gate voltage of IDUDGMOS. The analog parameters analyzed are, the bandwidth, the Total Harmonic Distortion (THD), the linearity and the power consumption of the circuit. The proposed circuit reduces power loss and presents larger bandwidth than other established oscillator circuit designs. The study also shows that IDUDGMOS with larger S/D straggle length improves bandwidth of the oscillator circuit. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction Rapid improvement in wireless handheld technology has resulted in an increased need for low-power circuit. In the communication domain, low power on-chip systems are in high demand for implementation in low-power hand-held devices like tablet PC, smart phones and satellite phones [1]. The present communication bandwidth of 9–90 GHz, which includes radar, satellite phones, wireless-LAN and other radio system, requires a low power oscillator with programmable output frequency for modulation/demodulation. With the advancement of microelectronics technology, the size of transistor is reducing every year following Moore’s Law. As a result, design of analog circuits with devices in the decananometer regime, with limited control over short channel effect (SCE), is a real challenge. An IDUDGMOS device, which has two independently driven gates, is a good alternative in this regard [2,3]. The two independently driven gates of the device offer better control over the channel [4] resulting in smaller SCE and higher on current (Ion) to off current (Ioff) ratio. At the same time, due to the independent gate property of IDUDGMOS the channel resistance can be modulated by the back gate voltage [4,5]. Thus these types of devices are used here in designing the ring oscillator which requires good control over drain current characteristics. In earlier works, non-tunable ring oscillator circuit designs with bandwidth of 9.8–11.5 GHz [6] and 0.1–39.1 GHz [7] are reported. However,
⇑ Corresponding author. E-mail address: [email protected] (S. Mukherjee).
in this work a ring oscillator with higher bandwidth and tunable feature using the IDUDGMOS devices is designed. The operation of the ring oscillator is also dependent on fabrication process dependent device parameters such as S/D lateral straggle. The lateral straggle is the maximum distance where the source/drain out diffusion concentration goes below the channel doping concentration value. The variation of straggle length (LS) causes a change in the effective channel length and the channel resistance of IDUDGMOS which results in variation of the analog/ RF performance of the circuit [8]. Thus, the study of its impact on the circuit performance is necessary. Before going to analysis the ring oscillator, the Ion/Ioff ratio of the IDUDGMOS device is optimized with the S/D underlap length as described in [4]. Later, a programmable ring oscillator is designed using IDUDGMOS and the effect of lateral straggle on circuit performance is observed for three different LS. Following sections present the details of the devices structure, circuit design and its performance analysis.
2. Device structures In Fig. 1 the structure of IDUDGMOS under consideration is shown. The IDUDGMOS device has the characteristics like gate length (LG) of 45 nm, the silicon body thickness (Tsi) of 20 nm, gate height (TG) of 10 nm, front oxide thickness (Toxf) and back oxide thickness (Toxb) of 1.9 nm, S/D underlap length (Lun) of 20 nm and channel doping concentration of 1015 cm3 [9]. The optimized underlap length (Lun) of 20 nm, by maximizing Ion to Ioff ratio, is used for simulation, where Ion is defined as the current at Vgs = Vds = VDD = 1 V and Ioff is defined as the current at Vgs = 0 and
http://dx.doi.org/10.1016/j.sse.2015.11.009 0038-1101/Ó 2015 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009
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Fig. 1. Cross section of an idealized IDUDGMOS device structure with symmetric source/drain underlap.
Vds = VDD = 1 V. Molybdenum is used as gate contact material, SiO2 with dielectric constant of 3.9 is used as the gate oxide material, and silicon nitride with dielectric constant of 7.5 is used as spacer. The device width W = 1 lm is kept constant for all simulation. The doping profile of the channel at the source-to-channel and drain-to-channel junction is considered as Gaussian type due to out-diffusion during ion implantation and is given by N sd ðxÞ ¼ N peak expðx2 =L2S Þ. Where, Nsd represents the source-to-channel/d rain-to-channel doping concentration, x represents the position along the channel, LS is lateral straggle length [10]. The model for the straggle is adopted as described in [10]. For the process variations, we have simulated three different values of LS during the simulation: 3 nm, 5 nm and 7 nm. It may be noted that during the fabrication process, the circuits designed on a die undergo the same process steps thus the effective source/drain LS is same for all the devices in the circuit on the die. The simulated doping profile of the investigated structure is shown in Fig. 2. All the simulations are performed with 2D numerical simulator Sentaurus TCAD [11] of Synopsys. During the simulation, ionized impurity scattering and temperature dependency is included using Arora mobility model [12]. S hockley–Read–Hall (SRH) recombination is used to model active carrier lifetime/carrier density [13] and for carrier transport drift diffusion model is considered [14]. In addition, to accurately predict the characteristics of the devices a robust optimized mesh was generated and it also accelerates the computational efficiency [15]. The carrier mobility was carefully fitted with standard experimental data [16] for the precise estimation of the performance parameters as shown in Fig. 3. The IDUDGMOSFET device is fabricated following steps similar to the FinFET fabrication process flow however, a significant
Fig. 2. Gaussian doping profiles for various LS as a function of position along channel length.
Fig. 3. Calibration of simulated result against experimental result [16].
distinction in the process flow is formation of the dry etched cavity used for back gate formation [17,18]. In next section, the design and analysis of the ring oscillator circuits has been carried out for the three different LS IDUDGMOS. 3. Circuit design In the first part of this section, the design of programmable oscillator using IDUDGMOS has been described, and then the effect of lateral straggle in IDUDGMOS on the circuit performance is observed. Fig. 4 is the basic circuit of a 3 stage and a 5 stage ring oscillator, designed using inverter. In an inverter circuit, a signal faces two types of delay, rise time delay and fall time delay. The fall time delay sPHL or the delay during high to low transition is represented as in Eq. (1).
sPHL ¼
C load ðV OH V 50% Þ ½19 Iav g:HL
ð1Þ
where C load is the load capacitance, Iav g:HL is the average current during a high to low transition, V 50% is the voltage point where the voltage is half of VDD and VOH is the maximum output voltage during the ‘‘HIGH” output of the inverter. The frequency of oscillation, fosc for the oscillator circuit designed using inverter is given as in Eq. (2).
f osc ¼
1 ½20 2 N TD
ð2Þ
where TD is the propagation delay of each stage and N is the number of stages. The TD is dependent on sPHL [19] and N can be altered only during the pre-silicon design time of the circuit. For a CMOS based ring oscillator like Fig. 4 the frequency of oscillation cannot be changed once the circuit is fabricated. In Fig. 4 there are two oscillators where fosc is f osc ð3StageÞ ¼ 1=ð6 T D Þ for the three-stage oscillator and f osc ð5StageÞ ¼ 1=ð10 T D Þ for five-stage oscillator. Thus, for a CMOS ring oscillator the frequency of oscillation can only be changed by changing the number of stages at design time. For a variable-frequency application like VCO (Voltage Controlled Oscillator) this inverter-based ring oscillator would not be a good choice as the frequency cannot be varied by control voltage. For a VCO application, a differential amplifier-based ring oscillator as in Fig. 5 would be a better choice, where the frequency could be changed by a control voltage. However, it comes at a cost of increased number of transistor resulting in increased power consumption and size of the chip. The Iavg of a differential amplifier depends on the ISS, which is the tail current of the differential amplifier [20]. As a result, a control voltage can be
Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009
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3
Fig. 4. A schematic view of 5 stage and 3 stage CMOS ring oscillator.
Fig. 5. Differential amplifier based voltage controlled ring oscillator.
applied to the gate of the tail MOSFET of the differential amplifier to generate voltage controlled frequencies from the ring oscillator circuit. The bandwidth of such a differential amplifier based ring oscillator is limited due to the minor change in frequency with control voltage. To increase the controllability of the output frequency of the ring oscillator, a new design is proposed in this work in which the frequency can be tuned like a VCO and can be stepped up or down by controlling the number of active stages N during the circuit usage. The range (Nmin, Nmax) between the minimum and maximum number of stages shall be determined by application requirement and results in maximum frequency of oscillation, fosc,max and in minimum frequency of oscillation, fosc,min respectively. The proposed circuit is designed using IDUDGMOS which has two independently driven gates. For IDUDGMOS, the channel current is controlled by both Vgsb and Vgsf, which is front gate to source
voltage and back gate to source voltage, respectively [21]. Now, by changing the Vgsb, channel current is modulated and the back gate dependency of corresponding transconductance gm is represented by gm(Vgsb), where Vgsf is fixed. As a result, for a fixed Vgsf, drain current Id of the IDUDGMOS at any instant is controlled by the product of gm(Vgsb) and Vgsf and is represented as
Id ¼ g m V gsb ðtÞ V gsf
ð3Þ
Eq. (3) shows that by changing the Vgsb it is possible to change the current through the IDUDGMOS. This in turn causes a change in the Iavg of the inverter, which will affect the TD of the inverter circuit [19]. In IDUDGMOS based inverter the Iavg can be modulated by changing the back gate voltage of the nIDUDGMOS. In Fig. 6 the back gate of all the nIDUDGMOS of inverters are connected together, forming a control terminal for the ring oscillator, where one applies the tuning voltage VtuneN. Variation of VtuneN will
Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009
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Fig. 6. Circuit diagram of proposed programmable IDUDGMOS based ring oscillator.
modulate the channel current, resulting in an inversely proportional variation of propagation delay of the inverter. Thus, VtuneN and fosc are directly proportional. Thus, keeping N fixed, fosc for the inverter based ring oscillator is tuned by changing the tied back gate voltage of nIDUDGMOS devices in the oscillator. Since the design is CMOS based, it reduces the number of transistor in comparison to differential amplifier based VCO and at the same time provides the advantages of voltage controlled frequency like VCO. Next challenge is to change the N during the operation of the circuit to step up or down the frequency for a larger span. The N can be changed by providing a programmable hardware scheme as shown in Fig. 6, where the input of first inverter, Vout, is connected to output of each odd stage of inverter beyond 3, via a transmission gate based switch. As a result, the effective number of stages of the oscillator depends on the switch that is ‘‘ON”. Fig. 6 shows the feedback path via switches going back to the input of the first inverter. If the target stage of oscillator is N = 3 then, VcontrolP3 and VcontrolN3 will be set to 0 V and 1 V, respectively, to turn ‘‘ON” the switch for the three-stage oscillator. Similarly, to increase N further, the corresponding switch circuits will be enabled to send the proper feedback path back to the input of first inverter. Thus, one has a programmable ring oscillator where the coarse frequency is controlled by changing the number of stages and the frequency is fine-tuned by changing the VtuneN. The programmable oscillator designed is simulated for three different LS of IDUDGMOS to study the analog performance of the programmable ring oscillator for process-related variations. In the next section, performance study of the proposed circuit is done. 4. Analog performance study In Fig. 7 the performance of the three oscillator circuits designed using the IDUDGMOS device shows that the maximum frequency achieved, corresponding to three stage, is about 86.4 GHz for LS = 7 nm followed by 63.9 GHz for LS = 5 nm and 55.2 GHz for LS = 3 nm. The frequency of the oscillator circuit, governed by Eq. (2), suggests that the circuit having the highest TD will
Fig. 7. Variation of output frequency (fosc) as a function of number of stages (N) for designed oscillator for constant Vgsb = 0.7.
have the lowest fosc [20]. It is observed that increase in LS shortens the effective channel length which results in increased channel current, causing a decrease in TD. As a result circuit designed with IDUDGMOS having highest LS = 7 nm will have the minimum TD resulting in highest fosc followed by LS of 5 nm and 3 nm. The number of stages in the circuit is varied by switching on appropriate feedback path as described in the previous section. In Fig. 8 ratio of frequency variation (Df) and minimum frequency is considered as the measure of change in frequency. Fig. 8 shows the variation in ratio of Df and minimum frequency (f) for oscillator having N = 3 with respect to the change in back gate control voltage. It is exhibited that all three circuits show a linear change of frequency with VtuneN and the change is maximum for the circuit designed with the IDUDGMOS of highest LS = 7 nm due to the maximum channel current. Thus using this oscillator circuit nearly two times improvement of bandwidth in comparison to the previous literature [7] is achieved. Thus, by changing the number of stages using switch
Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009
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Fig. 8. Variation of output frequency as a function of tuning voltage (VtuneN) for the designed oscillator for N = 3.
we can change the core frequency and by changing the back gate voltage frequency can be fine-tuned. Hence, the circuit can be used as a programmable oscillator for a wide range which results in few interesting application of the proposed circuit like VCO and frequency modulation. Fig. 9 shows linearity performance study of the proposed circuit from the output power vs. input power characteristics of three oscillator circuits which show that the circuit is having a linear characteristics up to 8 dB beyond which the gain become saturated. Circuit with lower LS shows larger linear range of operation due to large gain property [9] of individual inverter stage of oscillators. Fig. 9 shows the exact agreement with this where LS = 3 nm based device having a linear range of operation up to 7 dB followed by 8 dB for LS = 5 nm and 10 dB for LS = 7 nm. Linearity of the circuit is also measured from the harmonic distortion of the circuit which is measured by Total Harmonic Distortion (THD) [22] as shown in Fig. 10 which shows that the circuit is having a low value of distortion and THD increases with number of stages. Low value of THD represents that the circuit is having a linear and low distortion performance for a wide range of frequency due to wide bandwidth of IDUDGMOS. Maximum THD of 5 dB and minimum THD of 1 dB is resulted by oscillator designed with LS = 7 nm and LS = 3 nm IDUDGMOS based circuit respectively. All the mixed-mode AC device simulations are done using TCADbased [11] small-signal equivalent model of the device that includes the effect of parasitic capacitances like outer fringing
Fig. 10. Variation of THD of oscillator for different number of stages for designed oscillator.
Fig. 11. Power consumption of the oscillator circuit for three different LS.
Table 1 Performance summary of oscillator circuits of three different LS. Parameter
Bandwidth (GHZ) Input range (dB) Maximum THD (dB) Power consumption (mW)
Fig. 9. Output power versus input power of designed oscillator for different LS.
LS of IDUDGMOS used in oscillator design LS = 3 nm
LS = 5 nm
LS = 7 nm
8.72–55.2 7 1 6.61
10.1–63.9 8 3 7.60
13.6–86.4 10 5 8.69
and inner fringing capacitances as described in [23] and thus, the analog performances are faithful for comparative analysis. In Fig. 11, the power performance of three circuits for three different straggle lengths is shown. It is observed that the power consumption increases with increasing LS due to following reason. With the increase in LS the effective channel length decreases causing increased Id and resulting in higher power consumption. The power consumption is minimum for IDUDGMOS with LS = 3 nm and is about 6.61 mW which is 8 time smaller than existing circuit [6] (see Table 1). In this study IDUDGMOS device under analysis is a FDSOI device having equal Toxf and Toxb, known as symmetric FDSOI FET [24]. For a case where Toxb is much more than Toxf, the device operates like
Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009
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an asymmetric IDUDGMOS [24]. The decrease in Id of the asymmetric IDUDGMOS device with decreasing back gate voltage is much more than the symmetric IDUDGMOS, as gm of the asymmetric IDUDGMOS device decreases for thicker Toxb, due to lower inversion charge near back gate now to compensate the reduction in gm, a higher range of voltage is needed to be applied at the back gate, resulting in a requirement of higher VtuneN. 5. Conclusion In this work, design and performance analysis for programmable ring oscillator circuit for different lateral straggle (LS) of IDUDGMOS is presented. A strategy of controlling the frequency with both coarse and fine accuracy is presented. Coarse frequency is controlled by controlling the proper feedback path through control voltages and fine frequency control is done by changing the tuning voltage, which is applied to the back gate voltage of the IDUDGMOS. It is observed that the maximum frequency is achieved by the device with highest LS = 7 nm IDUDGMOS at 1 V DC supply. The bandwidth is highest for the maximum LS device based circuit. Linearity is highest and power consumption is lowest for minimum LS device. Thus the ring oscillator circuit designed with LS = 3 nm IDUDGMOS device is considered as the best choice for low power application. Proposed circuit produces highest output frequency (fosc,max) of 86.4 GHz and lowest output frequency (fosc,min) of 8.72 GHz for Nmin = 3 and Nmax = 19 of proposed oscillator respectively considering variation of LS. The circuit provides a maximum bandwidth of 73 GHz with a cost of 8.69 mW of power consumption with a 1 dB compression point at 10 dB of input power for LS = 7 nm device. This makes the programmable ring oscillator circuit ideal for low-power, handheld communication devices. References [1] Tham JL, Hull C, Ali A, Carr F, Chu R, Walley J, Koullias I. A direct-conversion transceiver chip set for 900 MHz (ISM band) spread-spectrum digital cordless telephone. In: IEEE international symposium on circuits and systems, vol. 4, 12–15 May 1996. p. 85–8. [2] Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong HSP. Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 2001;89(3):259–88. [3] Koley K, Syamal B, Kundu A, Mohankumar N, Sarkar CK. Subthreshold analog/ RF performance of underlap DG FETs with asymmetric source/drain extensions. Microelectron Reliab 2012;52(11):2572–8.
[4] Koley K, Dutta A, Syamal B, Saha SK, Sarkar CK. Subthreshold analog/RF performance enhancement of underlap DG FETs with high-k spacer for low power applications. IEEE Trans Electron Devices 2013;60(1):63–9. [5] Bansal A, Paul BC, Roy K. Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices. In: IEEE international SOI conference, 4–7 October 2004. p. 94–5. [6] van der Tang JD, Kasperkovitz D, van Roermund A. A 9.8–11.5-GHz quadrature ring oscillator for optical receivers. IEEE J Solid-State Circuits 2002;37 (3):438–42. [7] Cai Yong, Cheng Zhiqun, Tang WCW, Lau Kei May, Chen KJ. Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMT inverters and ring oscillators using CF4 plasma treatment. IEEE Trans Electron Devices 2006;53 (9):2223–30. [8] Fossum JG, Zhou Z, Mathew L, Nguyen BY. SOI versus bulk-silicon nanoscale FinFETs. Solid-State Electron 2010;54(2):86–9. [9] Koley K, Dutta A, Saha SK, Sarkar CK. Effect of source/drain lateral straggle on distortion and intrinsic performance of asymmetric underlap DG-MOSFETs. IEEE J Electron Devices Soc 2014;2(6):135–44. [10] Trivedi V, Fossum JG, Chowdhury MM. Nanoscale FinFETs with gate-source/ drain underlap. IEEE Trans Electron Devices 2005;52(1):56–62. [11] Sentaurus TCAD Manuals, Synopsys Inc., Mountain View, CA; 2009 [12] Arora ND, Hauser JR, Roulston DJ. Electron and hole mobilities in silicon as a function of concentration and temperature. IEEE Trans Electron Devices 1982;29(2):292–5. [13] Fossum JG, Lee DS. A physical model for the dependence of carrier lifetime on doping density in nondegenerate silicon. Solid State Electron 1982;25:741–7. [14] Egley JL, Chidambarrao D. Strain effects on device characteristics: implementation in drift-diffusion simulators. Solid-State Electron 1993;36 (12):1653–64. [15] Saha S. MOSFET test structures for two-dimensional device simulation. Solid State Electron 1995;38(1):69–73. [16] Esseni D, Mastrapasqua M, Celler GK, Baumann FH, Fiegna C, Selmi L, et al. Low field mobility of ultra-thin SOI N- and P-MOSFETs: measurements and implications on the performance of ultra-short MOSFETs. Int Electron Devices Meet Tech Digest 2000;2000:671–4. [17] Chung TM, Olbrechts B, Södervall U, Bengtsson S, Flandre D, Raskin J-P. Planar double-gate SOI MOS devices: fabrication by wafer bonding over prepatterned cavities and electrical characterization. Solid-State Electron 2007;51(2):231–8. [18] Wong HSP, Chan KK, Taur Y. Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel. Int Electron Devices Meet Tech Digest 1997;1997:427–30. [19] Kang Sung-Mo, Leblebici Y. CMOS digital integrated circuits. Tata McGraw-Hill Education; 2003. [20] Razavi B. Design of analog CMOS integrated circuits. Tata McGraw-Hill Education; 2002. [21] Shrivastava M, Baghini MS, Sachid AB, Sharma DK, Rao VR. A novel and robust approach for common mode feedback using IDDG FinFET. IEEE Trans Electron Devices 2008;55(11):3274–82. [22] Razavi B. RF microelectronics. Prentice Hall; 2011. [23] Kang IM, Shin H. Non-quasi-static small-signal modeling and analytical parameter extraction of SOI FinFETs. IEEE Trans Nanotechnol 2006;5 (3):205–10. [24] Amara A, Rozeau O. Planar double-gate transistor: from technology to circuit. Springer-Verlag; 2009.
Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Design and study of programmable ring oscillator using IDUDGMOSFET Sagar Mukherjee ⇑, Swarnil Roy, Kalyan Koley, Arka Dutta, Chandan Kumar Sarkar Jadavpur University, Kolkata, West Bengal, India
a r t i c l e
i n f o
Article history: Available online xxxx Keywords: Symmetric DGMOS Lateral straggle Ring oscillator Total Harmonic Distortion Programmable circuit
a b s t r a c t In this paper, a novel RF range programmable ring oscillator is designed using independently driven underlap double gate (IDUDG) MOSFET and its performance is studied. The study also presents the variation in analog parameters of the designed oscillator circuit considering different source/drain (S/D) lateral straggle lengths of the IDUDGMOS device. The primary objective behind the programmable oscillator design is the variation of frequency with number of inverter stages and the back gate voltage of IDUDGMOS. The analog parameters analyzed are, the bandwidth, the Total Harmonic Distortion (THD), the linearity and the power consumption of the circuit. The proposed circuit reduces power loss and presents larger bandwidth than other established oscillator circuit designs. The study also shows that IDUDGMOS with larger S/D straggle length improves bandwidth of the oscillator circuit. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction Rapid improvement in wireless handheld technology has resulted in an increased need for low-power circuit. In the communication domain, low power on-chip systems are in high demand for implementation in low-power hand-held devices like tablet PC, smart phones and satellite phones [1]. The present communication bandwidth of 9–90 GHz, which includes radar, satellite phones, wireless-LAN and other radio system, requires a low power oscillator with programmable output frequency for modulation/demodulation. With the advancement of microelectronics technology, the size of transistor is reducing every year following Moore’s Law. As a result, design of analog circuits with devices in the decananometer regime, with limited control over short channel effect (SCE), is a real challenge. An IDUDGMOS device, which has two independently driven gates, is a good alternative in this regard [2,3]. The two independently driven gates of the device offer better control over the channel [4] resulting in smaller SCE and higher on current (Ion) to off current (Ioff) ratio. At the same time, due to the independent gate property of IDUDGMOS the channel resistance can be modulated by the back gate voltage [4,5]. Thus these types of devices are used here in designing the ring oscillator which requires good control over drain current characteristics. In earlier works, non-tunable ring oscillator circuit designs with bandwidth of 9.8–11.5 GHz [6] and 0.1–39.1 GHz [7] are reported. However,
⇑ Corresponding author. E-mail address: [email protected] (S. Mukherjee).
in this work a ring oscillator with higher bandwidth and tunable feature using the IDUDGMOS devices is designed. The operation of the ring oscillator is also dependent on fabrication process dependent device parameters such as S/D lateral straggle. The lateral straggle is the maximum distance where the source/drain out diffusion concentration goes below the channel doping concentration value. The variation of straggle length (LS) causes a change in the effective channel length and the channel resistance of IDUDGMOS which results in variation of the analog/ RF performance of the circuit [8]. Thus, the study of its impact on the circuit performance is necessary. Before going to analysis the ring oscillator, the Ion/Ioff ratio of the IDUDGMOS device is optimized with the S/D underlap length as described in [4]. Later, a programmable ring oscillator is designed using IDUDGMOS and the effect of lateral straggle on circuit performance is observed for three different LS. Following sections present the details of the devices structure, circuit design and its performance analysis.
2. Device structures In Fig. 1 the structure of IDUDGMOS under consideration is shown. The IDUDGMOS device has the characteristics like gate length (LG) of 45 nm, the silicon body thickness (Tsi) of 20 nm, gate height (TG) of 10 nm, front oxide thickness (Toxf) and back oxide thickness (Toxb) of 1.9 nm, S/D underlap length (Lun) of 20 nm and channel doping concentration of 1015 cm3 [9]. The optimized underlap length (Lun) of 20 nm, by maximizing Ion to Ioff ratio, is used for simulation, where Ion is defined as the current at Vgs = Vds = VDD = 1 V and Ioff is defined as the current at Vgs = 0 and
http://dx.doi.org/10.1016/j.sse.2015.11.009 0038-1101/Ó 2015 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009
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Fig. 1. Cross section of an idealized IDUDGMOS device structure with symmetric source/drain underlap.
Vds = VDD = 1 V. Molybdenum is used as gate contact material, SiO2 with dielectric constant of 3.9 is used as the gate oxide material, and silicon nitride with dielectric constant of 7.5 is used as spacer. The device width W = 1 lm is kept constant for all simulation. The doping profile of the channel at the source-to-channel and drain-to-channel junction is considered as Gaussian type due to out-diffusion during ion implantation and is given by N sd ðxÞ ¼ N peak expðx2 =L2S Þ. Where, Nsd represents the source-to-channel/d rain-to-channel doping concentration, x represents the position along the channel, LS is lateral straggle length [10]. The model for the straggle is adopted as described in [10]. For the process variations, we have simulated three different values of LS during the simulation: 3 nm, 5 nm and 7 nm. It may be noted that during the fabrication process, the circuits designed on a die undergo the same process steps thus the effective source/drain LS is same for all the devices in the circuit on the die. The simulated doping profile of the investigated structure is shown in Fig. 2. All the simulations are performed with 2D numerical simulator Sentaurus TCAD [11] of Synopsys. During the simulation, ionized impurity scattering and temperature dependency is included using Arora mobility model [12]. S hockley–Read–Hall (SRH) recombination is used to model active carrier lifetime/carrier density [13] and for carrier transport drift diffusion model is considered [14]. In addition, to accurately predict the characteristics of the devices a robust optimized mesh was generated and it also accelerates the computational efficiency [15]. The carrier mobility was carefully fitted with standard experimental data [16] for the precise estimation of the performance parameters as shown in Fig. 3. The IDUDGMOSFET device is fabricated following steps similar to the FinFET fabrication process flow however, a significant
Fig. 2. Gaussian doping profiles for various LS as a function of position along channel length.
Fig. 3. Calibration of simulated result against experimental result [16].
distinction in the process flow is formation of the dry etched cavity used for back gate formation [17,18]. In next section, the design and analysis of the ring oscillator circuits has been carried out for the three different LS IDUDGMOS. 3. Circuit design In the first part of this section, the design of programmable oscillator using IDUDGMOS has been described, and then the effect of lateral straggle in IDUDGMOS on the circuit performance is observed. Fig. 4 is the basic circuit of a 3 stage and a 5 stage ring oscillator, designed using inverter. In an inverter circuit, a signal faces two types of delay, rise time delay and fall time delay. The fall time delay sPHL or the delay during high to low transition is represented as in Eq. (1).
sPHL ¼
C load ðV OH V 50% Þ ½19 Iav g:HL
ð1Þ
where C load is the load capacitance, Iav g:HL is the average current during a high to low transition, V 50% is the voltage point where the voltage is half of VDD and VOH is the maximum output voltage during the ‘‘HIGH” output of the inverter. The frequency of oscillation, fosc for the oscillator circuit designed using inverter is given as in Eq. (2).
f osc ¼
1 ½20 2 N TD
ð2Þ
where TD is the propagation delay of each stage and N is the number of stages. The TD is dependent on sPHL [19] and N can be altered only during the pre-silicon design time of the circuit. For a CMOS based ring oscillator like Fig. 4 the frequency of oscillation cannot be changed once the circuit is fabricated. In Fig. 4 there are two oscillators where fosc is f osc ð3StageÞ ¼ 1=ð6 T D Þ for the three-stage oscillator and f osc ð5StageÞ ¼ 1=ð10 T D Þ for five-stage oscillator. Thus, for a CMOS ring oscillator the frequency of oscillation can only be changed by changing the number of stages at design time. For a variable-frequency application like VCO (Voltage Controlled Oscillator) this inverter-based ring oscillator would not be a good choice as the frequency cannot be varied by control voltage. For a VCO application, a differential amplifier-based ring oscillator as in Fig. 5 would be a better choice, where the frequency could be changed by a control voltage. However, it comes at a cost of increased number of transistor resulting in increased power consumption and size of the chip. The Iavg of a differential amplifier depends on the ISS, which is the tail current of the differential amplifier [20]. As a result, a control voltage can be
Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009
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Fig. 4. A schematic view of 5 stage and 3 stage CMOS ring oscillator.
Fig. 5. Differential amplifier based voltage controlled ring oscillator.
applied to the gate of the tail MOSFET of the differential amplifier to generate voltage controlled frequencies from the ring oscillator circuit. The bandwidth of such a differential amplifier based ring oscillator is limited due to the minor change in frequency with control voltage. To increase the controllability of the output frequency of the ring oscillator, a new design is proposed in this work in which the frequency can be tuned like a VCO and can be stepped up or down by controlling the number of active stages N during the circuit usage. The range (Nmin, Nmax) between the minimum and maximum number of stages shall be determined by application requirement and results in maximum frequency of oscillation, fosc,max and in minimum frequency of oscillation, fosc,min respectively. The proposed circuit is designed using IDUDGMOS which has two independently driven gates. For IDUDGMOS, the channel current is controlled by both Vgsb and Vgsf, which is front gate to source
voltage and back gate to source voltage, respectively [21]. Now, by changing the Vgsb, channel current is modulated and the back gate dependency of corresponding transconductance gm is represented by gm(Vgsb), where Vgsf is fixed. As a result, for a fixed Vgsf, drain current Id of the IDUDGMOS at any instant is controlled by the product of gm(Vgsb) and Vgsf and is represented as
Id ¼ g m V gsb ðtÞ V gsf
ð3Þ
Eq. (3) shows that by changing the Vgsb it is possible to change the current through the IDUDGMOS. This in turn causes a change in the Iavg of the inverter, which will affect the TD of the inverter circuit [19]. In IDUDGMOS based inverter the Iavg can be modulated by changing the back gate voltage of the nIDUDGMOS. In Fig. 6 the back gate of all the nIDUDGMOS of inverters are connected together, forming a control terminal for the ring oscillator, where one applies the tuning voltage VtuneN. Variation of VtuneN will
Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009
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Fig. 6. Circuit diagram of proposed programmable IDUDGMOS based ring oscillator.
modulate the channel current, resulting in an inversely proportional variation of propagation delay of the inverter. Thus, VtuneN and fosc are directly proportional. Thus, keeping N fixed, fosc for the inverter based ring oscillator is tuned by changing the tied back gate voltage of nIDUDGMOS devices in the oscillator. Since the design is CMOS based, it reduces the number of transistor in comparison to differential amplifier based VCO and at the same time provides the advantages of voltage controlled frequency like VCO. Next challenge is to change the N during the operation of the circuit to step up or down the frequency for a larger span. The N can be changed by providing a programmable hardware scheme as shown in Fig. 6, where the input of first inverter, Vout, is connected to output of each odd stage of inverter beyond 3, via a transmission gate based switch. As a result, the effective number of stages of the oscillator depends on the switch that is ‘‘ON”. Fig. 6 shows the feedback path via switches going back to the input of the first inverter. If the target stage of oscillator is N = 3 then, VcontrolP3 and VcontrolN3 will be set to 0 V and 1 V, respectively, to turn ‘‘ON” the switch for the three-stage oscillator. Similarly, to increase N further, the corresponding switch circuits will be enabled to send the proper feedback path back to the input of first inverter. Thus, one has a programmable ring oscillator where the coarse frequency is controlled by changing the number of stages and the frequency is fine-tuned by changing the VtuneN. The programmable oscillator designed is simulated for three different LS of IDUDGMOS to study the analog performance of the programmable ring oscillator for process-related variations. In the next section, performance study of the proposed circuit is done. 4. Analog performance study In Fig. 7 the performance of the three oscillator circuits designed using the IDUDGMOS device shows that the maximum frequency achieved, corresponding to three stage, is about 86.4 GHz for LS = 7 nm followed by 63.9 GHz for LS = 5 nm and 55.2 GHz for LS = 3 nm. The frequency of the oscillator circuit, governed by Eq. (2), suggests that the circuit having the highest TD will
Fig. 7. Variation of output frequency (fosc) as a function of number of stages (N) for designed oscillator for constant Vgsb = 0.7.
have the lowest fosc [20]. It is observed that increase in LS shortens the effective channel length which results in increased channel current, causing a decrease in TD. As a result circuit designed with IDUDGMOS having highest LS = 7 nm will have the minimum TD resulting in highest fosc followed by LS of 5 nm and 3 nm. The number of stages in the circuit is varied by switching on appropriate feedback path as described in the previous section. In Fig. 8 ratio of frequency variation (Df) and minimum frequency is considered as the measure of change in frequency. Fig. 8 shows the variation in ratio of Df and minimum frequency (f) for oscillator having N = 3 with respect to the change in back gate control voltage. It is exhibited that all three circuits show a linear change of frequency with VtuneN and the change is maximum for the circuit designed with the IDUDGMOS of highest LS = 7 nm due to the maximum channel current. Thus using this oscillator circuit nearly two times improvement of bandwidth in comparison to the previous literature [7] is achieved. Thus, by changing the number of stages using switch
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Fig. 8. Variation of output frequency as a function of tuning voltage (VtuneN) for the designed oscillator for N = 3.
we can change the core frequency and by changing the back gate voltage frequency can be fine-tuned. Hence, the circuit can be used as a programmable oscillator for a wide range which results in few interesting application of the proposed circuit like VCO and frequency modulation. Fig. 9 shows linearity performance study of the proposed circuit from the output power vs. input power characteristics of three oscillator circuits which show that the circuit is having a linear characteristics up to 8 dB beyond which the gain become saturated. Circuit with lower LS shows larger linear range of operation due to large gain property [9] of individual inverter stage of oscillators. Fig. 9 shows the exact agreement with this where LS = 3 nm based device having a linear range of operation up to 7 dB followed by 8 dB for LS = 5 nm and 10 dB for LS = 7 nm. Linearity of the circuit is also measured from the harmonic distortion of the circuit which is measured by Total Harmonic Distortion (THD) [22] as shown in Fig. 10 which shows that the circuit is having a low value of distortion and THD increases with number of stages. Low value of THD represents that the circuit is having a linear and low distortion performance for a wide range of frequency due to wide bandwidth of IDUDGMOS. Maximum THD of 5 dB and minimum THD of 1 dB is resulted by oscillator designed with LS = 7 nm and LS = 3 nm IDUDGMOS based circuit respectively. All the mixed-mode AC device simulations are done using TCADbased [11] small-signal equivalent model of the device that includes the effect of parasitic capacitances like outer fringing
Fig. 10. Variation of THD of oscillator for different number of stages for designed oscillator.
Fig. 11. Power consumption of the oscillator circuit for three different LS.
Table 1 Performance summary of oscillator circuits of three different LS. Parameter
Bandwidth (GHZ) Input range (dB) Maximum THD (dB) Power consumption (mW)
Fig. 9. Output power versus input power of designed oscillator for different LS.
LS of IDUDGMOS used in oscillator design LS = 3 nm
LS = 5 nm
LS = 7 nm
8.72–55.2 7 1 6.61
10.1–63.9 8 3 7.60
13.6–86.4 10 5 8.69
and inner fringing capacitances as described in [23] and thus, the analog performances are faithful for comparative analysis. In Fig. 11, the power performance of three circuits for three different straggle lengths is shown. It is observed that the power consumption increases with increasing LS due to following reason. With the increase in LS the effective channel length decreases causing increased Id and resulting in higher power consumption. The power consumption is minimum for IDUDGMOS with LS = 3 nm and is about 6.61 mW which is 8 time smaller than existing circuit [6] (see Table 1). In this study IDUDGMOS device under analysis is a FDSOI device having equal Toxf and Toxb, known as symmetric FDSOI FET [24]. For a case where Toxb is much more than Toxf, the device operates like
Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009
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an asymmetric IDUDGMOS [24]. The decrease in Id of the asymmetric IDUDGMOS device with decreasing back gate voltage is much more than the symmetric IDUDGMOS, as gm of the asymmetric IDUDGMOS device decreases for thicker Toxb, due to lower inversion charge near back gate now to compensate the reduction in gm, a higher range of voltage is needed to be applied at the back gate, resulting in a requirement of higher VtuneN. 5. Conclusion In this work, design and performance analysis for programmable ring oscillator circuit for different lateral straggle (LS) of IDUDGMOS is presented. A strategy of controlling the frequency with both coarse and fine accuracy is presented. Coarse frequency is controlled by controlling the proper feedback path through control voltages and fine frequency control is done by changing the tuning voltage, which is applied to the back gate voltage of the IDUDGMOS. It is observed that the maximum frequency is achieved by the device with highest LS = 7 nm IDUDGMOS at 1 V DC supply. The bandwidth is highest for the maximum LS device based circuit. Linearity is highest and power consumption is lowest for minimum LS device. Thus the ring oscillator circuit designed with LS = 3 nm IDUDGMOS device is considered as the best choice for low power application. Proposed circuit produces highest output frequency (fosc,max) of 86.4 GHz and lowest output frequency (fosc,min) of 8.72 GHz for Nmin = 3 and Nmax = 19 of proposed oscillator respectively considering variation of LS. The circuit provides a maximum bandwidth of 73 GHz with a cost of 8.69 mW of power consumption with a 1 dB compression point at 10 dB of input power for LS = 7 nm device. This makes the programmable ring oscillator circuit ideal for low-power, handheld communication devices. References [1] Tham JL, Hull C, Ali A, Carr F, Chu R, Walley J, Koullias I. A direct-conversion transceiver chip set for 900 MHz (ISM band) spread-spectrum digital cordless telephone. In: IEEE international symposium on circuits and systems, vol. 4, 12–15 May 1996. p. 85–8. [2] Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong HSP. Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 2001;89(3):259–88. [3] Koley K, Syamal B, Kundu A, Mohankumar N, Sarkar CK. Subthreshold analog/ RF performance of underlap DG FETs with asymmetric source/drain extensions. Microelectron Reliab 2012;52(11):2572–8.
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Please cite this article in press as: Mukherjee S et al. Design and study of programmable ring oscillator using IDUDGMOSFET. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.11.009