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Design for reliability
MICROELECTRONICS RELIABILITY
PERGAMON
Microelectronics Reliability 40 (2000) 1285-1294 www.elsevier.com/locate/microrel
Invited paper
Design for reliability S. Minehane, R. Duane, P. O'Sullivan, K.G. McCarthy and A. Mathewson National Microelectronics Research Centre (NMRC), University College Cork, Ireland Abstract
The advent of the ULSI era, and the continuing decrease of the critical dimensions of MOSFETs, has raised a number of issues concerning the prediction of device reliability, and the consequences for overall product reliability. The established practice has been to assure reliability at the end of the lengthy product cycle. However, to achieve a shorter time-to-market, product reliability concerns should be addressed at the design stage ("design for reliability"). Accordingly, the design and implementation of reliability simulation tools, which give a prediction of the susceptibility of an IC design to device failure mechanisms, is becoming critical. This paper reviews some of the reliability simulation tools that are currently available to industry. The capability of the most popular of these tools is described for a number of different reliability hazards. A topical reliability simulation issue is addressed, and a statistical validation, comparing measured and simulated degraded ring oscillator data, is presented. © 2000 Elsevier Science Ltd. All rights reserved.
1. Introduction
One of the primary means for reducing cost, improving performance and increasing the scale of integration in an IC has been the miniaturisation of the MOSFET. While it is anticipated that there are still many more performance gains that can be achieved in the next 15 years, before the potential of CMOS technology is fully exhausted [1-5], scaling has intensified the reliability problems facing the IC designer [6-10]. The key to reliable IC production is to consistently manufacture a product that can perform it's intended function for a specified interval, under stated conditions. Up to now, product reliability has been largely implemented at the end of the process flow. Reliability assessment has been the almost exclusive consideration of process and device engineers, who optimised device architecture and process flow so that a given reliability target could be achieved. Typically, the target reliability would be well in excess of the actual required device lifetimes in so-called "worst-case" circuit operation. This
worst-case approach to defining product reliability may have been sufficient when there was a large margin between the required product lifetime and worst-case device lifetime figures, but there is evidence to suggest that the worst-case lifetime figures no longer meet product lifetime requirements [11, 12]. Nevertheless, ICs continue to be made without achieving conventional worst-case targets. There are several reasons why product reliability is often assumed. In real circuit operation, devices are subjected to some type of duty cycle during their normal lifespan [11],and it would be unusual for a device to be continually biased at worst-case conditions. Furthermore, increased device lifetime has been observed under AC stress, as opposed to DC stress, for some failure mechanisms [13]. However, it is important that more realistic reliability evaluation practices are established, so that the IC designer can have a clearer understanding of any potential design pitfalls. For this reason, the concept of "building in reliability" (BIR) [14-17] into a product has become essential. In this procedure, the key parameters
0026-2714/00/$ - see front matter. © 2000 Elsevier Science Ltd. All rights reserved. PII: S0026-2714(00)00138-4
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Building in reliability (BIR)
:~totype]
Concept
~ Reliability Evaluation
Volume Production
Conventionalloop Fig. 1: Design for reliability in the context of a BIR methodology. from all aspects of the product cycle - be it the design, fabrication or testing stages - that affect product reliability are determined and controlled. The success of any BIR scheme in ensuring overall product reliability is contingent on the implementation of comprehensive design for reliability (DFR) strategies which, in turn, ensure that each product design is considered individually and optimised as much as possible for reliability before committing to silicon [ 18]. The position of DFR in the context of a BIR methodology is illustrated schematically in Fig. 1. By suitable use of reliability simulation, the goal is to reduce the number of passes through the conventional loop needed for a reliable product. This will minimise the expensive design-test-redesign cycle, thus reducing the product time-to-market and development costs. As a result, reliability can then be built into the final circuit design, while allowing a designer to carefully weigh design tradeoffs and utilise the full potential of advanced ULSI technologies. There are three distinct areas in which the implementation of DFR strategies are.appropriate: (i) technology-level, where various material and structural failure mechanisms can be simulated using technology computer aided design (TCAD) tools [19-21]; (ii) circuit-level, where the reliability of complete IC designs can be assessed [2224]; and (iii) package-level, where IC systems and components are tested for mechanical, electrical and thermal reliability [25]. The focus of this paper is on the circuit-level DFR concern.
2. Reliability simulation: state-of-the-art There is now considerable interest within the semiconductor industry in the development of reli-
ability simulators, which aim to predict the degradation in circuit performance after a specified operating period. The different reliability simulation tools currently available to industry are considered in this section. First of all, the major reliability hazards are described. Some of the reliability simulators available to industry are then presented. Finally, as an illustration of the capability of these simulators, the operation of the most frequently used tool is described for a number of different reliability hazards.
2.1. Major reliability hazards There are a number of reliability hazards of concern to the IC designer, and these can be grouped in two categories. The first, the catastrophic wearout concerns, result in an abrupt circuit failure. Examples of this type of hazard are electromigration [26-28], time-dependent dielectric breakdown (TDDB) [29, 30], electrostatic discharge (ESD) [31-33], electrical overstress (EOS) [33] and stress migration [34, 35]. The second group, the gradual wearout concerns, result in the progressive decline in circuit performance during it's normal lifespan. Examples of this type of hazard include hot-carrier injection [3643] and stressinduced leakage current (SILC) [44--47]. Naturally, there can be some overlap between the two categories. For example, the early stages of electromigration can cause parametric change before the short or void causes catastrophic failure. In the Quality and Reliability Supplement to the 1997 U.S. Semiconductor Industry Association (SIA) Roadmap [48], nine semiconductor manufacturers were asked to forecast and prioritise their reliability related technology constraints for the year 2000. In total, nineteen reliability
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Table 1: Some commercial and in-house reliability simulators for the hot-carrier injection, electromigration and oxide reliability hazards. Hazard
Simulator(s)
Organisation
Hot-carrier injection
BERT[49] BTABERT,GLACIER[50] PRESS [51] iRULE [52]
University of California, Berkeley BerkeleyTechnologyAssociates (BTA), Inc. Philips Semiconductors University of Illinois
Electromigration
BERT [491 BTABERT,EmWorks[50] ElectronStorm [53] Railmill [54] iTEM [55] EmSim [56]
University of California, Berkeley Berkeley TechnologyAssociates (BTA), Inc. Simplex Solutions, Inc. Synopsys, Inc. University of Illinois Massachusetts Institute of Technology
Oxide reliability
BERT [491 BTABERT[50] iProbe-d [57]
University of California, Berkeley Berkeley TechnologyAssociates (BTA), Inc. University of Illinois
constraints were listed, and, of these, the five major hazards (in descending order of average priority) were oxide reliability, electromigration, ESD, stress migration, and hot-carrier injection. 2.2. Reliability simulators available
to
industry
Table 1 lists some of the in-house and commercial reliability simulators that are currently available to industry. It can be said that reliability simulation is becoming more mature, with the tools transferring from the universities to the commercial domain. There are now good links with commercial circuit design software, and as a result of this reliability simulation is likely to become an important link in the circuit design chain in the immediate future.
ity simulation for the hot-carrier, electromigration and oxide reliability hazards. 2.3.1. Hot-carrier injection The hot-carrier module of BERT is called the Circuit Aging Simulator (CAS) [61]. Provided that the necessary information is supplied to the simulator, CAS predicts: (i) the hot-carrierinduced degradation of the individual devices within the circuit, in the form of a lifetime figure; and (ii) circuit performance after a specified period of operation. The nMOSFET lifetime model at the centre of the operation of CAS is the Berkeley hot-carrier lifetime model [40]:
(I) 2.3. Berkeley Reliability Tools (BERT) Probably the most widely known, and used, circuit simulation program for reliability analysis is BTABERT, from Berkeley Technology Associates (BTA) [50]. BTABERT is the commercial version of Berkeley Reliability Tools (BERT) [49], which was developed at the University of California, Berkeley. BERT consists of several modules which cover various device reliability hazards. The simulator can be coupled with commercial circuit simulators, such as HSPICE [58], SmartSpice [59] and ELDO [60]. Since BERT is one of the more established of the available tools, the operation of this simulator will be described as a general overview of state-of-the-art reliabil-
where m and C are technology-dependent degradation parameters. The simulator input requirements are: (a) device model parameter sets extracted at increasing levels of hot-carrier-induced degradation; (b) a circuit description, with some extra BERT-specific commands; and (c) a set of degradation constants, extracted from the degradation data of a series of accelerated hot-carrier tests performed on numerous devices. The CAS pre-processor takes the input data and produces the appropriate circuit netlist, which is passed to the circuit simulator, and a series of intermediate files which are used to communicate with the post-processor. The circuit simulator uses
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the netlist to calculate nodal current and voltage information, which is used by the post-processor in it's calculation of drain and substrate currents for each device. Drain and substrate currents in each device are required in order to make reliability predictions based on the Berkeley model presented in Eqn. 1. The input waveform described in the circuit description is assumed to repeat itself continuously for the duration of the circuit lifetime in a quasi-static fashion. The post-processor takes the output data and calculates a value for a coefficient called age for each transistor: / /~ub "Xm / / age = \-/~7~/
Ias H--~
•
t
(2)
where the degradation parameter H is linearly related to C from Eqn. 1. This age parameter is a means of relating the degraded device data to normal operating conditions, and simply allows the easy application of the Berkeley model in a quasistatic manner. Each of the supplied stressed device parameter sets includes an a9e parameter. The value of device a9 e after a period of constant-bias stress is easily calculated. Since all parameters except time, t, can be taken as constant, this reduces the integration to simple multiplication. Using the values of a9e calculated by BERT, a degraded parameter set for each transistor is calculated by interpolation (or by extrapolation if necessary), between the recorded data sets. The circuit is resimulated using the degraded parameter set, yielding a prediction of circuit performance as a function of time.
more conveniently, use the layout extractor. From the layout, the extractor determines the circuit elements and ~enerates the nodal waveforms for the circuit. The electromigration analysis is performed and the results can be back annotated on the layout in the form of current density contour maps. The critical interconnects, contacts and vias can be marked, and information on the failure rate and cumulative percent failure is provided. An advisory for layout modification is also provided. 2.3.3. Oxide reliability
The oxide reliability simulation module of BERT is the Circuit Oxide Reliability Simulator (CORS) [81]. The inputs required are: (a) the test structure data, which usually consists of a distribution of times to breakdown measured from a population of capacitors which are subjected to a constant voltage stress; (b) a circuit description, which lists the number of devices and the area and edge components of each device; and (c) the circuit stimuli over the time period of the simulation. It is assumed in the lifetime calculations that these stimuli are applied repeatedly over the entire device lifetime. The circuit description and bias conditions are input to the circuit simulator, which is usually a SPICE-type simulation tool. This allows the bias on each device to be calculated. Then the bias information, the area and edge information, and the test structure data is combined using the area and field acceleration models, and the failure probability of each device and the overall circuit is calculated. The user can then determine if the circuit will meet a specific reliability requirement at, say, 10 years of operation.
2.3.2. Electromigration
There are two ways that the BERT simulator can be used to predict electromigration effects on circuit performance [49]. In the first, the user can simply provide a schematic of the circuit and the desired reliability specification (failure rate after a certain number of operating hours) at the prelayout stage. Based on these inputs the simulator will generate the nodal current and voltage waveforms which are then provided to the electromigration analysis engine. This analysis engine then provides layout guidelines for the width and length of each interconnect and a safety factor for each contact or via in the circuit. In the second mode of operation, the user can provide the layout geometry for all of the interconnects, contacts and vias for the layout by hand, or
2.4. Discussion
It is obvious that the two reliability hazards that have attracted the most attention in reliability simulation research have been the hot-carrier [52, 61-75] and electromigration concerns [55,76-80]. There has also been additional research on investigating the susceptibility of circuits to the oxide [81-83], ESD [84, 85] and hot-carrier bipolar [86] reliability concerns. It is also evident that much work remains before realistic reliability simulation will become commonplace. A study by Jiang et al. [75] has raised a number of interesting issues on the question of hot-carrier reliability simulation. One of these issues, namely the extraction of SPICE model para-
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meters for hot-carrier reliability simulation, is addressed in the following section. 3. A reliability simulation issue: SPICE model parameter extraction One of the key input requirements of any hotcarrier reliability simulator tool are sets of SPICE model parameters extracted at varying degrees of hot-carrier stress. However, there has been very little published research on a correct approach to this task. Careful parameter extraction and validation of the simulator is vital, in order to obtain meaningful simulations. In this section, the application of novel direct BSIM3 [87] parameter extraction techniques [88] to hot-carrier reliability simulation is presented. Direct techniques are advantageous in this context, because they produce physically-relevant parameter sets from a minimum amount of data, and the extracted parameters follow a monotonic trend with respect to stressing time [89]. In addition, a statistical validation, comparing measured and simulated degraded ring oscillator data using a novel hot-carrier reliability simulation framework, is presented. As an illustration of the accuracy of the direct parameter extraction techniques in modelling the changes in device characteristics due to hotcarrier injection, Fig. 2 compares measured and fitted (a) linear and (b) output characteristics for a 10#m/0.35#m nMOSFET, which has been subjected to a hot-carrier stress. It is clear that the BSIM3 model, coupled with the direct extraction techniques, achieves a very accurate representation of device behaviour before and after stress.
As a further illustration of the accuracy of the techniques, Fig. 3 demonstrates a comparison between measured and fitted threshold voltage for a number of short-channel devices of a constant width of 10#m, which have been subjected to a hot-carrier stress. It is observed that the change in the threshold voltage due to hot-carrier effects increases as the drawn channel length decreases. In particular, the channel length at which the "peak" in the curve occurs also decreases. The direct parameter extraction techniques cope very well with these effects, and a very accurate representation of the threshold voltage as a function of geometry before and after stress is achieved. 0.64
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S. Minehane et al./ Microelectronics Reliability 40 (2000) 1285-1294
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hot-carrier stress is presented in Fig. 4. Two sets of optimised parameter data are presented in Fig. 4. The first set uses the same initial parameter value, while the second set uses the previously-extracted parameter value as it's initial starting point. Both of these approaches are typically used in parameter extraction. It is observed that the evolution of the optimised parameter sets follow irregular trends. This indicates that parameters extracted during stress using optimisation are not extracted in the same manner each time. It is highly desirable, from a hot-carrier reliability viewpoint, to ensure that the extraction of device parameters during stress is performed in a consistent and repeatable manner. In contrast, the direct extraction strategy produces a much more monotonic degradation trend for N L X . This effect is noted for all parameters extracted.
modelled using a simple linear extrapolation from the extracted parameter data up to the lifetime criterion, i.e. t _< 7-. In our work, the evolution of both the key parameters and BSIM3 parameters with respect to time is modelled using a new formulation [89]:=
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In the context of hot-carrier reliability simulation, the evolution of key MOSFET parameters, such as Vth, 9m, and Ids(Un), has usually been modelled using a simple power-law [40]: A P = A . t '~
i
(3)
where P is the parameter, and n and A represent the degradation rate and magnitude, respectively, of the parameter. Typically, n is determined from the slope of a double log plot of the parameter change versus stressing time up to, and including, the lifetime criterion, 7-, which in our work is a 10% degradation in Ids(Un). The usual approach taken in hot-carrier reliability simulation is to model the evolution of the key parameters using the power-law approach of Eqn. 3, while the evolution of SPICE parameters is
. . .. . . ..
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Fig. 5: Comparison
of the directly-extracted degradation trend, and the power-law, linear and new fits for the BSIM3 parameters (a) N L X and (b) DVTO.
Fig. 5 illustrates the degradation trends for the BSIM3 threshold voltage parameters (a) N L X and (b) DVTO, which is used to fit the shortchannel effect. In both cases, three fits to the parameter data are also shown: (1) using simple linear extrapolation, (2) using Eqn. 3 and (3) using Eqn. 4. Both linear extrapolation and the powerlaw model predict parameter values for the later
S. Minehane et al./ Microelectronics Reh'abili~ 40 (2000) 1285-1294
stages of stress (t > 7-, open circles) from the parameter values extracted up to the lifetime criteria (t < 7", solid circles). This figure illustrates the shortcomings of both approaches in predicting parameter values for the later stages of hot-carrier stress. The new fits are a more realistic prediction of both N L X and DVTO behaviour during stress. To ensure the validity of the techniques presented here, it is essential to assess the correlation of measured and simulated degraded circuit data. A total of 47 accelerated hot-carrier stresses (l/da = 4.25V) were performed on 99-stage ring oscillators from a representative 0.35#'m CMOS technology. The aspect ratio of the devices were (W/L),~ = 10#m/0.35#m, and (W/L)p = 20#m/0.35/zm. The stresses were suspended every 1,000 seconds, to allow the measurement of the circuit propagation delay (PD) at V,td = 3.6V. 220
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Time (s) Fig. 6: Comparison of statistical measured and simulated degraded propagation delay (PD), for accelerated hot-carrier stresses performed at Vaa = 4.25V. Fig. 6 compares accelerated measured and simulated circuit degradation data. The simulated data was generated using a novel reliability simulation framework. Both mean (#) and distributed (+2.5cr) data is presented. It is seen that there is very good agreement between the measured data and the simulator predictions. The average simulated data, when no pMOSFET degradation is assumed, is also demonstrated. It can be seen that the predictions are incorrect in this case, indicating that pMOSFET degradation should not be ignored when simulating the influence of hot-carrier stress, as is sometimes done. The work presented in this section has successfully addressed the question of proper SPICE parameter extraction for hot-carrier reliability simulation. Direct parameter extraction techniques pro-
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duce a full set of SPICE parameters from a minimised I-V data set, and are ideally suited to this task. In addition, the extracted parameters follow a more monotonic trend with respect to time than those extracted using conventional methods. This is important, because the behaviour of SPICE parameters with respect to time can then be more confidently predicted. The task of modelling degraded parameter trends was considered, and a new formulation was presented. Finally, a statistical validation, which compared measured and predicted degraded ring oscillator data, was presented.
4. Future issues
4.1. IC design support Because reliability simulation is still a new research topic, there is still relatively little published research or guidelines available to the IC designer. In particular, there is a lack of studies comparing degraded and predicted circuit data. As a result, the task of performing reliability simulation on a design may seem daunting to the designer. Evidently, there is a need for the training of IC designers to fully understand reliability concepts and to promote the integration of reliability simulation and assessment into the design strategy. However, we believe that the provision of specialist in-house support for the reliability simulation task will become essential.
4.2. Simulation speed One of the big issues with hot-carrier reliability simulation to date has been simulation speed. Even with the introduction of support for faster event-driven simulators, such as ELDO, within the BERT framework, there is still a big issue with simulation speed. A new generation of tools, such as GLACIER [50], are emerging, and will allow the hot-carrier characterisation of cell library blocks to calculate the effect of hot-carrier stress on circuit timing. The associated speed improvements with the new methodology will contribute greatly to the hot-carrier reliability simulation of large digital ICs.
4.3. New failure mechanisms The scaling downwards of the critical geometries of the MOSFET will complicate and increase
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the number of reliability hazards faced by the IC designer. For channel lengths below 100nm, oxide charge due to hot-carrier effects extends over the entire channel length, thus impacting on the source barrier [90]. New measurement methodologies such as inverse modelling [91] are being used to extract oxide charge after hot-carrier stress, and provide insight into the physical effects of oxide charge on transistor performance. These studies should provide a physical basis for the analytical hot-carrier degradation models used in circuit reliability tools. At the moment, the number of mechanisms dealt with by commercial reliability simulators is limited to the more established hazards. Some of the newer failure mechanisms such as SILC and quasi-breakdown [47], which are important in present day technologies, have yet to be included in reliability simulators.
5. Summary A major goal of the design strategies for ULSI circuits based on deep-submicron technologies is to achieve "first-time right" designs. In the past, this goal has concentrated on achieving designs which exhibit the correct functionality from their first fabrication run. In more recent years, an increasing emphasis has also been placed on achieving designs which give satisfactory yields and exhibit in-built reliability from the outset. These latter attributes also help to eliminate the costs, and possible sales losses, caused by design iterations, while reducing the time-to-market. All of these design requirements can only be achieved by the development of comprehensive design for reliability (DFR) strategies. The implementation of DFR strategies requires simulation tools which allow IC designers to take account of reliability. The current state-of-the-art in reliability simulation was reviewed in this paper. Some of the tools currently available to industry were listed. In addition, the capability of the BERT reliability simulator in predicting circuit degradation due to the hot-carrier, electromigration and oxide reliability hazards was described. It is evident that much work has yet to be done before realistic DFR tools can be successfully implemented. A major hot-carrier reliability simulation issue, namely the extraction of SPICE parameters for use with the tools, was addressed in this paper. The successful implementation of direct SPICE parameter extraction techniques was
validated by comparing measured and predicted degraded ring oscillator data. The work presented in this paper will help in overcoming this problem and advancing the state-of-the-art.
References [1] Semiconductor Industry Association (SIA). International Technology Roadmap for Semiconductors (1999) available at www. s e m a t e c h , o r g [2] Iwai H. Downsizing of silicon MOSFETs beyond 0. l#m. Microelec. J. 29 (1998) 671-678. [3] Hu C. Silicon nanoelectronics for the 21st century. Nanotech. 10 (1999) 113-116. [4] Wong H-SP et al. Nanoscale CMOS. Proc. IEEE 87 (1999) 537-570. [5] Borkar S. Design challenges of technology scaling. IEEE Micro. 19 (1999) 23-29. [6] Yakeda E et al. VLSI Reliability Challenges: from device physics to wafer scale systems. Microelec. Reliab. 35 (1995) 325-363. [7] Galbraith JM et al. Reliability challenges for low voltage/low power integrated circuits. Qual. and Reliab. Eng. Intl. (1996) 271-279. [8] Krautschneider WHet al. Scaling down and reliability problems of gigabit CMOS circuits. Microelec. Reliab. 37 (1997) 19-37. [9] Takeda E. Challenges for giga-scale integration. Microelec. Reliab. 37 (1997) 985-1001. [10] Figueras J e t al. Test Challenges in Nanometric CMOS Technologies. Microelec. Eng. 49 (1999) 119-133. [11] Bellens R et al. Building-in reliability during library development: hot-carrier degradation is no longer a problem of the technologists only! Microelec. Reliab. 37 (1997) 1425-1428. [12] Nardi A e t al. Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies. IEEE Trans. Semiconductor Manufacturing SM12 (1999) 396-402. [13] Hu C. Reliability phenomena under AC stress. Microelec. Reliab. 38 (1998) 1-5. [14] McPherson JW. Does Building-In Reliability Imply More or Less Wafer-Level Reliability Testing? IEEE Intl. Integ. Reliab. Workshop Final Report, pp. 1-15, 1996. [15] Molyneaux Jet al. BIR - Breaking Down the Barriers. IEEE Intl. Integ. Reliab. Workshop Final Report, pp. 16-19, 1996. [16] Schafft HA et al. Toward a building-in reliability approach. Microelec. Reliab. 37 (1997) 3-18. [17] Leroux C et al. Building in reliability with latchup, ESD and hot carrier effects on 0.25#m CMOS technology. Microelec. Reliab. 38 (1998) 15471552.
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[18] Mathewson A et al. Modelling and Simulation Of Reliability For Design. Microelec. Eng. 49 (1999) 95-117. [19] Concannon A. Technology Computer Aided Design of Non Volatile Memory devices. PhD Thesis, National University of Ireland, 1996. [20] Thompson CV and Knowlton BD. Designing circuits and processes to optimize performance and reliability: metallurgy meets TCAD. Microelec. Reliab. 36 (1996) 1683-1690. [21] Duane R. Advances in MOS Memory Technology. PhD Thesis, National University of Ireland, 2000. [22] Hu C. IC Reliability Simulation. IEEE J. SolidState Circuits SSC-27 (1992) 241-246. [23] Verweij J and Lunenborg MM. On the design of a reliability circuit simulator. Microelec. Reliab. 35 (1995) 101-103. [24] Rempp H et al. Experiences on reliability simulation in the framework of the PROPHECY project. Microelec. Reliab. 39 (1999) 661-672. [25] Herard L. Packaging reliability. Microelec. Eng. 49 (1999) 17-26. [26] Li P-C and Young TK. Electromigration: the time bomb in deep-submicron ICs. IEEE Spectrum 33 (1996) 75-78. [27] Pierce DG and Brusius PG. Electromigration: a review. Microelec. Reliab. 37 (1997) 1053-1072. [28] Ryan JG et al. The evolution of interconnection technology at IBM. Microelec. Reliab. 37 (1997) 1282-1283. [29] Martin A et al. Dielectric reliability measurement methods: a review. Microelec. Reliab. 38 (1998) 37-72. [30] Kimura M. Field and temperature acceleration model for time-dependent dielectric breakdown. IEEE Trans. Electron Devices ED-46 (1999) 220229. [31] Voldman SH. State of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling. IEEE J. SolidState Circuits 34 (1999) 1272-1282. [32] Richier C et al. Comparison of different on-chip ESD protection structures in a 0.35#m CMOS technology. Microelec. Reliab. 37 (1997) 15371540. [33] Diaz CH et al. Building-in ESD/EOS reliability for sub-halfmicron CMOS processes. IEEE Trans. Electron Devices ED-43 (1996) 991-999. [34] Foley S e t al. A study of the influence of inter-metal dielectrics on electromigration performance. Microelec. Reliab. 38 (1998) 107-113. [35] Takatsuji H et al. Pure A1 thin film protective layer to prevent stress migration in AI wiring for thinfilm transistors. Surface and Coatings Tech. 125 (2000) pp. 167-172.
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[36] Ning TH et al. Emission Probability of Hot Electrons from Silicon into Silicon Dioxide. J. Electronic Materials 6 (1977) 65-76. [37] Eitan B and Frohman-Bentchkowsky D. HotElectron Injection into the Oxide in n-Channel MOS Devices. IEEE Trans. Electron Devices ED28 (1981) 328-334. [38] Poorter T and Zoestbergen P. Hot-Carrier Effects in MOS Transistors. in IEDM Tech. Dig., 1984, pp. 100-105. [39] Takeda E et al. High Field Effects in MOSFET's. in IEDM Tech. Dig., 1985, pp. 60-63. [40] Hu C et al. Hot-electron-induced MOSFET degradation - model, monitor and improvement. IEEE Trans. Electron Devices ED-32 (1985) 375-384. [41] Heremans P e t al. Consistent Model for the HotCarrier Degradation in n-Channel and p-Channel MOSFET's. IEEE Trans. Electron Devices ED-35 (1988) 2194-2200. [42] Choi J et al. Hot-Carrier-Induced Degradation of Metal-Oxide-Semiconductor Field Effect Transistors. J. Applied Physics 65 (1989) 354-357. [43] Vuillaume D et al. Hot-Carrier Injections in SiO2. Microelec. Reliab. 38 (1998) 7-22. [44] DiMaria DJ. Stress induced leakage currents in thin oxides. Microelec. Eng. 28 (1995) 63-66. [45] Rosenbaum E and Register LF. Mechanism of stress-induced leakage current in MOS capacitors, IEEE Trans. Electron Devices ED-44 (1997) 317323. [46] Scarpa A et al. Stress induced leakage current in ultra-thin gate oxides after constant current stress. Microelec. Eng. 36 (1997) 145-148. [47] Ghibaudo G et al. Emerging Oxide Degradation Mechanisms: Stress Induced Leakage Current (S1LC) and Quasi-Breakdown (QB). Microelec. Eng. 49 (1999) 41-50. [48] Semiconductor Industry Association (SIA). International Technology Roadmap for Semiconductors (1997) available at www. s e m a t e c h , org [49] Tu RH et al. Berkeley Reliability Tools - BERT. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems CAD-12 (1993) 1524-1534. [50] Homepage: w w w . b t a t , corn [51] Lunenborg MM et al. PRESS - a circuit simulator with built-in reliability model for hot-carrier reliability, in Proc. IEEE ESRER 1993, pp. 157-161. [52] Teng CC et al. iRULE: Fast Hot-Carrier Reliability Diagnosis using Macro-Models. in Proc. IEEE CICC, 1994, pp. 421-424. [53] Homepage: www. s i m p l e x , corn [54] Homepage: www. s y n o p s y s , c o m [55] Teng CC et al. iTEM: A temperature-dependent electromigration reliability diagnosis tool. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems CAD-16 (1997) 882-893. [56] Homepage: n i r v a n a , mit. e d u / e m s i m /
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[57] Li P-C et al. iProbe-d: a Hot-Carrier and Oxide Reliability Simulator. in Proc. IEEE IRPS, 1994, pp. 274-279. [58] Meta-Software Inc. HSPICE User's Manual. [59] Silvaco International. SmartSpice Manual. [60] Mentor Graphics Corp. ELDO Manual. [61] Lee PM et al. Circuit aging simulator (CAS). in IEDM Tech. Dig., 1988, pp. 134-137. [62] Sheu BJ et al. An integrated-circuit reliability simulator - RELY. IEEE J. Solid-State Circuits SSC24 (1989) 473-477. [63] Chung S et al. A new MOSFET hot carrier model in SPICE feasible for LSI reliability analysis, in Proc. Intl. Symp. on VLSI Tech. Sys., 1991, p. 283. [64] Leblebici Y and Kang SM. Simulation of hotcarrier induced MOS circuit degradation for VLSI reliability analysis. IEEE Trans. Reliab. R-43 (1994) 197-206. [65] Quader KN et al. Hot-carrier-reliability design guidelines for CMOS logic circuits. IEEE J. Solid-State Circuits SSC-29 (1994) 253-262. [66] Quader KN et al. Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation. IEEE Trans. Electron Devices ED-41 (1994) 681-691, [67] Lee PM et al. Simulating the competing effects of P- and N-MOSFET hot-carrier aging in CMOS circuits. IEEE Trans. Electron Devices ED-41 (1994) 852-853. [68] Thewes R et al. Evaluation of the hot-carrierinduced offset voltage of differential pairs in analogue CMOS circuits. Quality and Reliability Eng. Intl. 11 (1995) 273-277. [69] Hwang N and Forbes L. Hot-carrier induced series resistance enhancement model (HISREM) of nMOSFET's for circuit simulations and reliability projections. Microelec. Reliab. 35 (1995) 225239. [70] Chan V-H and Chung JE. Impact of NMOSFET hot-carrier degradation on CMOS analog subcircuit performance. IEEE J. Solid-State Circuits SSC-30 (1995) 644-649. [71] Li P-C and Hajj IN. Computer-aided redesign of VLSI circuits for hot-cartier reliability. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems CAD-15 (1996) 453-464. [72] Huh Yet al. Analysis of circuit degradation due to hot-carrier effects in 64Mb DRAMs. Solid-State Electron. 39 (1996) 1501-1506. [73] Horiuchi T. In-circuit hot-carrier model and its application to inverter chain optimization. IEEE Trans. Electron Devices ED-43 (1996) 14281432. [74] Minehane S at al. Direct Parameter Extraction for Hot-Carrier Reliability Simulation. Microelec. Reliab. 37 (1997) 1437-1440.
[75] Jiang W et al. Key Hot-Carrier Degradation Model Calibration and Verification Issues for Accurate AC Circuit-Level Reliability Simulation. in Proc. IEEE IRPS, 1997, pp. 300-306. [76] Winterton SS et al. Simulation and analysis of electromigration failure distributions. Microelec. Reliab. 34 (1994) 1047-1056. [77] Moosa MS and Poole KE Simulating IC reliability with emphasis on process-flaw related early failures. IEEE Trans. Reliab. R-44 (1995) 556561. [78] Roy K and Prasad S. Logic synthesis for reliability: an early start to controlling electromigration & hot-carrier effects. IEEE Trans. Reliab. R-44 (1995) 251-255. [79] Moosa MS et al, EFSIM: an integrated circuit early failure simulator. Qual. and Reliab. Eng. Intl. 12 (1996) 229-234. [80] Tekleab D et al. Modeling early failure in integrated circuit interconnect. Microelec. Reliab. 40 (2000) 991-996. [81] Rosenbaum E et al. Circuit reliability simulator - oxide breakdown module, in IEDM Tech. Dig., 1989, pp. 331-334. [82] Minami ER et al. Circuit-level simulation of TDDB failure in digital CMOS circuits. 1EEE Trans. Semiconductor Manufacturing SM8 (1995) 370-374. [83] Tu R et al. Simulating process-induced gate oxide damage in circuits. IEEE Trans. Electron Devices ED-44 (1997) 1393-1400, [84] Egger P et al. ESD monitor circuit - a tool to investigate the susceptibility and failure mechanisms of the charged device model. Qual. and Reliab. Eng. Intl. 12 (1996) 265-270. [85] Mergens Met al. Modular approach of a high current MOS compact model for circuit~level ESD simulation including transient gate-coupling behaviour. Microelec. Reliab. 40 (2000) 99-115. [86] Burnett JD. Hot-Carrier Reliability of Bipolar Transistors and Circuits. PhD Thesis, University of California, Berkeley, 1990. [87] Liu W et al. BSIM3v3.2.2 MOSFET Model Users' Manual. Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, 1999. [88] Minehane S e t al. Novel Parameter Extraction Techniques for Low-Voltage, Low-Power Technologies, in Proc. ESSDERC, 1999, pp. 452-455, [89] Minehane S e t al. Statistical Hot-Carrier Reliability Simulation using a Novel SPICE Parameter Evolution Model. To be presented at ESSDERC 2000. [90] Viullame D. Hot-Carrier Injections in SiO2 Microelec. Reliab. 38 (1998) 7-22. [91] Duane R et al. Inverse Modelling of trapped charge in Hot-Carrier Stressed nMOSFET. To be presented at ESSDERC 2000.
PERGAMON
Microelectronics Reliability 40 (2000) 1285-1294 www.elsevier.com/locate/microrel
Invited paper
Design for reliability S. Minehane, R. Duane, P. O'Sullivan, K.G. McCarthy and A. Mathewson National Microelectronics Research Centre (NMRC), University College Cork, Ireland Abstract
The advent of the ULSI era, and the continuing decrease of the critical dimensions of MOSFETs, has raised a number of issues concerning the prediction of device reliability, and the consequences for overall product reliability. The established practice has been to assure reliability at the end of the lengthy product cycle. However, to achieve a shorter time-to-market, product reliability concerns should be addressed at the design stage ("design for reliability"). Accordingly, the design and implementation of reliability simulation tools, which give a prediction of the susceptibility of an IC design to device failure mechanisms, is becoming critical. This paper reviews some of the reliability simulation tools that are currently available to industry. The capability of the most popular of these tools is described for a number of different reliability hazards. A topical reliability simulation issue is addressed, and a statistical validation, comparing measured and simulated degraded ring oscillator data, is presented. © 2000 Elsevier Science Ltd. All rights reserved.
1. Introduction
One of the primary means for reducing cost, improving performance and increasing the scale of integration in an IC has been the miniaturisation of the MOSFET. While it is anticipated that there are still many more performance gains that can be achieved in the next 15 years, before the potential of CMOS technology is fully exhausted [1-5], scaling has intensified the reliability problems facing the IC designer [6-10]. The key to reliable IC production is to consistently manufacture a product that can perform it's intended function for a specified interval, under stated conditions. Up to now, product reliability has been largely implemented at the end of the process flow. Reliability assessment has been the almost exclusive consideration of process and device engineers, who optimised device architecture and process flow so that a given reliability target could be achieved. Typically, the target reliability would be well in excess of the actual required device lifetimes in so-called "worst-case" circuit operation. This
worst-case approach to defining product reliability may have been sufficient when there was a large margin between the required product lifetime and worst-case device lifetime figures, but there is evidence to suggest that the worst-case lifetime figures no longer meet product lifetime requirements [11, 12]. Nevertheless, ICs continue to be made without achieving conventional worst-case targets. There are several reasons why product reliability is often assumed. In real circuit operation, devices are subjected to some type of duty cycle during their normal lifespan [11],and it would be unusual for a device to be continually biased at worst-case conditions. Furthermore, increased device lifetime has been observed under AC stress, as opposed to DC stress, for some failure mechanisms [13]. However, it is important that more realistic reliability evaluation practices are established, so that the IC designer can have a clearer understanding of any potential design pitfalls. For this reason, the concept of "building in reliability" (BIR) [14-17] into a product has become essential. In this procedure, the key parameters
0026-2714/00/$ - see front matter. © 2000 Elsevier Science Ltd. All rights reserved. PII: S0026-2714(00)00138-4
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Building in reliability (BIR)
:~totype]
Concept
~ Reliability Evaluation
Volume Production
Conventionalloop Fig. 1: Design for reliability in the context of a BIR methodology. from all aspects of the product cycle - be it the design, fabrication or testing stages - that affect product reliability are determined and controlled. The success of any BIR scheme in ensuring overall product reliability is contingent on the implementation of comprehensive design for reliability (DFR) strategies which, in turn, ensure that each product design is considered individually and optimised as much as possible for reliability before committing to silicon [ 18]. The position of DFR in the context of a BIR methodology is illustrated schematically in Fig. 1. By suitable use of reliability simulation, the goal is to reduce the number of passes through the conventional loop needed for a reliable product. This will minimise the expensive design-test-redesign cycle, thus reducing the product time-to-market and development costs. As a result, reliability can then be built into the final circuit design, while allowing a designer to carefully weigh design tradeoffs and utilise the full potential of advanced ULSI technologies. There are three distinct areas in which the implementation of DFR strategies are.appropriate: (i) technology-level, where various material and structural failure mechanisms can be simulated using technology computer aided design (TCAD) tools [19-21]; (ii) circuit-level, where the reliability of complete IC designs can be assessed [2224]; and (iii) package-level, where IC systems and components are tested for mechanical, electrical and thermal reliability [25]. The focus of this paper is on the circuit-level DFR concern.
2. Reliability simulation: state-of-the-art There is now considerable interest within the semiconductor industry in the development of reli-
ability simulators, which aim to predict the degradation in circuit performance after a specified operating period. The different reliability simulation tools currently available to industry are considered in this section. First of all, the major reliability hazards are described. Some of the reliability simulators available to industry are then presented. Finally, as an illustration of the capability of these simulators, the operation of the most frequently used tool is described for a number of different reliability hazards.
2.1. Major reliability hazards There are a number of reliability hazards of concern to the IC designer, and these can be grouped in two categories. The first, the catastrophic wearout concerns, result in an abrupt circuit failure. Examples of this type of hazard are electromigration [26-28], time-dependent dielectric breakdown (TDDB) [29, 30], electrostatic discharge (ESD) [31-33], electrical overstress (EOS) [33] and stress migration [34, 35]. The second group, the gradual wearout concerns, result in the progressive decline in circuit performance during it's normal lifespan. Examples of this type of hazard include hot-carrier injection [3643] and stressinduced leakage current (SILC) [44--47]. Naturally, there can be some overlap between the two categories. For example, the early stages of electromigration can cause parametric change before the short or void causes catastrophic failure. In the Quality and Reliability Supplement to the 1997 U.S. Semiconductor Industry Association (SIA) Roadmap [48], nine semiconductor manufacturers were asked to forecast and prioritise their reliability related technology constraints for the year 2000. In total, nineteen reliability
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Table 1: Some commercial and in-house reliability simulators for the hot-carrier injection, electromigration and oxide reliability hazards. Hazard
Simulator(s)
Organisation
Hot-carrier injection
BERT[49] BTABERT,GLACIER[50] PRESS [51] iRULE [52]
University of California, Berkeley BerkeleyTechnologyAssociates (BTA), Inc. Philips Semiconductors University of Illinois
Electromigration
BERT [491 BTABERT,EmWorks[50] ElectronStorm [53] Railmill [54] iTEM [55] EmSim [56]
University of California, Berkeley Berkeley TechnologyAssociates (BTA), Inc. Simplex Solutions, Inc. Synopsys, Inc. University of Illinois Massachusetts Institute of Technology
Oxide reliability
BERT [491 BTABERT[50] iProbe-d [57]
University of California, Berkeley Berkeley TechnologyAssociates (BTA), Inc. University of Illinois
constraints were listed, and, of these, the five major hazards (in descending order of average priority) were oxide reliability, electromigration, ESD, stress migration, and hot-carrier injection. 2.2. Reliability simulators available
to
industry
Table 1 lists some of the in-house and commercial reliability simulators that are currently available to industry. It can be said that reliability simulation is becoming more mature, with the tools transferring from the universities to the commercial domain. There are now good links with commercial circuit design software, and as a result of this reliability simulation is likely to become an important link in the circuit design chain in the immediate future.
ity simulation for the hot-carrier, electromigration and oxide reliability hazards. 2.3.1. Hot-carrier injection The hot-carrier module of BERT is called the Circuit Aging Simulator (CAS) [61]. Provided that the necessary information is supplied to the simulator, CAS predicts: (i) the hot-carrierinduced degradation of the individual devices within the circuit, in the form of a lifetime figure; and (ii) circuit performance after a specified period of operation. The nMOSFET lifetime model at the centre of the operation of CAS is the Berkeley hot-carrier lifetime model [40]:
(I) 2.3. Berkeley Reliability Tools (BERT) Probably the most widely known, and used, circuit simulation program for reliability analysis is BTABERT, from Berkeley Technology Associates (BTA) [50]. BTABERT is the commercial version of Berkeley Reliability Tools (BERT) [49], which was developed at the University of California, Berkeley. BERT consists of several modules which cover various device reliability hazards. The simulator can be coupled with commercial circuit simulators, such as HSPICE [58], SmartSpice [59] and ELDO [60]. Since BERT is one of the more established of the available tools, the operation of this simulator will be described as a general overview of state-of-the-art reliabil-
where m and C are technology-dependent degradation parameters. The simulator input requirements are: (a) device model parameter sets extracted at increasing levels of hot-carrier-induced degradation; (b) a circuit description, with some extra BERT-specific commands; and (c) a set of degradation constants, extracted from the degradation data of a series of accelerated hot-carrier tests performed on numerous devices. The CAS pre-processor takes the input data and produces the appropriate circuit netlist, which is passed to the circuit simulator, and a series of intermediate files which are used to communicate with the post-processor. The circuit simulator uses
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the netlist to calculate nodal current and voltage information, which is used by the post-processor in it's calculation of drain and substrate currents for each device. Drain and substrate currents in each device are required in order to make reliability predictions based on the Berkeley model presented in Eqn. 1. The input waveform described in the circuit description is assumed to repeat itself continuously for the duration of the circuit lifetime in a quasi-static fashion. The post-processor takes the output data and calculates a value for a coefficient called age for each transistor: / /~ub "Xm / / age = \-/~7~/
Ias H--~
•
t
(2)
where the degradation parameter H is linearly related to C from Eqn. 1. This age parameter is a means of relating the degraded device data to normal operating conditions, and simply allows the easy application of the Berkeley model in a quasistatic manner. Each of the supplied stressed device parameter sets includes an a9e parameter. The value of device a9 e after a period of constant-bias stress is easily calculated. Since all parameters except time, t, can be taken as constant, this reduces the integration to simple multiplication. Using the values of a9e calculated by BERT, a degraded parameter set for each transistor is calculated by interpolation (or by extrapolation if necessary), between the recorded data sets. The circuit is resimulated using the degraded parameter set, yielding a prediction of circuit performance as a function of time.
more conveniently, use the layout extractor. From the layout, the extractor determines the circuit elements and ~enerates the nodal waveforms for the circuit. The electromigration analysis is performed and the results can be back annotated on the layout in the form of current density contour maps. The critical interconnects, contacts and vias can be marked, and information on the failure rate and cumulative percent failure is provided. An advisory for layout modification is also provided. 2.3.3. Oxide reliability
The oxide reliability simulation module of BERT is the Circuit Oxide Reliability Simulator (CORS) [81]. The inputs required are: (a) the test structure data, which usually consists of a distribution of times to breakdown measured from a population of capacitors which are subjected to a constant voltage stress; (b) a circuit description, which lists the number of devices and the area and edge components of each device; and (c) the circuit stimuli over the time period of the simulation. It is assumed in the lifetime calculations that these stimuli are applied repeatedly over the entire device lifetime. The circuit description and bias conditions are input to the circuit simulator, which is usually a SPICE-type simulation tool. This allows the bias on each device to be calculated. Then the bias information, the area and edge information, and the test structure data is combined using the area and field acceleration models, and the failure probability of each device and the overall circuit is calculated. The user can then determine if the circuit will meet a specific reliability requirement at, say, 10 years of operation.
2.3.2. Electromigration
There are two ways that the BERT simulator can be used to predict electromigration effects on circuit performance [49]. In the first, the user can simply provide a schematic of the circuit and the desired reliability specification (failure rate after a certain number of operating hours) at the prelayout stage. Based on these inputs the simulator will generate the nodal current and voltage waveforms which are then provided to the electromigration analysis engine. This analysis engine then provides layout guidelines for the width and length of each interconnect and a safety factor for each contact or via in the circuit. In the second mode of operation, the user can provide the layout geometry for all of the interconnects, contacts and vias for the layout by hand, or
2.4. Discussion
It is obvious that the two reliability hazards that have attracted the most attention in reliability simulation research have been the hot-carrier [52, 61-75] and electromigration concerns [55,76-80]. There has also been additional research on investigating the susceptibility of circuits to the oxide [81-83], ESD [84, 85] and hot-carrier bipolar [86] reliability concerns. It is also evident that much work remains before realistic reliability simulation will become commonplace. A study by Jiang et al. [75] has raised a number of interesting issues on the question of hot-carrier reliability simulation. One of these issues, namely the extraction of SPICE model para-
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7.00
0.60
'
0.50
Vds=0.1V,
i
,
i
,
i
,
I
,
i
,
i
W/L = 10gm/0.35gm, Vbs = 0V, Vg s = 0.7-3.5V
W/L = 10gm/0.35pm f
Vbs=0V
6.00
-
'
-
-
Fit
Measured:
<
eroy
~ B e f o r e stress . ~ / /
Measured:
E 030
5.00
A
<
0.40 =
i
/
E
"~
4.00 3.00
m
020
2.00
0.10 0.00 0.0
_ ~ , - - - ~ _ ~
B e f o r e stress After s t y / / ~ f - ' ~ - - -
1.00
0.5
1.0
1.5
2.0
2.5
3.0
0.0¢ 0.0
3.5
0.5
1.0
1.5
Vg s (V)
2.0
25
30
35
qas (V)
(a)
(b)
Fig. 2" Comparison of measured and fitted nMOSFET (a) linear and (b) output characteristics before and after a hot-carrier-induced degradation of A l a s / I a s o = 10%.
meters for hot-carrier reliability simulation, is addressed in the following section. 3. A reliability simulation issue: SPICE model parameter extraction One of the key input requirements of any hotcarrier reliability simulator tool are sets of SPICE model parameters extracted at varying degrees of hot-carrier stress. However, there has been very little published research on a correct approach to this task. Careful parameter extraction and validation of the simulator is vital, in order to obtain meaningful simulations. In this section, the application of novel direct BSIM3 [87] parameter extraction techniques [88] to hot-carrier reliability simulation is presented. Direct techniques are advantageous in this context, because they produce physically-relevant parameter sets from a minimum amount of data, and the extracted parameters follow a monotonic trend with respect to stressing time [89]. In addition, a statistical validation, comparing measured and simulated degraded ring oscillator data using a novel hot-carrier reliability simulation framework, is presented. As an illustration of the accuracy of the direct parameter extraction techniques in modelling the changes in device characteristics due to hotcarrier injection, Fig. 2 compares measured and fitted (a) linear and (b) output characteristics for a 10#m/0.35#m nMOSFET, which has been subjected to a hot-carrier stress. It is clear that the BSIM3 model, coupled with the direct extraction techniques, achieves a very accurate representation of device behaviour before and after stress.
As a further illustration of the accuracy of the techniques, Fig. 3 demonstrates a comparison between measured and fitted threshold voltage for a number of short-channel devices of a constant width of 10#m, which have been subjected to a hot-carrier stress. It is observed that the change in the threshold voltage due to hot-carrier effects increases as the drawn channel length decreases. In particular, the channel length at which the "peak" in the curve occurs also decreases. The direct parameter extraction techniques cope very well with these effects, and a very accurate representation of the threshold voltage as a function of geometry before and after stress is achieved. 0.64
.
.
.
.
.
.
.
.
i
.
.
.
.
.
.
.
.
W = lO~m, Vds = 0.1V, Vbs = OV 0.62 0.60 0.58 e0.56
/
---
Fit (Before Stress)
/
Fit (After Stress)
0.54
Measured
0 52 0.50 10 -7
i
i
,
t
Before Stress
:
After Stress
, , llll
I
10 .6
. . . . . . . 10-5
Ldraw n (m) Fig. 3: Vth vs. Lctrawn for a range of nMOSFETs of constant W -- 10#m before & after hotcarrier stress. A comparison of directly-extracted and optimised parameter values for the BSIM3 reverse short-channel effect parameter, N L X , during a
S. Minehane et al./ Microelectronics Reliability 40 (2000) 1285-1294
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hot-carrier stress is presented in Fig. 4. Two sets of optimised parameter data are presented in Fig. 4. The first set uses the same initial parameter value, while the second set uses the previously-extracted parameter value as it's initial starting point. Both of these approaches are typically used in parameter extraction. It is observed that the evolution of the optimised parameter sets follow irregular trends. This indicates that parameters extracted during stress using optimisation are not extracted in the same manner each time. It is highly desirable, from a hot-carrier reliability viewpoint, to ensure that the extraction of device parameters during stress is performed in a consistent and repeatable manner. In contrast, the direct extraction strategy produces a much more monotonic degradation trend for N L X . This effect is noted for all parameters extracted.
modelled using a simple linear extrapolation from the extracted parameter data up to the lifetime criterion, i.e. t _< 7-. In our work, the evolution of both the key parameters and BSIM3 parameters with respect to time is modelled using a new formulation [89]:=
1.6 0
Directly-extracted Optimised using previous - - 0 - - Optimised using same initial
125 1.20 1.15 O
1.10
X
1.05 Fits."
0.95
(1) Linear fit (2) Power-law fit (3) New fit
0.90
1.0
Z
o8
10 3
10 4
10 5
(a)
Di,ectJv-extracted DVT0:/i;;]
0 . 9 2
. . . . . . . .
0.90 . . . . . . . .
10 2
"~ ~"(3) \ \ (2)
Time (s)
0.6 0.4
~ ( 1 )
0.85 102
1.2
..I
1,00
1.4
E ~'~ x
(4)
where B p and np are the SPICE parameter evolution coefficients for each parameter, and are extracted from parameter data for t < 7-.
x z...l
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•
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i
. . . . . . . .
10 3
i
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.
.
.
.
.
.
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,
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. . . . . . . .
i
.
.
.
.
.
.
.
.
.
.
t-
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Fig. 4: Evolution of directly-extracted and optimised values of the BSIM3 parameter N L X during hot-carrier stress.
I>n
0.86
.
o04 0.82
In the context of hot-carrier reliability simulation, the evolution of key MOSFET parameters, such as Vth, 9m, and Ids(Un), has usually been modelled using a simple power-law [40]: A P = A . t '~
i
(3)
where P is the parameter, and n and A represent the degradation rate and magnitude, respectively, of the parameter. Typically, n is determined from the slope of a double log plot of the parameter change versus stressing time up to, and including, the lifetime criterion, 7-, which in our work is a 10% degradation in Ids(Un). The usual approach taken in hot-carrier reliability simulation is to model the evolution of the key parameters using the power-law approach of Eqn. 3, while the evolution of SPICE parameters is
. . .. . . ..
.
.
--
_
(1) Linear fit (2) Power-Haw fit
1
__
{?) p.e.~.!!t ...........
0.80 10 2
10 3
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............... 10 4
10 5
12) 1
1 10 6
Time (s) (b)
Fig. 5: Comparison
of the directly-extracted degradation trend, and the power-law, linear and new fits for the BSIM3 parameters (a) N L X and (b) DVTO.
Fig. 5 illustrates the degradation trends for the BSIM3 threshold voltage parameters (a) N L X and (b) DVTO, which is used to fit the shortchannel effect. In both cases, three fits to the parameter data are also shown: (1) using simple linear extrapolation, (2) using Eqn. 3 and (3) using Eqn. 4. Both linear extrapolation and the powerlaw model predict parameter values for the later
S. Minehane et al./ Microelectronics Reh'abili~ 40 (2000) 1285-1294
stages of stress (t > 7-, open circles) from the parameter values extracted up to the lifetime criteria (t < 7", solid circles). This figure illustrates the shortcomings of both approaches in predicting parameter values for the later stages of hot-carrier stress. The new fits are a more realistic prediction of both N L X and DVTO behaviour during stress. To ensure the validity of the techniques presented here, it is essential to assess the correlation of measured and simulated degraded circuit data. A total of 47 accelerated hot-carrier stresses (l/da = 4.25V) were performed on 99-stage ring oscillators from a representative 0.35#'m CMOS technology. The aspect ratio of the devices were (W/L),~ = 10#m/0.35#m, and (W/L)p = 20#m/0.35/zm. The stresses were suspended every 1,000 seconds, to allow the measurement of the circuit propagation delay (PD) at V,td = 3.6V. 220
i
i
i
99-stage 035~m Ring Oscillator
Vdd = 425V
210
t~
/
z~ / ~ 1 ~ " ~ ' ~
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"~
•
200 190 IX 180" 170 160
Measured: • g-values z~ ±2.5o-values
Fits No pMOS deg. 0
2000
40;0
60;0
8000
Time (s) Fig. 6: Comparison of statistical measured and simulated degraded propagation delay (PD), for accelerated hot-carrier stresses performed at Vaa = 4.25V. Fig. 6 compares accelerated measured and simulated circuit degradation data. The simulated data was generated using a novel reliability simulation framework. Both mean (#) and distributed (+2.5cr) data is presented. It is seen that there is very good agreement between the measured data and the simulator predictions. The average simulated data, when no pMOSFET degradation is assumed, is also demonstrated. It can be seen that the predictions are incorrect in this case, indicating that pMOSFET degradation should not be ignored when simulating the influence of hot-carrier stress, as is sometimes done. The work presented in this section has successfully addressed the question of proper SPICE parameter extraction for hot-carrier reliability simulation. Direct parameter extraction techniques pro-
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duce a full set of SPICE parameters from a minimised I-V data set, and are ideally suited to this task. In addition, the extracted parameters follow a more monotonic trend with respect to time than those extracted using conventional methods. This is important, because the behaviour of SPICE parameters with respect to time can then be more confidently predicted. The task of modelling degraded parameter trends was considered, and a new formulation was presented. Finally, a statistical validation, which compared measured and predicted degraded ring oscillator data, was presented.
4. Future issues
4.1. IC design support Because reliability simulation is still a new research topic, there is still relatively little published research or guidelines available to the IC designer. In particular, there is a lack of studies comparing degraded and predicted circuit data. As a result, the task of performing reliability simulation on a design may seem daunting to the designer. Evidently, there is a need for the training of IC designers to fully understand reliability concepts and to promote the integration of reliability simulation and assessment into the design strategy. However, we believe that the provision of specialist in-house support for the reliability simulation task will become essential.
4.2. Simulation speed One of the big issues with hot-carrier reliability simulation to date has been simulation speed. Even with the introduction of support for faster event-driven simulators, such as ELDO, within the BERT framework, there is still a big issue with simulation speed. A new generation of tools, such as GLACIER [50], are emerging, and will allow the hot-carrier characterisation of cell library blocks to calculate the effect of hot-carrier stress on circuit timing. The associated speed improvements with the new methodology will contribute greatly to the hot-carrier reliability simulation of large digital ICs.
4.3. New failure mechanisms The scaling downwards of the critical geometries of the MOSFET will complicate and increase
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s. Minehane et al./ Microelectronics Reliability 40 (2000) 1285-1294
the number of reliability hazards faced by the IC designer. For channel lengths below 100nm, oxide charge due to hot-carrier effects extends over the entire channel length, thus impacting on the source barrier [90]. New measurement methodologies such as inverse modelling [91] are being used to extract oxide charge after hot-carrier stress, and provide insight into the physical effects of oxide charge on transistor performance. These studies should provide a physical basis for the analytical hot-carrier degradation models used in circuit reliability tools. At the moment, the number of mechanisms dealt with by commercial reliability simulators is limited to the more established hazards. Some of the newer failure mechanisms such as SILC and quasi-breakdown [47], which are important in present day technologies, have yet to be included in reliability simulators.
5. Summary A major goal of the design strategies for ULSI circuits based on deep-submicron technologies is to achieve "first-time right" designs. In the past, this goal has concentrated on achieving designs which exhibit the correct functionality from their first fabrication run. In more recent years, an increasing emphasis has also been placed on achieving designs which give satisfactory yields and exhibit in-built reliability from the outset. These latter attributes also help to eliminate the costs, and possible sales losses, caused by design iterations, while reducing the time-to-market. All of these design requirements can only be achieved by the development of comprehensive design for reliability (DFR) strategies. The implementation of DFR strategies requires simulation tools which allow IC designers to take account of reliability. The current state-of-the-art in reliability simulation was reviewed in this paper. Some of the tools currently available to industry were listed. In addition, the capability of the BERT reliability simulator in predicting circuit degradation due to the hot-carrier, electromigration and oxide reliability hazards was described. It is evident that much work has yet to be done before realistic DFR tools can be successfully implemented. A major hot-carrier reliability simulation issue, namely the extraction of SPICE parameters for use with the tools, was addressed in this paper. The successful implementation of direct SPICE parameter extraction techniques was
validated by comparing measured and predicted degraded ring oscillator data. The work presented in this paper will help in overcoming this problem and advancing the state-of-the-art.
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