Design of hybrid flash-SAR ADC using an inverter based comparator in 28 nm CMOS

Microelectronics Journal 95 (2020) 104666

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Design of hybrid flash-SAR ADC using an inverter based comparator in 28 nm CMOS Dinesh Kumar B a, ∗ , Sumit K. Pandey a , Navneet Gupta b , Hitesh Shrimali a a b

School of Computing and Electrical Engineering, Indian Institute of Technology Mandi, Kamand, HP, 175005, India Minima Processor Oy, Espoo, Finland

A R T I C L E

I N F O

Keywords: ADC Successive approximation register (SAR) Comparator CDAC Split-cap

A B S T R A C T

This paper presents a hybrid design of flash based successive approximation register (SAR) analog-to-digital converter (ADC) with a resolution of 6 bits, operating at 1 GS/s. The dynamic comparator in traditional architecture is replaced by an inverter based comparator, for an energy efficient comparison. A segmented spilt capacitor array charge redistribution digital-to-analog-converter (CDAC) is used to achieve improved linearity, power, speed and area. Further, a 3 bit per clock cycle approach is adopted to achieve fast conversion time. The hybrid flash-SAR ADC has been designed and simulated in a standard 28 nm CMOS technology with VDD of 0.9 V and 1 GS/s of sampling rate. The designed ADC achieves a peak SNDR of 35.56 dB and an SFDR of 40.81 dB. The design achieves 5.61 effective number of bits (ENOB) with 2.33 mW of power consumption and figure-of-merit (FOM) of 47.7 fJ/conversion.

1. Introduction Communication systems such as RF receivers, ethernet, DSP based serial links require high speed and medium resolution ADCs [1,2]. The analog-to-digital converter (ADC) topology is chosen carefully to achieve the desired trade-off between the number of bits, sampling rate and the power consumption. Conventionally, a flash architecture is preferred for very high speed applications at the cost of power consumption and area [3,4]. In the flash architecture, number of decision-making comparators increases with the number of bits (2N -1 comparators for N bits) [5,6]. Note that, the SAR architecture is efficient to perform data conversion up to 100 MS/s [7–9]. Selection of a DAC architecture plays a vital role for the overall performance in a SAR ADC. The settling speed and accuracy of the DAC determine the conversion speed and effective number of bits (ENOB) of the ADC. The charge scaling DAC is preferred in SAR ADCs for their low power consumption and inherent sampling capability on the capacitor array [10]. Further to reduce the area of the DAC, a split-capacitor array based charge redistribution digital-to-analog-converter (CDAC) is a usual choice [11]. In the past few years, ADC architectures which combine two or more architectures together to achieve high performance have been implemented to and achieve high throughput with

low power consumption [12,13]. The high-speed flash ADCs use dynamic comparators to achieve fast conversion time and very good energy efficiency [5,11,14]. However, the high-speed dynamic comparators consume a large amount of power. So, another interesting approach is to use inverter as comparator for the flash ADCs [15]. For sensor applications [16,17], single ended ADC designs are used. A single ended ADC design reduces the overall power and area. But single ended designs are affected by noises and DC offset. These effects can be further avoided by using a signal conditioning circuitry. This paper describes the design of a 3-bit per stage hybrid flashSAR ADC for a sampling rate of 1 GS/s and a resolution of 6 bits. This work proposes a 6-bit segmented split-capacitor array CDAC for reduction in area and switching power dissipation. Moreover, in this paper, an inverter based comparator is proposed, to reduce the power consumption. A simple CMOS inverter based comparator is PVT invariant because of the usage of body-biased common-mode feedback circuitry [18]. It also exhibits similar performance comparing a conventional dynamic comparator. The proposed design improves the overall performance of the hybrid flash-SAR ADC in terms of figure of merit (FOM). The remaining part of the paper is organized as follows: Section 2 presents comparison between the conventional SAR architecture with

∗ Corresponding author. E-mail addresses: [email protected] (D.K. B), [email protected] (S.K. Pandey), [email protected] (N. Gupta), hitesh@iitmandi. ac.in (H. Shrimali). https://doi.org/10.1016/j.mejo.2019.104666 Received 24 January 2019; Received in revised form 14 September 2019; Accepted 17 November 2019 Available online 20 November 2019 0026-2692/© 2019 Published by Elsevier Ltd.

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Fig. 2. Idea: an inverter based comparator.

Fig. 1. The architecture of n-bit hybrid flash-SAR ADC.

the hybrid flash-SAR architecture. Section 3 describes the design of the proposed inverter based comparator. Selection of the CDAC architecture is discussed in Section 4. Section 5 presents the design and implementation of the hybrid flash-SAR ADC. The simulation results are discussed in Section 6 and the paper is summarized in Section 7.

Fig. 3. Complete inverter based comparator including biasing circuitry ([18]) with the aspect ratios for 5 stage inverter chain as MB1 = M1 = 0.51 μm/0.09 μm, MB2 = M2 = 0.3 μm/0.09 μm, MB3 = MB5 = 0.17 μm/0.03 μm, MB4 = MB6 = 0.1 μm/0.03 μm, second stage Mp2 = 2 × M1 , Mn2 = 2 × M2 , third stage Mp3 = 4 × M1 , Mn3 = 4 × M2 , fourth stage Mp4 = 8 × M1 , Mn4 = 8 × M2 , fifth stage Mp5 = 16 × M1 and Mn5 = 16 × M2 .

2. Conventional SAR and hybrid flash-SAR ADC The SAR and hybrid flash-SAR ADCs work on the binary search algorithm [19]. These ADCs work recursively on an analog input voltage to produce a digital output code. This section highlights some of the similarities and differences in the operation of both the ADCs.

3. Proposed inverter based comparator The comparator produces a respective output by comparing a variable input with a fixed threshold voltage. This motivates to use an inverter circuit which compares the variable input with a designed threshold voltage. The variation 𝛿 in the threshold voltage1 can be controlled through the offered resistances of pMOS and nMOS transistors in a CMOS inverter. The 𝛿 denotes the minimum resolution detectable by the inverter based comparator. Fig. 2 shows the equivalent circuit notations for an inverter as a comparator. The inverter provides an output as follows:

2.1. Conventional SAR ADC: revisited The SAR ADC performs a binary search between positive and negative reference voltages to produce a digital output for the input analog voltage applied to it. The search is a recursive technique and it requires N clock cycles to produce the converted digital code (where, N is the number of bits at the output of an ADC). A SAR ADC consists of a sample and hold (S/H), a comparator, a SAR digital logic and a DAC in its simplest form. The conventional SAR architecture is best suitable for medium-speed ADC realization (< 100 MS/s). The limitation of the architecture is it’s bandwidth requirement of the comparator (>N × Fs ) for sampling frequency of Fs . Hence, it consumes more power, if the ADC is designed for sampling speed higher than 100 MS/s. Furthermore, there is a requirement of the sub blocks to be designed with the bandwidth of (N × Fs ), for sampling frequency of Fs [7].

VOUT = 1

if V∗IN < VCM

VOUT = 0

if V∗IN > VCM .

∗

(1)

Where, VIN is a sampled input voltage VIN , VOUT is the output and VCM is the common-mode voltage. The signal V∗IN is compared with VCM to produce VOUT . The operation describes the relay-characteristic with saturation. Hence, the inverter can be treated as a comparator with switching threshold of VCM as the comparison value, where VCM = VDD ∕2. Fig. 3 shows the realization of such a comparator using a chain of inverters. The number of stages and the aspect ratios of the transistors depend upon speed, resolution, and logical effort requirements [20]. Note that the purpose of transistors M1 and M2 is to reduce offset and kick-back noise [21]. The first stage of the chain acts as a preamplifier stage similar to a conventional comparator. The size of the transistors increases in a geometric progression of two with each stage, considering the logical effort requirement. Since the biasing circuit for the inverter based comparator in Fig. 3 is biased at VDD ∕2, the inverters consume static current. The inverter formed by the transistors MB1 and MB2 consumes a static current of 6.032 μA. Whereas the inverters formed by MB3 - MB6 consume a static current of

2.2. Hybrid flash-SAR ADC Fig. 1 shows an n-bit per stage hybrid flash-SAR ADC, where n is the number of bits resolved in one cycle. The hybrid flash-SAR ADC uses the conventional binary search algorithm along with parallel conversion of partial bits. The search space is divided into 2n parts. Hence, for N/n clock cycles, a hybrid flash-SAR ADC produces N number of bits. The hybrid flash-SAR ADC requires 2n -1 comparators, 2n -1 DACs, and supporting circuitry. However, the stringent requirements on the comparator bandwidth are bypassed in the hybrid flash-SAR architecture. The comparator design for the hybrid flash-SAR ADC needs atleast (N/n)+1 times Fs of the bandwidth. The number of stages and number of bits per stage (n) for a hybrid flash-SAR ADC is a trade-off between area and speed.

1

2

The threshold voltage may vary with various process corners.

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capacitor. It is noteworthy that the total capacitance of the array is same as that in conventional binary weighted CDAC. However, the capacitance spread (ratio of maximum capacitance value to the minimum capacitance value) is less in the segmented CDAC with smaller switches. In a hybrid flash-SAR ADC, the comparators output is in a thermometric fashion. The thermometric code can be directly fed to the CDAC. It eliminates the need for a thermometric-to-binary (T-to-B) code converter in the comparator to DAC loop and hence reduces the overall loop delay. In order to optimize area, power and speed, a split capacitor array is combined with the segmented CDAC architecture. The segmented architecture reduces the need for a thermometric to binary conversion during comparator output feedback. The segmented split-capacitor array CDAC is shown in Fig. 5(a) for 6 bits. This architecture can further be improved for higher number of bits without affecting performance. Fig. 5(b) shows the design of the switch used in the CDAC. The split capacitor CDAC architecture allows us to use smaller capacitors. It also helps to use smaller switches. The switching power is reduced with reduction in a unit capacitance. The maximum capacitor in the split-capacitor DAC is 4C, whereas the conventional DAC requires 32C. The settling time and switching power are reduced by 10% and 37% respectively in split capacitor DAC [23], with comparing a conventional DAC. So, the reduced settling time of the CDAC provides sufficient time for the comparison operation. Furthermore, the bridge capacitor introduces a parasitic capacitance at the different plates of the capacitor. The DAC has been designed with keeping the parasitic capacitance budget well within half LSB. By proper selection of unit capacitor, the parasitic effects does not affect the performance of the DAC [23,24]. The split capacitance value is selected as Csplit = C ·2n/2 /(2n/2 − 1). The mismatch in the split capacitor value can add integral nonlinearity (INL) and differential nonlinearity (DNL) errors during switching. The linearity performance of the split capacitor array is discussed in Ref. [23]. The error (𝛾 ) in the unit capacitance value of the DAC affects the ADC linearity performance in the conversion process. The analog output of the ith DAC in the 1st cycle can be written as:

Fig. 4. Noise margin comparison for a single and five stage inverter chain.

3 μA. Fig. 3 also shows the circuit [18,22] used to bias the threshold voltage of the comparator. This circuit works on negative feedback. If either of nMOS or pMOS is stronger than the other, the output of the first stage of the biasing circuit will not be VDD ∕2. This will force the Δ change in the voltage at body terminal (ΔVbody ) around VDD ∕2. This will neutralise the stronger nMOS or pMOS by providing more or less current in the negative feedback loop, respectively. This allows the inverter threshold to be VDD ∕2 irrespective of process, voltage, and temperature (PVT) variation. The n-well of every pMOS in the inverter chain is connected with this terminal. Fig. 4 shows the difference in noise margins of a single inverter (NML1 and NMH1 ) and a five inverter chain (NML5 and NMH5 ). The chain of five inverters shows a better input offset voltage capability. 4. Selection of the CDAC architecture The CDAC samples the input voltage and also converts the digital input (output of the SAR logic block) to an analog voltage. The voltage references are generated as the difference between the sampled voltage V∗IN and analog equivalent of 2n -1 bit patterns. Considering a n-bit/cycle hybrid flash-SAR ADC, the analog voltages generated by the DACs in the 1st cycle are given as: VDAC (i) = VCM − V∗IN + i(VDD ∕2n );

VDAC (i) = VCM − V∗IN + V(𝛾)MSB ;

The analog output of the ith DAC in the 2nd cycle can be written as: VDAC (i) = VCM − V∗IN + A(𝛾)MSB + V(𝛾)LSB ;

(2)

(5)

Where A(𝛾 )MSB is the analog voltage generated from the feedback of the comparator array, V(𝛾 )MSB and V(𝛾 )LSB are the voltages generated due to the error and the unit capacitance C. The values are computed for 6-bits of CDAC (Fig. 5(a)) as:

Where, VDAC (i) is the analog voltage generated by the ith DAC. The analog voltages generated by the DACs in the 2nd cycle are given as: VDAC (i) = VCM − V∗IN + Afb + i(VDD ∕22n );

(4)

(3)

V(𝛾)MSB =

Where, Afb is the analog voltage generated from the feedback of the comparator array in the 1st cycle. Any non-linearity associated with a CDAC impacts the performance matrices of the ADC in terms of INL, DNL, SNR etc. For this, the bottom plate sampling is preferred to avoid the parasitic capacitance which is prone to the non-linear effects. Considering these design facts, the CDAC is designed to achieve low power without use of separate sample and hold circuit. The reference levels for the flash ADC operation are provided by the CDAC. These levels are in accordance with the switching control voltage pattern from the SAR digital logic block. As the number of bits increases, the CDAC capacitance size increases. The settling time constant of the DAC should be sufficiently low so that the reference levels are ready for comparison. This implies that the resistance associated with the switches should be low with wider sized transistors. Also, the capacitance spread is more for high resolution designs. Hence, binary-weighted CDAC is not preferred for high resolutions. Considering the design facts, the segmented CDAC is best suitable for high resolution applications [11]. The segmented CDAC requires the maximum capacitor reduction from 32C to 8C, where C is the unit

V(𝛾)LSB =

[Σ6k=0 (Ck + 𝛾k )Bk ]VDD 23 C

[Σ10 (C + 𝛾k )Bk ]VDD k=7 k 26 C

, (6)

.

Where Ck +𝛾 k is the total capacitance connected to the switch Sk . When Sk is connected to VDD , Bk = 1 and when Sk is connected to GND, Bk = 0. The error voltage generated by the ith CDAC due to the error 𝛾 at tth sampled input voltage is written as [23,25]: V(i)error(t) ≈ INL(i)t ≈

[Σ10 𝛾 B ]V k=0 k(t) k(t) DD 26 C

.

(7)

The variation in the CDAC analog voltage can affect the ADC conversion process. In order to minimize the linearity errors, the error due to ith CDAC should be kept less than VDD /2N+1 . The DNL can be derived as the difference between two consecutive ith CDAC outputs and is written as [23,25]: DNL (i)t ≈ ΔV(i)error(t) = V(i)error(t) − V(i)error(t−1) , DNL (i)t ≈ 3

[Σ10 ( 𝛾(i)k(t) Bk(t) − 𝛾(i)k(t−1) Bk(t−1) )]VDD k=0 26 C

(8)

.

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Fig. 5. (a) The schematic diagram of a segmented split-capacitor array CDAC, (b) the schematic diagram of switch used in segmented split-capacitor array CDAC.

The INL and DNL for the hybrid flash-SAR ADC is a combined effect of 2n -1 CDACs in the DAC array. For better linearity, the deviation in V(𝛾 )MSB and V(𝛾 )LSB should be less than VDD /2n+1 and VDD /2N+1 respectively. In order to minimize the effects of parasitic split capacitance, bridge capacitor is realised for a minimum error 𝛾 split [26,27]. Fig. 6 shows the voltage waveform of different CDACs at different cycles. Referring to Fig. 5 (a), the top plate of the DAC is connected to VOUT voltage and the bottom plate is connected to VDD , VIN or GND. During the sampling cycle, the top and bottom plates are sampled with VCM and VIN voltages, respectively. Further explanation in the diagram during the 1st cycle is with VIN = VDD /2. Each DAC produces the corresponding voltage with respect to the bits assigned to them. For instance, DAC1 is assigned to the 3-bit 001. It generates a voltage VDAC (1) = VCM - V∗IN + (1 ·VDD /8) in the 1st cycle. Similarly, the other DACs generate the corresponding reference voltage levels (Eqn. (2)). The comparator array generates a thermometric code of 0000111 with respect to the DACs reference voltage levels. Its equivalent binary representation is 100. During the 2nd cycle, the thermometric code of 0000000 equivalent to the binary representation of 000. Here, the 6-bit digital representation for the sampled input VDD /2 is obtained as 100 000. Similarly for the next conversion cycle, the bottom plates of the DAC capacitors are sampled with a next sampled value. The diagram has been considered with the next sample of (VDD /2) + 1 LSB. The corresponding 6-bit digital output is 100 001. The process is repeated for all sampled values. 5. Implementation of hybrid flash-SAR ADC The 6-bit, 3-bit per stage hybrid flash-SAR ADC has been considered to explain the implementation part. The proposed ADC consists of four design blocks, viz. comparators, CDACs, SAR digital logic block and delay blocks. 5.1. Architecture

Fig. 6. The waveform of the 3 bit/cycle CDAC switching procedure.

Fig. 7 shows the block-diagram of the proposed flash-SAR hybrid 6-bit ADC. The 6-bit flash-SAR hybrid ADC takes 3 cycles for a conversion cycle including sampling cycle. In the 1st cycle, 3-bits are generated using 3-bit flash ADC. The 3-bit flash ADC is implemented using 7 inverter based comparators. The SAR digital logic block produces 3 bits based on the inputs from the 7 comparators (VOUT1 to VOUT7 ). At the end of the 1st cycle, the digital code from the SAR logic is converted into an analog value using 7 CDACs. The outputs from the CDACs are further compared with VCM using the inverter based comparators in the next cycle. Similarly, next 3-bits are generated by the SAR digital logic and end-of-conversion signal stores the 6 bits in the digital code registers. The hybrid flash-SAR ADC works on an asynchronous clock. The clock is generated by the delay block on the arrival of the start-ofconversion signal (SOC). The delay block works on the external clock (CLK). The delay specification of the delay block is derived from the worst case delay (across PVT corners) of the comparator. The number of

stages required for the chain is decided by the noise-margin and speed specifications of the comparator. The delay line provides required and matched delay with minimum sizes of pMOS and nMOS for a respective technology node and fan out specifications. 5.2. Operation Fig. 8 (a) shows the working operation in terms of flow chart for the proposed ADC. Fig. 8 (b) shows the corresponding timing diagram with start-of-conversion (SOC), sampling, switching, comparison, and endof-conversion (EOC) as digital control signals. The timing signal shows three cycles annotated on the signal. In the sampling phase, the input analog voltage VIN is sampled on all the capacitors of the DAC array. During the sampling phase, the output of the 7 DACs are in VCM due to the bottom plate sampling. The DAC array (DAC1 to DAC7 ) provides 4

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Fig. 7. (a) The block-diagram of a 3-bit per stage, 6-bit flash-SAR ADC, (b) The block-diagram of the delay cell.

the different voltage levels to the comparator array in the switching phase-I. The reference levels from the DAC during first switching phase is given by Eqn. (2). The single ended ADC architecture uses only VCM as the comparison voltage for all the comparators. Hence the inverter based comparator with switching threshold (VCM ) can be used in the ADC design. During the comparison phase-I, the comparators provide the thermometric code based on the DAC reference levels. The 7 bit thermometric code from the comparator array is converted to 3 bit binary code (D6 to D4 ) by a thermometric to binary converter (T-B). In switching phase-II, the SAR logic provides the thermometric code to the DAC array switches (S0 to S6 ). Based on the feedback to the DAC switches, the corresponding reference voltage is fed to the comparator array. The DAC reference levels for the second switching phase is given by Eqn. (3). The second comparison phase provides the successive binary bits (D3 to D1 ). The EOC pulse declares the end of conversion and stores the 6-bit digital output in the digital code registers. 5.3. Proposed inverter based comparison The inverter based comparators compare the voltages generated by the CDACs with VDD /2. The inverters have the threshold voltage of VDD /2 by design. For the resolution and speed specifications of the design, the number of inverter stages is chosen as five. The delay line is designed for a worst case delay of 95 ps. The offset specifications of the comparator is decided by the LSB specification of the ADC. For a 6 bit ADC with a VDD of 0.9 V, the offset value should be less than 14 mV. The parasitic input capacitance of the inverter based comparator at switching threshold is 0.7 fF and the capacitance variation is 0.1 fF across 0 to VDD . Fig. 9 (a) shows the comparison of comparator’s input offset voltage (IOV) for various process corners, with and without proposed bodybiasing circuitry of Fig. 3. These process corners are slow nMOS-slow pMOS (SS), fast nMOS-fast pMOS (FF), typical nMOS-typical pMOS (TT), fast nMOS-slow pMOS (FS), and slow nMOS-fast pMOS (SF). The plot shows that the IOV is more than the budget requirement of an LSB of 14.0625 mV without using body biasing circuitry. However, the plot exhibits tuned performance for the LSB when body-biasing circuitry of Fig. 3 is used. Moreover, the plot shows maximum IOV of 23 mV and 11 mV for with and without body biasing at SF corner respectively.

Fig. 8. (a) The flow diagram of the 6-bit hybrid flash-SAR ADC, (b) Timing diagram of the hybrid flash-SAR ADC.

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Fig. 9. (a) Variation of the comparator IOV with various process corners with and without body-biasing, (b) Histogram of input-referred offset voltage for inverter based comparator in Fig. 3.

Fig. 10. Histogram of the input-referred offset voltage (Monte-Carlo simulation with 1000 runs) for comparator designs: (a) [28] (b) [29], (c) [30] and (d) [31].

Fig. 9 (b) shows the histogram of input-referred offset voltage for inverter based comparator. This statistical mismatch analysis is simulated (Monte-Carlo analysis with N = 1000 runs) for mismatches in both process and transistors. The analysis shows the mean value of 0.392 mV with standard deviation of 10.31 mV. Fig. 10 shows the histogram of input-referred offset voltage for comparator designs reported in recent papers ([28–31]). This statistical mismatch analysis is simulated (Monte-Carlo analysis with N = 1000 runs) for mismatches in both process and transistors. The analysis shows the mean value (𝜇 ) and standard deviation (𝜎 ) of the comparators. It should be noted that the comparators are designed and analysed for the specifications of the hybrid flash-SAR ADC in 28 nm CMOS. All the comparators have been designed to achieve 14 mV of the IOV to meet 6 bits of requirement. Table 1 shows the comparator performance comparison with stateof-artwork architectures. The designs ([28–31]) are based on strong arm latched comparator (dynamic comparator) with offset cancellation techniques. These structures use additional control signals for offset cancellation. It will in turn increase the complexity of the digital logic. The performance of the dynamic comparators does not include the complex digital clock generation circuitry. The performance of the inverter based comparator is comparable to other dynamic comparators without using additional clock signals. With the tradeoff in power, speed and offset, the proposed inverter based comparator achieves the desired specifications with reduced complexity for the equivalent performance at the lowest power. The biasing circuit for the inverter based comparator is designed specifically for 7 comparators, thereby reducing the power consumption and area of the inverter based comparator array. Unlike other dynamic comparators with a dedicated offset cancellation circuit, the biasing

circuit for the inverter based comparator can be shared by the other comparators. The biasing circuit is PVT independent and aids to achieve desired switching threshold for the inverter based comparator at VDD /2 for various cross-corners. 5.4. Segmented split capacitor array CDAC Referring to Fig. 8 (b), the designed ADC works for three cycles. In the first cycle all capacitors are charged with input voltage VIN . In the first comparison cycle, three most significant bit (MSB) capacitors are fed with the patterns from the SAR digital logic according to Table 2. In the next cycle, these patterns are replaced by the feedback from the SAR logic. This feedback is decided by the comparator outputs. Since there are seven comparators, one can use a segmented DAC for the 3 MSBs. This eliminates the need of a T-to-B converter in the loop. Hence, it improves the overall speed of the ADC. The design also uses seven CDACs. All of the CDACs generate different, but evenly spaced voltage levels. To generate these levels, SAR logic provides each DAC with different bit-patterns. The reference levels in the first cycle are 112.5 mV apart i.e. 3-bit resolution. In the second cycle, the reference levels are 14.06 mV apart i.e. 6-bit resolution. The optimal unit capacitor size for the CDAC is 8.66 fF, designed with the consideration of kT/C noise, propagation delay and power. 5.5. Digital logic Fig. 11 shows the block diagram of the digital logic. It consists of a clock and data control block, MSB registers, LSB registers, T-B converter, state detect block and digital code registers. The SAR logic con-

Table 1 Simulated state-of-artwork comparator performance in 28 nm CMOS technology.

[28] [29] [30] [31] This work a

FOM =

IOV (μ) (mV)

IOV (𝜎 ) (mV)

Power (μW)

Leakage power (μW)

Propagation delay (ps)

Type

FOM ([32]) (fJ/conv)a

2.532 5.323 0.86 0.75 0.324

13.22 12.157 12.32 3.85 10.31

72 54 32 70 48

3.01 0.039 0.01 0.369 0.004

96 79 95 65 87

dynamic dynamic dynamic dynamic static

0.375 0.281 0.166 0.364 0.25

Power . 2N ×Fs

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Table 2 Bit patterns generated by the digital block for all 7 CDACs in first and second comparison cycle. CDACs

1

2

3

4

5

6

7

1st cycle 2nd cyclea

1111111000 xxxxxxx111

0111111000 xxxxxxx110

0011111000 xxxxxxx101

0001111000 xxxxxxx100

0000111000 xxxxxxx011

0000011000 xxxxxxx010

0000001000 xxxxxxx001

a

x is the bit being fed back from the comparator output.

Fig. 11. The block diagram of the digital logic.

trols the operation of the ADC. It is responsible for the clock generation for various blocks, viz. memory and switch control of the CDAC. The digital logic is a fully custom design. The trigger signals for the digital logic is an external CLK signal, acting as a start of conversion (SOC). The reference data bits are generated with respect to the control signal from the state detect block. Here, the MSB registers store the data at 1st cycle data ready from comparators. The LSB registers are level triggered by the 2nd cycle data ready signal from comparator. The output of the MSB and LSB registers are passed to their corresponding T-B converter. The 3-bit T-B converter is designed using multiplexers. The binary bits arrive at the digital code registers without violating the set up time and hold time. The end of conversion (EOC) signal from the state detect block stores the digital bits into the digital code registers.

Fig. 12. (a) The I/O characteristics for ADC with a ramp input of 4.88 MHz frequency, (b) Transient response of the ADC to a 4.88 MHz sine wave.

6. Simulation results and discussions The hybrid flash-SAR ADC is designed in a standard 28 nm CMOS technology and operates with a supply voltage of 0.9 V. The design is intended for a resolution of 6 bits. Hence, the value of LSB is determined as LSB = 0.9∕26 = 14.0625 mV. To verify the functionality of the designed ADC, the ADC has been tested with two different inputs; ramp and sinusoidal waves. Fig. 12 (a) shows the I/O Characteristics with a full-scale ramp input with the frequency of 4.88 MHz. The ADC shows offset error of 1 LSB without any missing codes. Fig. 12 (b) shows the response of the ADC to a sinusoidal input of 4.88 MHz. The ADC output is passed through an ideal 8-bit DAC to generate analog levels. The plot shows the digitized sine wave. Fig. 13 shows the integral nonlinearity (INL) and differential nonlinearity (DNL) of the complete design. By normalising the difference with the ideal code width, the DNL at a code is calculated by taking the difference between the ideal code width with the code width obtained from the I/O characteristics. The INL is calculated as the running sum of the DNL values [3,4]. The DNL for the ADC is +0.47/-0.38 LSB.

Fig. 13. INL/DNL plots for the designed ADC.

The DNL is in agreement with the input-output characteristic and shows no missing codes. The plot shows an INL of +1.10/-0.75 LSB. Larger value of INL is observed after digital code 40 because of the capacitance mismatch due to the bridge capacitor, implemented using metal-oxide-metal (MOM) structure. This effect is seen when the switching between maximum values of capacitors occur. The 1024-point FFT for 96 MHz sinusoidal input is shown in Fig. 14. The SNR is 35.56 dB from the plot, which results in an ENOB of 5.61 bits. The FFT also shows a spurious free dynamic range (SFDR) of 40.81 dB. 7

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Fig. 14. 1024-point FFT for a sinusoidal signal with 96 MHz of frequency.

Fig. 17. The SNR variation plot with respect to varying process and temperature corners for FS of 1 GS/s.

Fig. 15. Variation of the SNR with input signal amplitude for a 1 MHz sinusoid.

Fig. 15 shows the variation of SNR with the input signal amplitude for a 100 MHz input. The curve has 1 dB/dB of slope. The plot shows the dynamic range (DR) of 34.32 dB. The variation of signal-to-noise-and-distortion ratio (SNDR) with input signal frequency is shown in Fig. 16. The SNDR drops by 3 dB from the peak value of 35.56 dB at 300 MHz. Hence, 300 MHz can be treated as the effective-resolution bandwidth (ERBW) for the proposed ADC. The variations of SNR for different process corners (slow nMOS slow pMOS(SS), fast nMOS fast pMOS (FF) and typical nMOS typical pMOS(TT) corner) and temperature (−20 ◦ C to 80 ◦ C) are shown in Fig. 17. The plot shows the maximum SNR of 35.72 dB at FF corner with 27 ◦ C and minimum SNR of 31.96 dB at SS corner with −20 ◦ C.The cross corner simulations exhibit 5.04 bits of ENOB at the worst case corner. Thus, the design shows an allowable deviation for the budgeted SNR. The pie-chart in Fig. 18 shows the power consumption of various sub-blocks of the ADC. The total power consumption is 2.33 mW. Switching of the capacitors in the CDAC leads to higher power consumption in the CDAC array which is seen in the pie-chart as a dominant power consuming block.

Fig. 18. Power consumption of various sub-blocks of the ADC.

Unlike the dynamic comparators, the inverter based comparator array including the biasing circuitry consumes only 250 μW of power. Further, the digital logic circuitry consumes 550 μW of power. The eye diagram of the MSB output bit with a pseudo-random bit sequence (PRBS) of 10 ns bit period, is shown in Fig. 19. The plot shows total jitter of 62.42 ps, resulting in 6.24% of the bit-period. Table 3 compares the proposed ADC with the state-of-the-artworks. The design has been compared with the recently reported results for a similar ENOBs. The designed ADC shows an FOM of 47.7 fJ/conversion. The design takes two conversion cycles to have the digital output bits. Comparing the state-of-the-artworks for SAR ADC alone, the designed ADC shows 1.34X, 1.85X, and 3X performance in terms of FOM, while comparing with [33,35,38] respectively. The designed ADC also exhibits 1.63X and 3.98X FOM improvement, for the case of pipeline [36] and flash [37] ADCs, respectively. Considering the case of hybrid ADC, the proposed design shows 3.96X and 10X of improvement for the case of 3 b/cy SAR [34] and

Fig. 16. Variation of SNDR with input signal frequency.

Fig. 19. Eye diagram of the MSB with PRBS of 10 ns bit period. 8

D.K. B et al.

Microelectronics Journal 95 (2020) 104666

Table 3 Comparison with the state-of-the-artworks.

[10] b [25] c [33] b [34] c [35] b [36] c [37] c [38] c [39] c Proposed workb Power 2ENOB ×Fs

Tech. (nm)

VDD (V)

Architecture

ENOB (Bits)

Fs (GHz)

SFDR (dB)

SNDR (dB)

Power (mW)

Conv. Cycles

FOM (fJ/conv)a

65 180 40 65 55 65 180 65 180 28

– 1.8 1.1 1 1.2 1.2 1.8 1.2 1.8 0.9

2 b/cy SAR SAR SAR 3 b/cy SAR SAR Pipeline Flash SAR SAR 3 b/cy SAR

5.9 10.85 5.29 4.69 5.6 5.63 3.6 5.72 9.32 5.61

0.32 0.01 0.7 0.37 1.6 1.5 0.40 0.55 0.002 1

48.52 75.8 – 41.95 52 – 26.5 47.97 68.9 40.81

37.20 66.9 31.5 28.52 35.4 35.8 23 36.21 57.7 35.56

9.81 0.82 3.1 1.84 5 5.8 0.95 3.12 0.009 2.33

4 12 6 3 6 6 1 6 10 3

479 44.2 144 189.2 64 78 190 88.6 7.5 47.7

a

FOM =

b

Simulation results. Measurement results (including the input signal buffers, clock buffers and output drivers).

c

.

tion (formerly Media Lab Asia) for supporting this R & D work through Young Faculty Research Fellowship (YFRF).

Table 4 Performance summary. Parameter

Value

Technology VDD Architecture ERBW DNL INL DR (@1 MHz) Power Total Jitter

28 nm CMOS 0.9 V 3-bit per cycle SAR 300 MHz +0.47/-0.38 LSB +1.10/-0.75 LSB 34.32 dB 2.33 mW 6.24% of the bit-period

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2 b/cy SAR [10] ADCs, respectively. The improvement is achieved because of the low power inverter based comparator. Refs. [25,39] show better performance at relatively low speed applications, because of which the reported ADCs consume lower power and exhibit better FOM. Moreover, the proposed ADC consumes only 3 cycles for the endof-conversion, whereas [25,39] require 10 and 12 conversion cycles, respectively. The conversion time of the proposed architecture is significantly lower comparing to the regular SAR ADC. For the completeness, the performance summary of the designed ADC in terms of INL, DNL, ERBW, DR, and total Jitter has been shown in Table 4. In summary, the ADC achieves all the budget specifications. 7. Conclusion The proposed design improves the conversion speed by using hybrid architecture, and power consumption by utilizing an inverter based comparator. The ADC does not use any background offset calibration or digital error correction. The design uses segmented-split capacitor array CDAC to save area and achieve fast settling time. Also, an inverter based comparator provides with very good performance at high frequencies with lower power consumption. The hybrid flash-SAR architecture can provide overall better performance at the sampling rates in excess of GHz. The design can be further used for high speed and medium resolution applications viz. RF receivers, DSP serial links, Sensors. Declaration of competing interest None. Acknowledgement The authors would like to thank Ministry of Electronics and Information Technology (MeitY), Government of India for providing EDA/CAD tools for this work under SMDP-C2SD project and Digital India Corpora-

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