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Behavioral model of a 1.8 V 6B CMOS flash ADC based on device parameters
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Engineering Information Abstracts (Part II)
cal package, the design cycle time is reduced considerably. ŽAuthor abstract . 10 Refs. In English EI Order Number: EIP97093817970 Keywords: Analog to digital conversion; Computer simulation; Pipeline processing systems; User interfaces; Error correction; Algorithms; Mathematical models; Computer architecture; Computer software Title: BEHAVIORAL MODEL OF A 1.8 V 6B CMOS FLASH ADC BASED ON DEVICE PARAMETERS Author(s): Pennell, M.J.; Hasan, M.; Allee, D.R.; Xie, W. Corporate Source: Motorola SPS, Tempe, AZ, USA Conference Title: Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS’97. Part 3 Žof 4. Conference Location: Hong Kong, Hong Kong Conference Date: 19970609-19970612 Source: Computer-Aided Design VLSI Proceedings - IEEE International Symposium on Circuits and Systems v 3 1997. IEEE, Piscataway, NJ, USA,97CH35987. p 1636-1639 CODEN: PICSDI ISSN: 0271-4310 Publication Year: 1997 Abstract: A hierarchical behavioral model of a submicron 6 bit CMOS flash analog to digital converter is presented. Circuit parameters are extracted from process dependent device data using an extension of the grrmrIrrD methodology for use in the behavioral model. In using this approach, the model will track changes in physical device geometries without the need for re-characterization. The comparator model is validated against SPICE and system level simulation results are presented for the full converter. ŽAuthor abstract . 4 Refs. In English EI Order Number: EIP97093817974 Keywords: Analog to digital conversion; CMOS integrated circuits; Comparator circuits; Computer simulation; Computer aided network analysis; Electric network parameters Title: COUNTING SFQ ANALOG TO DIGITAL CONVERTER RESULTS Author(s): Sandell, R.D.; Durand, D.J.; Dalrymple, B.J.; Pham, T. Corporate Source: TRW, Redondo Beach, CA, USA Conference Title: Proceedings of the 1996 Applied Superconductivity Conference. Part 3 Žof 3. Conference Location: Pittsburgh, PA, USA Conference Date: 19960825-19960830 Source: IEEE Transactions on Applied Superconductivity v 7 n 2 pt 3 June 1997. p 3298-3300 CODEN: ITASE9 ISSN: 1051-8223 Publication Year: 1997 Abstract: We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout ŽDRO.. The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate ŽSRG. at the carry out of the counter, we have measured the bit error rates ŽBER. of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit
counters connected to the two quantizer outputs were compared. We measured a BER of approximately 5 multiplied by 10minus with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG. ŽAuthor abstract. In English EI Order Number: EIP97073748555 Keywords: Analog to digital conversion; Flip flop circuits; Buffer circuits; Josephson junction devices; Gates Žtransistor .; Bit error rate; SQUIDs Title: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A BROAD-BAND DIGITAL HARMONIC VECTOR VOLTMETER Author(s): Mirri, Domenico; Pasini, Gaetano; Peretto, Lorenzo; Filicori, Fabio; Iuculano, Gaetano; Dolfi, Andrea Corporate Source: Facolta di Ingegneria, Bologna, Italy Conference Title: Proceedings of the 1997 IEEE Instrumentation & Measurement Technology Conference, IMTC. Part 2 Žof 2. Conference Location: Ottawa, Can Conference Date: 19970519-19970521 Source: Conference Record - IEEE Instrumentation and Measurement Technology Conference v 2 1997. IEEE, Piscataway, NJ, USA,97CH36022. p 1495-1499 CODEN: CRIIE7 Publication Year: 1997 Abstract: A broad-band digital harmonic vector voltmeter previously proposed and theoretically studied by the authors was implemented by using a special-purpose random sampling strategy to avoid the bandwidth limitations due to the finite conversion time of the SrH-ADC devices. The experimental results showed that the bandwidth of the instrument is limited only by that of the SrH devices of the acquisition channels, according to the theoretical findings. The maximum amplitude error was not greater than 2%. ŽAuthor abstract . 5 Refs. In English EI Order Number: EIP97073730957 Keywords: Digital voltmeters; Instrument errors; Analog to digital conversion; Bandwidth; Vectors Title: FAULT AND DIAGNOSIS ON A SUCCESSIVE APPROXIMATION ADC Author(s): Marc, Francois; Dallet, Dominique; Danto, Yves Corporate Source: Universite Bordeaux I, Talence, Fr Conference Title: Proceedings of the 1997 IEEE Instrumentation & Measurement Technology Conference, IMTC. Part 2 Žof 2. Conference Location: Ottawa, Can Conference Date: 19970519-19970521 Source: Conference Record - IEEE Instrumentation and Measurement Technology Conference v 2 1997. IEEE, Piscataway, NJ, USA,97CH36022. p 1460-1463 CODEN: CRIIE7 Publication Year: 1997 Abstract: In successive approximation ArD converters, the origin of failure is located through the bit error which is computed from the histogram, if it fulfil some conditions. In this paper, we present the real case of a failing ArD converter whose bit error is not computable. Consequently, the failure localization is performed using an alternative methodology including external electrical characterization and electron beam testing ŽEBT.. ŽAuthor abstract . 5 Refs. In English EI Order Number: EIP97073730950 Keywords: Analog to digital conversion; Approximation theory; Electron beams; Failure analysis
Engineering Information Abstracts (Part II)
cal package, the design cycle time is reduced considerably. ŽAuthor abstract . 10 Refs. In English EI Order Number: EIP97093817970 Keywords: Analog to digital conversion; Computer simulation; Pipeline processing systems; User interfaces; Error correction; Algorithms; Mathematical models; Computer architecture; Computer software Title: BEHAVIORAL MODEL OF A 1.8 V 6B CMOS FLASH ADC BASED ON DEVICE PARAMETERS Author(s): Pennell, M.J.; Hasan, M.; Allee, D.R.; Xie, W. Corporate Source: Motorola SPS, Tempe, AZ, USA Conference Title: Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS’97. Part 3 Žof 4. Conference Location: Hong Kong, Hong Kong Conference Date: 19970609-19970612 Source: Computer-Aided Design VLSI Proceedings - IEEE International Symposium on Circuits and Systems v 3 1997. IEEE, Piscataway, NJ, USA,97CH35987. p 1636-1639 CODEN: PICSDI ISSN: 0271-4310 Publication Year: 1997 Abstract: A hierarchical behavioral model of a submicron 6 bit CMOS flash analog to digital converter is presented. Circuit parameters are extracted from process dependent device data using an extension of the grrmrIrrD methodology for use in the behavioral model. In using this approach, the model will track changes in physical device geometries without the need for re-characterization. The comparator model is validated against SPICE and system level simulation results are presented for the full converter. ŽAuthor abstract . 4 Refs. In English EI Order Number: EIP97093817974 Keywords: Analog to digital conversion; CMOS integrated circuits; Comparator circuits; Computer simulation; Computer aided network analysis; Electric network parameters Title: COUNTING SFQ ANALOG TO DIGITAL CONVERTER RESULTS Author(s): Sandell, R.D.; Durand, D.J.; Dalrymple, B.J.; Pham, T. Corporate Source: TRW, Redondo Beach, CA, USA Conference Title: Proceedings of the 1996 Applied Superconductivity Conference. Part 3 Žof 3. Conference Location: Pittsburgh, PA, USA Conference Date: 19960825-19960830 Source: IEEE Transactions on Applied Superconductivity v 7 n 2 pt 3 June 1997. p 3298-3300 CODEN: ITASE9 ISSN: 1051-8223 Publication Year: 1997 Abstract: We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout ŽDRO.. The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate ŽSRG. at the carry out of the counter, we have measured the bit error rates ŽBER. of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit
counters connected to the two quantizer outputs were compared. We measured a BER of approximately 5 multiplied by 10minus with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG. ŽAuthor abstract. In English EI Order Number: EIP97073748555 Keywords: Analog to digital conversion; Flip flop circuits; Buffer circuits; Josephson junction devices; Gates Žtransistor .; Bit error rate; SQUIDs Title: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A BROAD-BAND DIGITAL HARMONIC VECTOR VOLTMETER Author(s): Mirri, Domenico; Pasini, Gaetano; Peretto, Lorenzo; Filicori, Fabio; Iuculano, Gaetano; Dolfi, Andrea Corporate Source: Facolta di Ingegneria, Bologna, Italy Conference Title: Proceedings of the 1997 IEEE Instrumentation & Measurement Technology Conference, IMTC. Part 2 Žof 2. Conference Location: Ottawa, Can Conference Date: 19970519-19970521 Source: Conference Record - IEEE Instrumentation and Measurement Technology Conference v 2 1997. IEEE, Piscataway, NJ, USA,97CH36022. p 1495-1499 CODEN: CRIIE7 Publication Year: 1997 Abstract: A broad-band digital harmonic vector voltmeter previously proposed and theoretically studied by the authors was implemented by using a special-purpose random sampling strategy to avoid the bandwidth limitations due to the finite conversion time of the SrH-ADC devices. The experimental results showed that the bandwidth of the instrument is limited only by that of the SrH devices of the acquisition channels, according to the theoretical findings. The maximum amplitude error was not greater than 2%. ŽAuthor abstract . 5 Refs. In English EI Order Number: EIP97073730957 Keywords: Digital voltmeters; Instrument errors; Analog to digital conversion; Bandwidth; Vectors Title: FAULT AND DIAGNOSIS ON A SUCCESSIVE APPROXIMATION ADC Author(s): Marc, Francois; Dallet, Dominique; Danto, Yves Corporate Source: Universite Bordeaux I, Talence, Fr Conference Title: Proceedings of the 1997 IEEE Instrumentation & Measurement Technology Conference, IMTC. Part 2 Žof 2. Conference Location: Ottawa, Can Conference Date: 19970519-19970521 Source: Conference Record - IEEE Instrumentation and Measurement Technology Conference v 2 1997. IEEE, Piscataway, NJ, USA,97CH36022. p 1460-1463 CODEN: CRIIE7 Publication Year: 1997 Abstract: In successive approximation ArD converters, the origin of failure is located through the bit error which is computed from the histogram, if it fulfil some conditions. In this paper, we present the real case of a failing ArD converter whose bit error is not computable. Consequently, the failure localization is performed using an alternative methodology including external electrical characterization and electron beam testing ŽEBT.. ŽAuthor abstract . 5 Refs. In English EI Order Number: EIP97073730950 Keywords: Analog to digital conversion; Approximation theory; Electron beams; Failure analysis