Determination of combinational logic circuit reliability through generation of fault diagnosis tests

Microelectron. Reliab., Vol. 28, No. 4, pp. 541-545, 1988. Printed in Great Britain.

0026-2714/8853.00 + .00 © 1988 Pergamon Press pie

DETERMINATION OF COMBINATIONAL LOGIC RELIABILITY THROUGH GENERATION OF FAULT TESTS

CIRCUIT DIAGNOSIS

S. P. DOKOUZGIANNISand J. M. KONTOLEON Department of Electrical Engineering, University of Thessaloniki, 540 06 Thessaloniki. Greece

(Receivedfor publication 26 November 1987) Abstract--This paper investigates the relationships between a given set of excitation vectors and the test sets for faults occuring in combinational circuits, in order to obtain new conditions for determining the redundant cubes of terminal states. The analysis presented is concluded with two new algorithms for the evaluation of combinational logic circuit reliability.

1. I N T R O D U C T I O N

vectors. In contrast, this n u m b e r of tests is comparable with the set of 'don't care' excitation vectors assumed for the considered circuits. Finally, it is noted that the analysis pesented throughout this paper is valid for any combinational circuit fault model, e.g. line, gate terminal and bridging

In recent work [1, 2] the reliability of combinational logic circuits, with regard to the given excitation vectors, is efficiently determined by enumerating and examining cubes of terminal states. The enumeration of such cubes does not present any difficulty and can faults. be easily performed for circuits of any size, In contrast, the examination of these cubes is very time consuming, since no efficient method is known for the fast comparison of large sets which have the form of overlapping binary cubes. The purpose of this paper is to provide new methods, which employ fault diagnosis X,R, Rw logic testing for the identification of the logic redundancy, represented by cubes of terminal states. r, r',e,{ r'} For more than two decades the logic testing of digital systems has been an everyday practice for most design and production stages. Through the years a ~4rr,./V.r, n u m b e r of techniques have been evolved in order to make the testing fast and cheap [3-5]. Important among these techniques is the generation of tests for X, {X} combinational circuits. For a given circuit fault a test O 1 (if it exists) is known as a certain excitation vector for Wg, W~ which the logical value on at least one circuit output is not correct. W, W°, W ~ This paper shows that the test sets are sufficient for the redundancy identification of a terminal state cube and that the set of 'don't care' excitation vectors is equally competent for this purpose as the set of ~, g,o, lg,1 the given excitation vectors. Thus, the relationships among test sets, the set of given excitation vectors and the set of the 'don't care' excitation vectors are first investigated for a cube, in order to provide new and o Wr,, Wr,1 efficient conditions equivalent to theorem 1 in [1]. According to these conditions two alternating algoT°:'(T~:°) rithms are presented, which give the exact value of reliability for combinational logic circuits. Two motives substantiate the application of test vectors for identifying redundant fault masking cubes. The first is that the average number of tests is exAB tremely low with respect to the exhaustive set of input 541

2. NOTATION

combinational logic circuit, probability that Y is fault free and the reliability of ~,, respectively terminal state vector of ~ cube of terminal state vectors Y, Y ¢ Y', and its probability, respectively the circuit ~ , when states of its gate terminals form the vector Y and when these states form any of the vectors in the cube Y' input excitation vector of ~" and ensemble forX subsets of {X} for which the fault free circuit .A:provides the logic 0 and 1 on its output,

w°+w) = {x} set of given input vectors X for JV and its subsets corresponding to the logic 0 and 1 on the output of the fault free circuit, W° + w I = W~_ {X}, W°~_ W°,

Wt =_W~. set of 'don't care' input vectors for Wand its subsets corresponding to the logic 0 and 1 on the output of the fault free circuit,

g¢o+ ~+, = ~, ~¢+w = {x} subsets of {X} for which +f'y, takes the logic 0 and 1 on its output, W°, + W~, = {X} set of vectors X, X ~ {X}, for which the faultfree circuit +V'provides the logic 0(l) on its output and the faulty circuit +V"r, the logic 1(0) on the same output (this is known as a set of test vectors for X r, [6]) --A c~B, notation meaning the intersection of the sets A and B

542

S.P. DOKOUZGIANNISand J. M. KONTOLEON ,A"

,./.'y

. t,,

--T

/

v•o

~o

I

Wo

¢v° w',\

-

i

/

\x

/

F

T,~.,°

I

,/

--¢v

(a)

(b)

¥'

___ W I w o \ , \

W~

W¢,------k,

v °

W o W,,,//

Wo

Wo

/

/

w°

(c)

Fig. l. A sample of excitation and test tables for combinational logic circuits. (a) The presumed layout of the sets if-o, W o, W t and fit. (b) Distribution of vectors of W~, and W:~, for a causal cube Y'. (c) The resulting test table.

Thus,

Nomenclature

Redundant cube Y' of terminal states a cube Y' of terminal states, which for a given W ° and W ~ satisfies theorem 1 in [1] Test test vector for a faulty circuit ,,~'; which for a given Y' is a binary cube which is an element of either TO:~ or T~:°. 3. BASIC E Q U A T I O N S F O R T E S T SETS O F COMBINATIONAL CIRCUITS

TO: t = W °. W~,

(la)

T~ :° = W~-Wr°,.

(lb)

and

In the known testing algorithms [ 3 - 5 ] the test sets T°: l and T~,;° are determined directly from the logic diagram of J V a n d not as the intersections of the sets W.0-, W,~, W °, and W~,,. Moreover, these algorithms ignore the given set W, W c {X}. When dealing with the reliability of ~,, however, the set W is presumed for a circuit and it must be taken into account, even if w

=

{x}.

A convenient way to describe the set W is through the set I~, because the number of elements in 17V is usually extremely low with respect to those of W.

(2a}

W~. = W ~+ 17V1,

(2b)

and

since according to the assumed notation W + ITv= {X}. By substituting equations (2) in equations (I) the test sets are T0,,l

It is already an established practice to demonstrate the problems of combinational circuit logic testing on single output circuits. A test vector for such circuits is, for a given Y (i.e. for a single/multiple fault of stuck-at type), a binary input cube for which the faulty circuit JV"r produces an incorrect logical value on its output [6]. According to the analysis presented in [1], test vectors are the same for all vectors Y which are covered by a cube Y', due to the functional equivalence among terminal state vectors included in such a cube. Therefore, for any cube Y' of A~

W ° = W ° + ITv°

1 = W o W rl , + W~ o W r,

(3a)

T~: ° = W t W ° , + ffV~W°,.

(3b)

and

In order to be aware of how interrelated these sets are, consider the sample excitation table for ,f~shown in Fig. l(a), where input vectors are merged in such a way to form isolated sets 171/°, W °, W ~ and 17VL A causal cube Y' in such a table defines the rows of W °, and W~,; this is schematically illustrated in Fig. l(b). In this way the excitation table for ,47, can be obtained, which has the same distribution of input vectors as that of Fig. l(a). The intersection of the above tables, i.e. for .A'~ and .A'],, in accordance with equations (3) results in the so called test table [Fig. l(c)]. It is an important feature of this table that the tests of T°r: 1 (Tlr:°) can only be found in the area ° ~W.tv, ~ ~ despite the fact that occupied by vectors W,~~ the vectors W °, and W~, can be scattered anywhere throughout the excitation table of L.~'],,. If Y' is a redundant cube o f , V t h e n W ° _~ W °, and W I ~ W~, (see theorem 1 in [1]). In such a case W ° W ~ , = ~ and W 1W °, = ~ , since W°and W 1 are subsets of W °, and W~,,, respectively, and W °, W~, = for any Y'. Thus, for redundant cubes Y' of ,.~ equations (3) are further simplified to obtain the forms T°v: 1 = 17V°W~,

(4a)

Combinational logic circuit reliability

543

To~*

~o

Fig. 3. Logic circuit example for demonstrating the determination of redundant cubes.

Proof. According to equations (4), which correspond to test sets for redundant cubes in Y,, T°:tW °= W°W~,W °

Fig. 2. Illustration of the distribution of tests inside the test table for redundant cubes of Y' of

and T~', o = Wl WO,.

(4b)

Figure 2 illustrates the situation represented by equations (4), by enlarging fragments of the test table of Fig. l(c).

4. DETERMINATION OF THE RELIABILITY BY

INTERSECTING TESTS WITH THE AVAILABLE EXCITATION VECTORS Due to the extremely large number of possible faults (single/multiple), the evaluation of combinational circuit reliability resorts to the enumeration of cubes of terminal states [1]. This enumeration can be performed for circuits of any size and structure [2]. The enumerated cubes are further examined, in accordance with theorem 1 in [1], in order to determine the probability of fault masking in Y r e d u n d a n t cubes. It has been observed however, that comparison of the sets W ° with W °, and W 1 with W 1, is generally more memory/time consuming than the formation of a cube Y'. The cause of this lies in the size and form of these sets, which are large as well as overlapping binary cubes; note also that for any Y': W °, + W~,, = {X}. In contrast to the sets W°r, and WI,, the average sizes of the sets TO; 1 and Tlr:o are very small and their appropriate utilization simplifies the above mentioned examination of enumerated cubes. Consider for this purpose the following theorem.

and

T~:°W 1 = W l W ° , W 1,

Since lTv°w ° = ~ and f f l W l =/Z/(see notation) the intersections under consideration are empty for any redundant cube Y'. The application of this theorem will be demonstrated using the following example. Suppose that the set of input vectors W, W = {(x1x2x3x4)} = { ( 0 0 0 0 ) , (0001), (0010), (0100), (0110),(1010),(1011),(1100),(1101) (1110),(1111)}, is processed by the circuit JV of Fig. 3 and that the currently enumerated cube Y' for JV'is (nnn nnn - - 0 nnn) (see Fig. 9 in [2], where gate terminal faults are considered). A testing program for the s-a-0 fault in the 9th gate terminal in JVgenerates the following test sets: T°: 1 = ~ (there is no test in this set) and T~;°= {(0-11),(0101)}. By intersecting these with the sets W ° and W ~, which are, respectively, {(000-), (0-10), (01-0)} and {(1-1-), (11--)}, the result T % I W ° = iZ and T r l : ° W l = ~ is obtained (note that the intersection of two binary cubes is empty if one includes 0 and the other 1 in the same position [3, 63). Therefore, according to Theorem 1, the above given cube Y' is redundant in ~ In contrast, when the same result is obtained in accordance with theorem 1 in [1], the sets W ° and W ~ are compared with their counterparts W °, and W~,. However, the sets Wr°, = {(100-),(010-),(001-),(011-),(000-)} and WrL = {(101-),(110-),(111-)} (see again fig. 9 in [21) are much larger than TO: ~ and T~; °. In addition, it is easier to intersect the set W°(W l) with T°:I(T~: °) than to investigate its inclusion in W°,(W~,). These differences can also be seen in Table 1, where the excitation and test tables summarize the obtained results. Note that for the cube Y' under consideration W ° ~ W ° , a n d w 1 = W~,.

Corollaries. (C1) If W ~ = ~ , ~ = 0, l, then the relation TrY,~ W ~ = ~ is valid for any T~,',~. (C2) If T~,~ = / Z , 7 = 0 , 1 , then the relation T~', W = ~ is valid for any W ~. (C3) If W ~ = W ~ , co= 0,1, then the relation T~,',~W~ = IZ/requires that T~',~ = tZ/.

Theorem 1. A cube Y' is redundant in JV'if and only if

T°;1W°= ~

and

T~:°W l = ~ .

The above application of Theorem 1 results in the algorithm REL1 presented below, which provides the exact reliability for

544

S. P. DOKOUZGIANNIS and J. M. KONTOLEON

Table 1. Excitation and test tables for a cube Y' - (nnn nnn - ~ ,;~,ofFig. 3

Algorithm REL1 Step 0. Set R~ = R. Split W into W ° and W ~. Step 1. Form a new cube Y', Y' ~ (an... n), for Jff; if it does not exist then go to step 6. Step 2. I f W ° = ~ then go to step 4. Step 3. F o r m a new test t for Jffr' which belongs in TO; a; if it does not exist then go to step 4. If W ° = W~- then go to step 1. If t n W ° = ~ then return to the beginning of this step else go to step 1. Step 4. Repeat exactly steps 2 and 3 using W ~, T~r:°, W~ and step 5, instead of W °, T°: l, W ° and step 4. Step 5. Set R~ = R~+ Pr{Y'} and go to step 1. Step 6. Stop; R~ equals the exact reliability value for

5. DETERMINATION OF THE RELIABILITY BY COMPARING TEST SETS WITH THE 'DON'T CARE' INPUT VECTORS

Another, alternating condition for determining red u n d a n t cubes Y' is through comparison of the sets TO: ~ with ITv° and Tlr:° with 17V1. In this case the following theorem is valid.

Theorem 2. A cube Y' is redundant in Jffif and only if TO: ~ ~ I711°

Proof.

and

T~,'°___ ITv~.

In order to prove that T~1_~ 1~ ° and T~',o _ 17Va when Y' is a redundant cube of ~4/ is is sufficient to show that TO: ~ 17g° = T°: ~and T~: o f f l = T~: °. Note that if an intersection AB for any two sets A and B is equal to one of these sets, e.g. to A, then

nnn} in

A _ B. According to equations (4), the intersections TO: 117goand T~',o 17V1are, respectively, I7V°W~,,ITV°

and

lTvtw°,ff 1.

It is evident that these equal the sets T°:t and T~: ° obtained in equations (4).

Corollaries. (C4) If 17V~= W3-, ct = 0,1, then the relation T~,',i ~ ff'~ is valid for any T~, ~. (C5) If T~,',~= ~ , ~ = 0 , 1 , then the relation T},,~ ___ W ~ is valid for any 17[/~. (C6) If ITv~ = ~ , ct = 0, 1, then the relation T~;,~ c !~ ~ requires that T} ,~ = ~ . According to Theorem 2, it is possible to modify the starting point for the combinational circuit reliability evaluation/analysis problem. That is, instead of the set W,, which is generally a large one, the set f f is now employed, which usually is of small size (note that very frequently ITV= ~ ) . Thus, for the previously presented example the reliability evaluation problem can be solved by considering the set of 'don't care' input vectors lTg = {(0011),(0101),(0111),(1000),(1001)}. For the already examined cube Y' (Section 4) T°: 1 = and Tlr:° = ITv1 (see also Table 1). Following the above reasoning, an alternative reliability evaluation algorithm REL2 is presented.

Alyorithm REL2 Step0. Set R w = R. If 17V= ~ then go to step 1 else split ITV into lTv° and if,1. Step 1. Form a new cube Y', Y' 4: (nn... n), for JV'; if it does not exist then go to step 6. Step 2. If 17V° = W° then go to step 4.

Combinational logic circuit reliability Step 3. F o r m a new test t for JVr, which belongs in TO: 1; if it does not exist then go to step 4. If ff¢ = ~ or I7¢o = ~ then go to step 1. If t g ~ o then go to step 1 else return to the beginning of this step. Step 4. Repeat exactly steps 2 and 3 using I7V1 W ~ , T~,'° and step 5, mstead of W °, W °-, T°: 1 and step 4. Step 5. Set Rw = R w + P r { Y ' } and go to step 1. Step 6. Stop; Rw equals the exact reliability value for X 6. C O N C L U S I O N S

Two efficient conditions have been presented for identifying redundant cubes of terminal states in combinational logic circuits. Through generation of tests for a given fault cube, these conditions avoid the excessively memory/time consuming comparisons among large sets consisting of overlapping binary cubes.

545

It is hoped that further investigation will provide more light into the complexity of reliability evaluation with regard to the complexity of digital circuit testing algorithms.

REFERENCES

1. S. P. Dokouzgiannis and J. M. Kontoleon, A cubical logic circuit modelling for reliability studies, Microelectron. Reliab. 27, 823-831 (1987). 2. S. P. Dokouzgiannis and J. M. Kontoleon, Recursive enumeration of state graphs for the reliability evaluation of logic circuits, Microelectron. Reliab. 28, 101- I 17 (1988). 3. J. P. Roth, Diagnosis of automata failures: a calculus and a method, I B M J. Res. Dev. 10, 278-291 (1966). 4. H. Fujiwara and T. Shimono, On the acceleration of test generation algorithms, IEEE Trans. Comput. C-32, 1137-1144(1983). 5. V. K. Agarwal and A. S. F. Fung, Multiple fault testing of large circuits by single fault test sets, IEEE Trans. Circuits Syst. CAS-28, 1059-1069 (1981). 6. H. Y. Chang, E. G. Manning and G. Metze, Fault Diagnosis of Digital Systems. Wiley, New York (1970).