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Development of a coated wire bonding technology
1206
World Abstracts on Microelectronics and Reliability
Effects of tip clearance and fin density on the performance of heat sinks for VLSI packages. KEI S. LAU and RooP L. MAHAJAN. IEEE Trans. Compon. Hybrids mfg Technol. 12(4), 757 (1989). Motivated by the high heat dissipation requirements of the advanced VLSI packages (AVP), experiments were performed with several heat sinks to study their heat transfer characteristics. The thermal resistances and pressure drops of the heat sinks were measured for fin densities of 1.3, 4.6, 5.6 fins/cm and tip clearance varying from 0 to 2 cm. The mass flow rate varied from 0.01 to 0.1 kg/s. For a fixed mass flow rate and zero tip clearance, the 1.3-fins/cm heat sink dissipated four times more heat than a heat sink without fins, and the 5.6-fins/cm heat sink dissipated seven times more. Accompanying this increased heat transfer, however, is an increase in pressure drop. With an increase in tip clearance, the pressure drop penalty is reduced but the heat transfer gain is also lower. This information is presented for different fin densities and tip clearances and should be useful to packaging engineers for the optimal design of high-density finned heat sinks. The effects of ultrasonic cleaning on device degradation. B. P. RICHARDS, P. BURTON and P. K. FOOTNER. Circuit l'Vld 16(3), 20 (1990). An investigation of the use of ultrasonic agitation for cleaning printed circuit boards using CFCbased solvents has shown that, under the standard conditions required to produce clean assemblies, no damage will occur to the components studied. Damage can only be induced by use of anomalously longer times or higher power densities. In all cases in which damage has been induced, it is of a purely mechanical nature due to fatigue, and is located on the device bond-wires and/or the package legs. Cleaning using CFC-based solvents under standard ultrasonic conditions of power density and time etc. is readily achieved within 2 minutes, even with a minimum stand-off height. A new multichip module using a copper polyimide multilayer snbstrate. SHINICHI SASAKI, TAICHI KON, TAKAAK10HSAKI and TOYOSHIYASUDA. IEEE Trans. Compon. Hybrids mfg Technol. 12(4), 658 (1989). A new multichip module using a multilayer substrate with a polyimide dielectric and a fine pattern of copper conductors is presented. This substrate contains small copper columnar vias which reduce the thermal resistance of polyimide layers without causing a channel accommodation decrease, and thin-film resistors for terminated transmission. This new module can densely mount high-speed LSI chips that produce twice as much heat as those in conventional modules. Furthermore, this module can transmit high-speed pulses at over 2 Gbits/s. High performance polymers for packaging and interconnections in micrnolectronics. J.-M. BUREAU,F. BERNARDand D. BROUSSOUX. Revue techn. Thomson-CSF 20-21(4), 689 (1989). As the geometries of modern electronic circuits are shrinking and as signal rate and complexity are increasing, the problem of interconnecting the active elements in a device is becoming more important. The area these interconnections cover, their transmission capacity, their fabrication yield and their sensitivity to electromagnetic interferences are factors limiting the performance of microelectronic systems. Both in monolithic and in hybrid circuits new interconnection systems must be developed. Multilevel electrical interconnections are now imperatively used for large integration density. It is also foreseen to replace, partly or totally, electrical interconnections by optical type interconnections for which speed and interference immunity are far
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , Gate arrays ride ASIC popularity to greater demand. JEE (Japan) 28 (January 1990). The market for gate arrays is
superior. In these two fields, multilevel interconnections and optical interconnections, heat resistant polymers and particularly polyimides play a very important role. In replacing or complementing traditional materials of microelectronics, they provide very interesting properties for the fabrication of interlevel insulating layers or integrated optical waveguides between chips or within a chip. The purpose of this paper is to review the chemistry and the properties of polyimides, the emergence of improved polymers as well as the state of the art in the technologies of packaging, of multilayer thin film interconnections and of integrated optical interconnections using organic materials. Development of a coated wire bonding technology. SUSUMU OKIKAWA, MICHIO TANIMOTO,HIROSHI WATANABE,HIROSHI MIKINO and TsuYoSHI KANEDA. IEEE Trans. Compon. Hybrids mfg Technol. 12(4), 603 (1989). As the number of functions on MOSLSIs increases, so does the number of its I/O pins. However, this pin increase has caused the wire bonding technology to become very complicated, leading to electric shorts between wires, wires and tab edges, wires and chip edges, and wires and leads. In addition, the length of the bonding wire has increased, resulting in various loop shapes as well as bent wires during resin molding. To solve these problems, the application of insulation coating films to the Au wire surfaces has been proposed. The insulation coating film developed here prevents short circuits, even if wires touch. This technology will be put into practical use in the near future. In addition, since this coating wire bonding makes far less critical bonding conditions, it facilitates the manufacture of multipin ASIC devices, which are expected to be widely used in the future. Comparative compliance of representative lead designs for surface-mounted components. ROBERTW. KOTLOWITZ. IEEE Trans. Compon. Hybrids mfg Technol. 12(4), 431 (1989). The long-term solder attachment reliability of leaded surfacemounted (SM) devices is controlled in part by the lead compliance. Lead stiffness characterization is then an essential feature of any program aimed at surface-mount solderjoint reliability evaluation. Structural models have been developed for common lead designs, including the straight J-lead, dimpled J-lead, gull-wing lead, butt-lead (l-lead), and S-bend lead configurations. Elastic strain energy methods were then applied to determine the effective flexural and torsional spring constants for each representative lead design. SM device solder attachment reliability assessment is typically accomplished through accelerated temperature, powdered, or mechanical cycling of test vehicles. Lead stiffness evaluation has been performed for different SM components tested using accelerated functional cycling and circuit-board dynamic bending. Comparative compliance data are provided for the chip carrier J-lead designs in the Phase A IEEE Compliant Lead Task Force mechanical cycling test program. The solder joint cycles-to-failure statistics indicate that significant differences in attachment fatigue performance can be correlated with disparate lead compliance between the tested SM components. The structural models and strain energy formulation presented provide a generalized method for quantifying the compliance of common lead configurations. The resultant spring constants represent mechanical properties of the particular lead design, and are independent of the SM package geometry and PCB interconnection details. The structural models provide a rational means to compare and rank order alternative lead designs based on overall directional compliance.
SYSTEMS
AND
EQUIPMENTS
expanding as ASIC applications for semi-custom ICs and LSIs increase. Although statistics are not available on the
World Abstracts on Microelectronics and Reliability
Effects of tip clearance and fin density on the performance of heat sinks for VLSI packages. KEI S. LAU and RooP L. MAHAJAN. IEEE Trans. Compon. Hybrids mfg Technol. 12(4), 757 (1989). Motivated by the high heat dissipation requirements of the advanced VLSI packages (AVP), experiments were performed with several heat sinks to study their heat transfer characteristics. The thermal resistances and pressure drops of the heat sinks were measured for fin densities of 1.3, 4.6, 5.6 fins/cm and tip clearance varying from 0 to 2 cm. The mass flow rate varied from 0.01 to 0.1 kg/s. For a fixed mass flow rate and zero tip clearance, the 1.3-fins/cm heat sink dissipated four times more heat than a heat sink without fins, and the 5.6-fins/cm heat sink dissipated seven times more. Accompanying this increased heat transfer, however, is an increase in pressure drop. With an increase in tip clearance, the pressure drop penalty is reduced but the heat transfer gain is also lower. This information is presented for different fin densities and tip clearances and should be useful to packaging engineers for the optimal design of high-density finned heat sinks. The effects of ultrasonic cleaning on device degradation. B. P. RICHARDS, P. BURTON and P. K. FOOTNER. Circuit l'Vld 16(3), 20 (1990). An investigation of the use of ultrasonic agitation for cleaning printed circuit boards using CFCbased solvents has shown that, under the standard conditions required to produce clean assemblies, no damage will occur to the components studied. Damage can only be induced by use of anomalously longer times or higher power densities. In all cases in which damage has been induced, it is of a purely mechanical nature due to fatigue, and is located on the device bond-wires and/or the package legs. Cleaning using CFC-based solvents under standard ultrasonic conditions of power density and time etc. is readily achieved within 2 minutes, even with a minimum stand-off height. A new multichip module using a copper polyimide multilayer snbstrate. SHINICHI SASAKI, TAICHI KON, TAKAAK10HSAKI and TOYOSHIYASUDA. IEEE Trans. Compon. Hybrids mfg Technol. 12(4), 658 (1989). A new multichip module using a multilayer substrate with a polyimide dielectric and a fine pattern of copper conductors is presented. This substrate contains small copper columnar vias which reduce the thermal resistance of polyimide layers without causing a channel accommodation decrease, and thin-film resistors for terminated transmission. This new module can densely mount high-speed LSI chips that produce twice as much heat as those in conventional modules. Furthermore, this module can transmit high-speed pulses at over 2 Gbits/s. High performance polymers for packaging and interconnections in micrnolectronics. J.-M. BUREAU,F. BERNARDand D. BROUSSOUX. Revue techn. Thomson-CSF 20-21(4), 689 (1989). As the geometries of modern electronic circuits are shrinking and as signal rate and complexity are increasing, the problem of interconnecting the active elements in a device is becoming more important. The area these interconnections cover, their transmission capacity, their fabrication yield and their sensitivity to electromagnetic interferences are factors limiting the performance of microelectronic systems. Both in monolithic and in hybrid circuits new interconnection systems must be developed. Multilevel electrical interconnections are now imperatively used for large integration density. It is also foreseen to replace, partly or totally, electrical interconnections by optical type interconnections for which speed and interference immunity are far
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , Gate arrays ride ASIC popularity to greater demand. JEE (Japan) 28 (January 1990). The market for gate arrays is
superior. In these two fields, multilevel interconnections and optical interconnections, heat resistant polymers and particularly polyimides play a very important role. In replacing or complementing traditional materials of microelectronics, they provide very interesting properties for the fabrication of interlevel insulating layers or integrated optical waveguides between chips or within a chip. The purpose of this paper is to review the chemistry and the properties of polyimides, the emergence of improved polymers as well as the state of the art in the technologies of packaging, of multilayer thin film interconnections and of integrated optical interconnections using organic materials. Development of a coated wire bonding technology. SUSUMU OKIKAWA, MICHIO TANIMOTO,HIROSHI WATANABE,HIROSHI MIKINO and TsuYoSHI KANEDA. IEEE Trans. Compon. Hybrids mfg Technol. 12(4), 603 (1989). As the number of functions on MOSLSIs increases, so does the number of its I/O pins. However, this pin increase has caused the wire bonding technology to become very complicated, leading to electric shorts between wires, wires and tab edges, wires and chip edges, and wires and leads. In addition, the length of the bonding wire has increased, resulting in various loop shapes as well as bent wires during resin molding. To solve these problems, the application of insulation coating films to the Au wire surfaces has been proposed. The insulation coating film developed here prevents short circuits, even if wires touch. This technology will be put into practical use in the near future. In addition, since this coating wire bonding makes far less critical bonding conditions, it facilitates the manufacture of multipin ASIC devices, which are expected to be widely used in the future. Comparative compliance of representative lead designs for surface-mounted components. ROBERTW. KOTLOWITZ. IEEE Trans. Compon. Hybrids mfg Technol. 12(4), 431 (1989). The long-term solder attachment reliability of leaded surfacemounted (SM) devices is controlled in part by the lead compliance. Lead stiffness characterization is then an essential feature of any program aimed at surface-mount solderjoint reliability evaluation. Structural models have been developed for common lead designs, including the straight J-lead, dimpled J-lead, gull-wing lead, butt-lead (l-lead), and S-bend lead configurations. Elastic strain energy methods were then applied to determine the effective flexural and torsional spring constants for each representative lead design. SM device solder attachment reliability assessment is typically accomplished through accelerated temperature, powdered, or mechanical cycling of test vehicles. Lead stiffness evaluation has been performed for different SM components tested using accelerated functional cycling and circuit-board dynamic bending. Comparative compliance data are provided for the chip carrier J-lead designs in the Phase A IEEE Compliant Lead Task Force mechanical cycling test program. The solder joint cycles-to-failure statistics indicate that significant differences in attachment fatigue performance can be correlated with disparate lead compliance between the tested SM components. The structural models and strain energy formulation presented provide a generalized method for quantifying the compliance of common lead configurations. The resultant spring constants represent mechanical properties of the particular lead design, and are independent of the SM package geometry and PCB interconnection details. The structural models provide a rational means to compare and rank order alternative lead designs based on overall directional compliance.
SYSTEMS
AND
EQUIPMENTS
expanding as ASIC applications for semi-custom ICs and LSIs increase. Although statistics are not available on the