- Email: [email protected]
Development of a technology independent library
Microproeessing and Microprogramming 39 (1993) 241-244 North-Holland
241
Development of a Technology Independent Library G. - P. E~.onomou, S. S. Nikolaidis, D. E. Metafas, C. E. Goutis VLSI Design Laboratory Department of Electrical Engineering University of Patras Greece
A technology-independentlibrarywhich is appropriatefor fast turn-around ASIC design is introduced. This library is based on a set of technology-independentLeafCells and a set of high-leveluser programmableModulesbuilt using them. Distinctdesign rules for developing the Modules have been adopted, from a set of manufacturers'most commondesign rules, thus resulting in the improvementof reliability and testability of designs. Using the set of Modules, the overall design time is reduced; furthermore, the structure of the library, enhances the aptitude of the designer to select a suitable IC manufacturerwhen most advantageous,independentlyof the progress of the design.
1.
Introduction
In the past years a steady increase has been evolved in customer demands for high performance, intense throughput, and signal/image processing modules which can be effectively used in ASICs design. The design and the development of a widely accepted Module Library to fulfil this purpose is the topic treated in this paper. Our purpose was the building of an efficient integrated CAD system on which to design, simulate, and develop an Integrated Circuit (IC) in the shortest time. By means of this library, named UPML_Iib, designers are supported with a manufacturers' common set of basic cells and a set of high performance user programmable modules [1]. These sets can be further used for fastturnaround ASIC design on the application fields that the designers would be interested in. In order to satisfy demands such as the feasibility of the design, the easiness of the implementation, the transferring quickness, the design environment compatibility factors, the reliability, and the testability of the design, a SemiCustom design approach, commonly used for ASIC designs, has been employed to accomplish this Library. Three individual Library levels, containing Low-, Medium- and High-level Cells, have been implemented to complete this task. Furthermore, various I/O pads are provided too. The central idea beyond the Library's set up is that it will act as an
intermediate level between logic-level designs and the great variety of manufacturers' real library cells to subsequently form the physical level designs. The UPML_Iib comes to help designers develop ICs on an environment - that is Manufacturers' Independent, - which offers a Common Design Basis, - supporting ASICs Design, - rich of Testability - Reliability conventions, - permissive of Fast turn-around design. lib's Development Process N~wadays, a lot of chip manufacturers offer many advantageous modes to implement a design and to keep on edge of technology in the competitive world of VLSI design and ASICs domain. Those ways, however, tend to be style-, technology-, design-, and manufacturer-dependent, inhibiting a designer to select from a variety of alternative choices after a design has been developed. As a matter of fact, a designer had first to choose a foundry and then to design. 2.1 The levels of the Library This Library enables each designer to select the foundry(ies) and VLSI technology of his own choice at any time during the logic design of the circuit. On this regard, the cells of the Library have been chosen not to be technology or foundry dependent. The following steps have been adopted, developing UPML_Iib: 2.
UPML
242
G.-P. Economou et aL
i. Low-level Cells These cells, constitute a set of the most commonly used by manufacturers, Standard lowlevel cells. No data about the mask level is included; schematic and behavioral descriptions of these Cells do, using most typical behavioral parameters. All the designs of UPML_Iib are based on this set of cells. The final step of a design is to map the circuit's logic level design, as developed by the schematic capture tool, to these sets of real cells, linking Cells to real foundry(ies)' cells. ii. Medium- and High-level Modules The Medium- and High-level Modules have been produced by using advanced CAD tools that produce parametrical netlists of designs. Since the Modules are based upon the Library's Leaf Cells, manufacturers' independent design is achieved. Design rules are maintained, too. A functional and approximated timing simulation of the design is also performed. For this, the behavioral models of the Leaf Cells are used, in conjunction to worst-case (or other) parameters for the chosen technology, obtained from manufacturers' specifications and appropriate statistical data. 2.2 Common Design Basis We have employed the Standard Kit of the Mentor Graphics software package (MGp) to make UPML_Iib a reality. This decision is ought to some special facilities of the schematic editor (graphical programming) and the universality of the tool. More precisely, by employing the FRAME command, the parametrical nature of the Library holds true. An easy to apply procedure is being effected in order to achieve Library Modules transportation between different CAD systems, based on international standard formats. That format is the M Behavioral Language [2]. M language enables a user to describe designs both digital and analog and provides for behavioral and structural modelling. Inertial and transport delays and load capacitances to the nodes can be read, so that drive delays can be adjusted during simulation processes. 2.3 Testability - Reliability All the Modules of the UPML_Iib are fully testable and can be incorporated in any kind of an IC design due to the special attention paid in their developing. All special design rules are satisfied and special-purpose structures have been used. Master-slave register patterns to avoid clock
skew, combinatorial circuits on the clock path strictly inhibited, internal feedback loops broken with test I/Os, are some of the features utilized to enhance the robustness of the UPML lib. Also, a buffer tree generator, which grows up with respect to the number of the output bits and the driving capability of a buffer is employed. The basic driving capability of each of those buffers can be selected by the designer (according to a specific library). 3. Library's
Contents
The semi-custom design approach has been adopted for the development of UPML_Iib. It comprises different complexity sets of: - Low-level Cells and Pads, - Medium-level and - High-level netlist generators To design a circuit using Standard Cells, a designer should use UPML_lib's Leaf Cells. Having finished with the design, the checking out for eventual errors (misplacement or bad connections), and having performed the necessary simulations, he should proceed in expanding it into a real-cells level, thus choosing a manufacturer. This step is implemented, through linking the Cells used in the design with those provided by the chosen foundry. Should a design request more complex cells, the Medium- and High-level Cells, of the Library can be used. This flow is shown in Figure 1.
UPML
Fig. 1. UPML_lib design flow.
Development of a technology independent library 3.1 Low-level Cells and Pads These Cells compose a set of the most commonly used foundries' Standard Cells and Pads. Schematic and behavioral description of these Leaf Cells are provided; pads are provided for both CMOS and TTL integrated families. The contents of the cells' set are typical Leaf Cells: basic gates of various number of inputs, latches, edge triggered flip-flops, buffers, and so on. Also, typical technology parameters for a variety of technologies (1.0/zm, 1.5/~m, 2/~m) are available for use by the behavioral models of these Cells. Low-level Pads' set comprises input, input/output, and output pads. 3.2 Medium- and High-level Module Generators These Modules have been produced by using a graphical programming technique by means of the FRAME command of the MGp Standard Kit schematic editor. Gates, (shift) registers, comparators, (de)multiplexers, encoders, decoders, different formation of adders (ripple, carry lookahead, carry-select), multipliers, dividers, programmable up and/or down counters, barrel shifters, FIFO and LIFO register structures, have been integrated in the UPML_Iib. The user has only to provide parameters such as the width of the input and/or the output bus, the number of the buses to be used etc., without having to use another software package quitting the schematic editor. Figures 2, 3, 4, and 5 show the development of some parametrical Modules of the UPML lib: the buffer tree (BUTR_nm), a nand gate (NANI~n), a comparator (COMP_n) and a comparator with output bus selection (COMPS_n). Their subscription, in a pseudo FRAME language is only for demonstrative purposes. The real gates assemble and their connections are not easily depicted due to the depth of their graphical nested and parametrical nature. We preferred this illustrative way of description because of its elegancy and completeness to a non initiated one. Each Module is defined through its symbol (e.g. COMPS_n), input (IN) and output (OUT) terminals and programmable settings (n, m). Terminals can also be buses (BUS). The structure of the Modules is then built by calling gates, latches, etc., and addressing the proper connections. When a structure is used repeatedly, then it can be entered into a FRAME and its function declared (IF, LOOP, etc.). An important feature of a FRAME command
243
is that it can support logical (&&, II, etc.) as well as arithmetic operators ( + , -, div, mod, etc.). The patterns inside the FRAME can be logical components used in any design; gates (NAND, etc.), buffers (BUFFER), even other FRAME structures (AND_n, etc.) to any depth. Nested FRAME groupings can grow up to any extend and even placement commands are supported. Much easily patterns of the Modules can be arranged so to be 'close' to each other or at any place of the final layout. Finally, INT function is used to characterize internal signals of the Modules and the '#' symbol external calls to other Modules so as to be included in the present design. 4. Library's Overview Up to this point, the development and the realisation of the UPML lib was described. As pictured, this task has been accomplished by three levels of design: the Low-level Cells, the Mediumand High-level user-programmable Modules. Thanks to the offering features, second-source enhancement, application-based specifications and even maintenance facilities along with manufacturer(s) choice at every stage of the design are offered to the designers. However, the integration of the Library could be enhanced by the introduction of Advancedlevel Modules planned to enhance the foundries' libraries. The Generator Development Tools of MGp will be used to fulfil this scope. Additionally, a system utilizing the VHDL [4] and EDIF [5] behavioral languages is being developed to ensure design transfer to other CAD tools more easily. References [1] Blionas, S., "VLSI Design for Parallel Digital Signal Processing", Ph.D. Dissertation, University of Patras, January, 1990. [2] Mentor Graphics, "M Language Users' Guide", series of Explorer Tools. [3] Six, P., Claesen, L., Rabaey, J., and De Man, H., "An Intelligent Module Generator Environment", Proc. of 23d Design Automation Conference, pp 730-735, 1986. [4] "IEEE Standard VHDL Language Reference Manual", March, 1988. [5] Electronic Industries Association, "Electronic Design Interchange Format", Version 2 0 0, Recommended Standard EIA-548, March, 1988.
G.-P. Economou et al.
244 BUTR_nm (IN(ck), P(n), P(m), OUT(BUS(c(n-1:0)))) v = ndivm w = nmodm x = ( m - 1 + w)divm y = (v + x)divm z = (v + x)modm IF ( (n < m) && (n < = IST(ekl) = BUFFER( LOOP(i = 0 T O ( y + IST(a(i)) = ekl ELSE LOOP(i =0TO(y + INT(a(i)) = ck
m*(m-1)) I [ (n > m ' m ) ) ck ) ( m - 1 + z ) d i v m - 1))
( m - 1 + z ) d i v m - 1))
LOOP(j = 0 TO ((n div 4) + ((n mod 4) + 1)div 4 - l) I F ( ( ( n d i v 4 ) + ( ( n m o d 4 ) + l ) d i v 4 - 1) > = 0 ) INT(b(j)) = (INT(a(2*j)) NOR IST(a(2*j + l)) ) IF ( ((n mod 4) > 0) && ((n mod 4) < = 2 ) ) INT(b(n div 4)) = NOT( INT(a(2*((n div 4) + + ((n mod 4) + l)div4)))) LOOP(j = 0 TO ((n div 8) + ((n rood 8) + 3)div 8 - 1) IP(((ndiv8)+ ((nmod8) +3)div8-1) >=0) lST(c(j)) = (INT(b(2*j)) NAND INT(b(2*j + 1)) ) IF ( ((n mod 8) > 0) && ((o mod 8) < = 4) ) IST(c(n div 8)) = NOT( INT(b(2*((n div 8) + + ((n rood 8) + 3)div8))) )
LOOP(j = 0 T O y ) u = j*m IF((v+x) >=m) LOOP(i = u T o ( u + m - 1)) I F ( i < (v + x ) ) INT(b(i)) = INT(al (,j)) I F ( u < (v + x ) ) INT(aI0)) = BUFFER(INT(a(j)) ) ELSE LOOP(i = 0 T O ( v + x - 1)) INT(b(i)) = INT(a(j))
LOOP(j = 0 TO ((n div 16) + ((n mod 16) + 7)div 16 - 1) IF ( ((n div 16) + ((n rood 16) + 7)div 1 6 - 1) > = 0 ) INT(d(j)) = (INT(c(2*j)) NOR INT(e(2*j + 1)) ) IF ( ((n rand 16) > 0) && ((n rood 16) < = 8) ) lST(b(d div 16)) = SOT( INT(c(2*((ndiv 16) + + ((n rood 16) + 7)div16))))
LOOP0 = 0 TO (n div m) ) u = j*m IF(n>=m) LOOP(i = u T O ( u + m - 1)) IF(i
LOOP(j = 0 TO ((o div 32) + ((n rood 32) + 15)div 32 - 1) IF ( ((n div 32) + ((n rood 32) + 15)div 32 - 1) > = 0 ) INT(e0)) = (IST(d(2*j)) S A N D INT(d(2*j + 1)) ) IF ( ((n rood 32) > 0) && ((n rood 32) < = 16) ) INT(b(e div 32)) = NOT( INT(d(2*((n div 32) + + ((n mod 32) + 15)div32))))
INT(bI(j) ) = BUFFER(INT(b(j)) ELSE LOOP(i = 0TO(nI)) c(i) = INT(b(j)) END OF BUTR nm
Fig. 2. Structure of B U T R
N A N D n (IN(BUS(i(o-1:0))), P(n), OUT(o) ) LOOP(j = 0 TO ((n div 2) - I) ) INT(a(j)) = (in(2*j) NAND in(2*j + 1) ) IF((nmod2) <> 0) INT(a(n div 2)) = NOT( in(n - l) )
)
nm
COMP_n< IN(BUS(a(n-1:0))), IN(BUS(b(n-1:0))), P(n), OUT(agb), OUT(aeb), OUT(alb) ) LOOP(j = 0 T O n - 1 ) INT(ab(j)) = ((a(j) NAND (NOT(b(j)))) INT(c0)) = (a(j) EXNOR b(j) ) LOOP( j = 2 TO n - 1 ) #AND_n(IN(c(n-1:0)), P(n - j + 1), OUT(INT(d)) ) INT(e) = ( INT(ab(j - 2)) NAND INT(d) ) INT(0 = NOT(INT(e) )
IF(n > 32) o = (INT(e(0)) NOR INT(e(1)) ) ELSE o = NOT(INT(e(0)) ) END OF S A N D n
Fig. 4. Structure of SAND n COMPS n (IN(BUS(a(n-1:0))), IN(BUSCo(n- 1:0))), IN (sel), P(n), OUT(BUS(re(n-1:0))), OUT(agb), OUT(avb), OUT(alb) ) #COMP_o(IN(a(n-1:0)), INCo(n-1:0)), P(n), OUT(agb). OUT(aeb), OUT(alb) ) INT(e) = SOT( sel ) INT(d) = ( alb S A N D INT(c) ) INT(¢) = ( agb S A N D sel ) INT(s) = (INT(d) S A N D INT(e) ) I F ( n > = 2) INT(sl) = BUFFER(INT(s) ) ELSE INT(sl) = INT(s)
INT(f(0)) = INT(ab(n- 1)) INT(f(1)) = NOT( ( INT(e(n - 1)) NAND INT(ab(n - 2)) ) ) #OR_n( IN(f(n- 1:0)), P(n), OUT(agb) ) #AND_n(IN(c(n-1:0)), P(n), OUT(aeb) ) alb = ( agb EXNOR aeb ) END OF COMP n
LOOP(j = 0 T O o - 1 INT(f) = NOT(INT(sl) ) INT(g) = (a(j) S A N D INT(0 ) IST(h) = ( b 0 ) S A N D INT(sl) ) mfj) = (INT(g) S A N D INT(h) ) END OF COMPS n
Fig. 3. Structure of COMP n
Fig. 5. Structure of COMPS n
241
Development of a Technology Independent Library G. - P. E~.onomou, S. S. Nikolaidis, D. E. Metafas, C. E. Goutis VLSI Design Laboratory Department of Electrical Engineering University of Patras Greece
A technology-independentlibrarywhich is appropriatefor fast turn-around ASIC design is introduced. This library is based on a set of technology-independentLeafCells and a set of high-leveluser programmableModulesbuilt using them. Distinctdesign rules for developing the Modules have been adopted, from a set of manufacturers'most commondesign rules, thus resulting in the improvementof reliability and testability of designs. Using the set of Modules, the overall design time is reduced; furthermore, the structure of the library, enhances the aptitude of the designer to select a suitable IC manufacturerwhen most advantageous,independentlyof the progress of the design.
1.
Introduction
In the past years a steady increase has been evolved in customer demands for high performance, intense throughput, and signal/image processing modules which can be effectively used in ASICs design. The design and the development of a widely accepted Module Library to fulfil this purpose is the topic treated in this paper. Our purpose was the building of an efficient integrated CAD system on which to design, simulate, and develop an Integrated Circuit (IC) in the shortest time. By means of this library, named UPML_Iib, designers are supported with a manufacturers' common set of basic cells and a set of high performance user programmable modules [1]. These sets can be further used for fastturnaround ASIC design on the application fields that the designers would be interested in. In order to satisfy demands such as the feasibility of the design, the easiness of the implementation, the transferring quickness, the design environment compatibility factors, the reliability, and the testability of the design, a SemiCustom design approach, commonly used for ASIC designs, has been employed to accomplish this Library. Three individual Library levels, containing Low-, Medium- and High-level Cells, have been implemented to complete this task. Furthermore, various I/O pads are provided too. The central idea beyond the Library's set up is that it will act as an
intermediate level between logic-level designs and the great variety of manufacturers' real library cells to subsequently form the physical level designs. The UPML_Iib comes to help designers develop ICs on an environment - that is Manufacturers' Independent, - which offers a Common Design Basis, - supporting ASICs Design, - rich of Testability - Reliability conventions, - permissive of Fast turn-around design. lib's Development Process N~wadays, a lot of chip manufacturers offer many advantageous modes to implement a design and to keep on edge of technology in the competitive world of VLSI design and ASICs domain. Those ways, however, tend to be style-, technology-, design-, and manufacturer-dependent, inhibiting a designer to select from a variety of alternative choices after a design has been developed. As a matter of fact, a designer had first to choose a foundry and then to design. 2.1 The levels of the Library This Library enables each designer to select the foundry(ies) and VLSI technology of his own choice at any time during the logic design of the circuit. On this regard, the cells of the Library have been chosen not to be technology or foundry dependent. The following steps have been adopted, developing UPML_Iib: 2.
UPML
242
G.-P. Economou et aL
i. Low-level Cells These cells, constitute a set of the most commonly used by manufacturers, Standard lowlevel cells. No data about the mask level is included; schematic and behavioral descriptions of these Cells do, using most typical behavioral parameters. All the designs of UPML_Iib are based on this set of cells. The final step of a design is to map the circuit's logic level design, as developed by the schematic capture tool, to these sets of real cells, linking Cells to real foundry(ies)' cells. ii. Medium- and High-level Modules The Medium- and High-level Modules have been produced by using advanced CAD tools that produce parametrical netlists of designs. Since the Modules are based upon the Library's Leaf Cells, manufacturers' independent design is achieved. Design rules are maintained, too. A functional and approximated timing simulation of the design is also performed. For this, the behavioral models of the Leaf Cells are used, in conjunction to worst-case (or other) parameters for the chosen technology, obtained from manufacturers' specifications and appropriate statistical data. 2.2 Common Design Basis We have employed the Standard Kit of the Mentor Graphics software package (MGp) to make UPML_Iib a reality. This decision is ought to some special facilities of the schematic editor (graphical programming) and the universality of the tool. More precisely, by employing the FRAME command, the parametrical nature of the Library holds true. An easy to apply procedure is being effected in order to achieve Library Modules transportation between different CAD systems, based on international standard formats. That format is the M Behavioral Language [2]. M language enables a user to describe designs both digital and analog and provides for behavioral and structural modelling. Inertial and transport delays and load capacitances to the nodes can be read, so that drive delays can be adjusted during simulation processes. 2.3 Testability - Reliability All the Modules of the UPML_Iib are fully testable and can be incorporated in any kind of an IC design due to the special attention paid in their developing. All special design rules are satisfied and special-purpose structures have been used. Master-slave register patterns to avoid clock
skew, combinatorial circuits on the clock path strictly inhibited, internal feedback loops broken with test I/Os, are some of the features utilized to enhance the robustness of the UPML lib. Also, a buffer tree generator, which grows up with respect to the number of the output bits and the driving capability of a buffer is employed. The basic driving capability of each of those buffers can be selected by the designer (according to a specific library). 3. Library's
Contents
The semi-custom design approach has been adopted for the development of UPML_Iib. It comprises different complexity sets of: - Low-level Cells and Pads, - Medium-level and - High-level netlist generators To design a circuit using Standard Cells, a designer should use UPML_lib's Leaf Cells. Having finished with the design, the checking out for eventual errors (misplacement or bad connections), and having performed the necessary simulations, he should proceed in expanding it into a real-cells level, thus choosing a manufacturer. This step is implemented, through linking the Cells used in the design with those provided by the chosen foundry. Should a design request more complex cells, the Medium- and High-level Cells, of the Library can be used. This flow is shown in Figure 1.
UPML
Fig. 1. UPML_lib design flow.
Development of a technology independent library 3.1 Low-level Cells and Pads These Cells compose a set of the most commonly used foundries' Standard Cells and Pads. Schematic and behavioral description of these Leaf Cells are provided; pads are provided for both CMOS and TTL integrated families. The contents of the cells' set are typical Leaf Cells: basic gates of various number of inputs, latches, edge triggered flip-flops, buffers, and so on. Also, typical technology parameters for a variety of technologies (1.0/zm, 1.5/~m, 2/~m) are available for use by the behavioral models of these Cells. Low-level Pads' set comprises input, input/output, and output pads. 3.2 Medium- and High-level Module Generators These Modules have been produced by using a graphical programming technique by means of the FRAME command of the MGp Standard Kit schematic editor. Gates, (shift) registers, comparators, (de)multiplexers, encoders, decoders, different formation of adders (ripple, carry lookahead, carry-select), multipliers, dividers, programmable up and/or down counters, barrel shifters, FIFO and LIFO register structures, have been integrated in the UPML_Iib. The user has only to provide parameters such as the width of the input and/or the output bus, the number of the buses to be used etc., without having to use another software package quitting the schematic editor. Figures 2, 3, 4, and 5 show the development of some parametrical Modules of the UPML lib: the buffer tree (BUTR_nm), a nand gate (NANI~n), a comparator (COMP_n) and a comparator with output bus selection (COMPS_n). Their subscription, in a pseudo FRAME language is only for demonstrative purposes. The real gates assemble and their connections are not easily depicted due to the depth of their graphical nested and parametrical nature. We preferred this illustrative way of description because of its elegancy and completeness to a non initiated one. Each Module is defined through its symbol (e.g. COMPS_n), input (IN) and output (OUT) terminals and programmable settings (n, m). Terminals can also be buses (BUS). The structure of the Modules is then built by calling gates, latches, etc., and addressing the proper connections. When a structure is used repeatedly, then it can be entered into a FRAME and its function declared (IF, LOOP, etc.). An important feature of a FRAME command
243
is that it can support logical (&&, II, etc.) as well as arithmetic operators ( + , -, div, mod, etc.). The patterns inside the FRAME can be logical components used in any design; gates (NAND, etc.), buffers (BUFFER), even other FRAME structures (AND_n, etc.) to any depth. Nested FRAME groupings can grow up to any extend and even placement commands are supported. Much easily patterns of the Modules can be arranged so to be 'close' to each other or at any place of the final layout. Finally, INT function is used to characterize internal signals of the Modules and the '#' symbol external calls to other Modules so as to be included in the present design. 4. Library's Overview Up to this point, the development and the realisation of the UPML lib was described. As pictured, this task has been accomplished by three levels of design: the Low-level Cells, the Mediumand High-level user-programmable Modules. Thanks to the offering features, second-source enhancement, application-based specifications and even maintenance facilities along with manufacturer(s) choice at every stage of the design are offered to the designers. However, the integration of the Library could be enhanced by the introduction of Advancedlevel Modules planned to enhance the foundries' libraries. The Generator Development Tools of MGp will be used to fulfil this scope. Additionally, a system utilizing the VHDL [4] and EDIF [5] behavioral languages is being developed to ensure design transfer to other CAD tools more easily. References [1] Blionas, S., "VLSI Design for Parallel Digital Signal Processing", Ph.D. Dissertation, University of Patras, January, 1990. [2] Mentor Graphics, "M Language Users' Guide", series of Explorer Tools. [3] Six, P., Claesen, L., Rabaey, J., and De Man, H., "An Intelligent Module Generator Environment", Proc. of 23d Design Automation Conference, pp 730-735, 1986. [4] "IEEE Standard VHDL Language Reference Manual", March, 1988. [5] Electronic Industries Association, "Electronic Design Interchange Format", Version 2 0 0, Recommended Standard EIA-548, March, 1988.
G.-P. Economou et al.
244 BUTR_nm (IN(ck), P(n), P(m), OUT(BUS(c(n-1:0)))) v = ndivm w = nmodm x = ( m - 1 + w)divm y = (v + x)divm z = (v + x)modm IF ( (n < m) && (n < = IST(ekl) = BUFFER( LOOP(i = 0 T O ( y + IST(a(i)) = ekl ELSE LOOP(i =0TO(y + INT(a(i)) = ck
m*(m-1)) I [ (n > m ' m ) ) ck ) ( m - 1 + z ) d i v m - 1))
( m - 1 + z ) d i v m - 1))
LOOP(j = 0 TO ((n div 4) + ((n mod 4) + 1)div 4 - l) I F ( ( ( n d i v 4 ) + ( ( n m o d 4 ) + l ) d i v 4 - 1) > = 0 ) INT(b(j)) = (INT(a(2*j)) NOR IST(a(2*j + l)) ) IF ( ((n mod 4) > 0) && ((n mod 4) < = 2 ) ) INT(b(n div 4)) = NOT( INT(a(2*((n div 4) + + ((n mod 4) + l)div4)))) LOOP(j = 0 TO ((n div 8) + ((n rood 8) + 3)div 8 - 1) IP(((ndiv8)+ ((nmod8) +3)div8-1) >=0) lST(c(j)) = (INT(b(2*j)) NAND INT(b(2*j + 1)) ) IF ( ((n mod 8) > 0) && ((o mod 8) < = 4) ) IST(c(n div 8)) = NOT( INT(b(2*((n div 8) + + ((n rood 8) + 3)div8))) )
LOOP(j = 0 T O y ) u = j*m IF((v+x) >=m) LOOP(i = u T o ( u + m - 1)) I F ( i < (v + x ) ) INT(b(i)) = INT(al (,j)) I F ( u < (v + x ) ) INT(aI0)) = BUFFER(INT(a(j)) ) ELSE LOOP(i = 0 T O ( v + x - 1)) INT(b(i)) = INT(a(j))
LOOP(j = 0 TO ((n div 16) + ((n mod 16) + 7)div 16 - 1) IF ( ((n div 16) + ((n rood 16) + 7)div 1 6 - 1) > = 0 ) INT(d(j)) = (INT(c(2*j)) NOR INT(e(2*j + 1)) ) IF ( ((n rand 16) > 0) && ((n rood 16) < = 8) ) lST(b(d div 16)) = SOT( INT(c(2*((ndiv 16) + + ((n rood 16) + 7)div16))))
LOOP0 = 0 TO (n div m) ) u = j*m IF(n>=m) LOOP(i = u T O ( u + m - 1)) IF(i
LOOP(j = 0 TO ((o div 32) + ((n rood 32) + 15)div 32 - 1) IF ( ((n div 32) + ((n rood 32) + 15)div 32 - 1) > = 0 ) INT(e0)) = (IST(d(2*j)) S A N D INT(d(2*j + 1)) ) IF ( ((n rood 32) > 0) && ((n rood 32) < = 16) ) INT(b(e div 32)) = NOT( INT(d(2*((n div 32) + + ((n mod 32) + 15)div32))))
INT(bI(j) ) = BUFFER(INT(b(j)) ELSE LOOP(i = 0TO(nI)) c(i) = INT(b(j)) END OF BUTR nm
Fig. 2. Structure of B U T R
N A N D n (IN(BUS(i(o-1:0))), P(n), OUT(o) ) LOOP(j = 0 TO ((n div 2) - I) ) INT(a(j)) = (in(2*j) NAND in(2*j + 1) ) IF((nmod2) <> 0) INT(a(n div 2)) = NOT( in(n - l) )
)
nm
COMP_n< IN(BUS(a(n-1:0))), IN(BUS(b(n-1:0))), P(n), OUT(agb), OUT(aeb), OUT(alb) ) LOOP(j = 0 T O n - 1 ) INT(ab(j)) = ((a(j) NAND (NOT(b(j)))) INT(c0)) = (a(j) EXNOR b(j) ) LOOP( j = 2 TO n - 1 ) #AND_n(IN(c(n-1:0)), P(n - j + 1), OUT(INT(d)) ) INT(e) = ( INT(ab(j - 2)) NAND INT(d) ) INT(0 = NOT(INT(e) )
IF(n > 32) o = (INT(e(0)) NOR INT(e(1)) ) ELSE o = NOT(INT(e(0)) ) END OF S A N D n
Fig. 4. Structure of SAND n COMPS n (IN(BUS(a(n-1:0))), IN(BUSCo(n- 1:0))), IN (sel), P(n), OUT(BUS(re(n-1:0))), OUT(agb), OUT(avb), OUT(alb) ) #COMP_o(IN(a(n-1:0)), INCo(n-1:0)), P(n), OUT(agb). OUT(aeb), OUT(alb) ) INT(e) = SOT( sel ) INT(d) = ( alb S A N D INT(c) ) INT(¢) = ( agb S A N D sel ) INT(s) = (INT(d) S A N D INT(e) ) I F ( n > = 2) INT(sl) = BUFFER(INT(s) ) ELSE INT(sl) = INT(s)
INT(f(0)) = INT(ab(n- 1)) INT(f(1)) = NOT( ( INT(e(n - 1)) NAND INT(ab(n - 2)) ) ) #OR_n( IN(f(n- 1:0)), P(n), OUT(agb) ) #AND_n(IN(c(n-1:0)), P(n), OUT(aeb) ) alb = ( agb EXNOR aeb ) END OF COMP n
LOOP(j = 0 T O o - 1 INT(f) = NOT(INT(sl) ) INT(g) = (a(j) S A N D INT(0 ) IST(h) = ( b 0 ) S A N D INT(sl) ) mfj) = (INT(g) S A N D INT(h) ) END OF COMPS n
Fig. 3. Structure of COMP n
Fig. 5. Structure of COMPS n