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Technology independent ASIC design methodology
World Abstracts on Microelectronics and Reliability wafer surfaces in solutions can be described by the welldocumented principles of colloid science. Particle concentration, solution pH, and ionic strength in solutions are all important factors which determine the number of particles which deposit on wafer surfaces immersed in liquids. Maximum particle deposition is observed in high ionic strength acidic solutions and is reduced as solution pH increase. Particle removal etiiciencies in various solutions were also investigated NH4OH-H202-H20 solutions were optimized in NH4OH content around the ratio of 0.05:1.5 (0.05 part NH4OH, 1 part H202, 5 parts H20). Wafer damage as measured by surface micro-roughness was not increased during NH4OH-H202-H20treatment using this ratio. Test dominates MCM assembly. JOHN BOND. Test Measmt Wld, 59 (March 1992). From the bare die to the assembled multichip module, you need to test every step of the way to ensure a final product that works.
A comparison of the optical projection lithography simulators in SAMPLE and PROLITH. OSCAR D. CREALLE et al. IEEE Trans. Semicond. mfg 5, 14 (1992). Although the simulation and modeling of profiles for lithography and etching (SAMPLE) and positive resist optical lithography (PROLITH) photolithography simulators perform the same functions, they rely on different models and numerical algorithms for the calculation of aerial and latent images, differ in the method used for propagating development fronts, and use different development-rate models. This paper documents important algorithmic details not available in the open literature, and illustrates differences and similarities between the programs using representative lithography systems as examples. Numerical comparisons demonstrate that the aerial images calculated by SAMPLE and PROLITH are in generally good agreement. At high numerical resolution the programs provide the same qualitative lithography information, including latent images and edge profile results; however, significant degradation occurs at lower resolutions. Adequate results are obtained using a vertical resolution smaller than one-twentieth of the theoretical standing-wave wavelength. Significant disagreement is found in the output of the post-exposure bake algorithms where SAMPLE predicts much lower standingwave amplitude attenuation effects. Based on the observation that a development-rate model must match experimental data only within a critical inhibitor concentration region, a new guideline is proposed for choosing the parameters for development rate models. Only PROLITH is capable of predicting the asymmetric behaviour observed in experimental data relating critical dimensions to defocus. The band algorithm used in SAMPLE for the calculation of linewidths is found to be a more reliable method for measuring critical dimensions. Binary and phase shifting mask design for optical lithography. YONGLIU and AVIDEHZAKHOR.1EEE Trans. Semicond. mfg 5, 138 (1992). We propose a number of pre-distorted mask design techniques for binary and phase-shifting masks. Our approach is based on modeling the imaging mechanism of a stepper by the Hopkins equations and taking advantage of the contrast-enhancement characteristics of photoresist. Optimization techniques such as the branch and bound algorithm and simulated annealing algorithm are used to systematically design pre-distorted masks under incoherent and partially coherent illumination. Computer simulations are used to show that the intensity contour shapes and
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S ,
The design of secand-order bit sliced Infinite impolse response digital filter chips using CIRCAD IL MASum OTtIMANet aL Microelectron. J. 23, 37 (1992). A digit slicing technique was proposed to speed up the computation of important
1795
developed resist shapes of our designed mask patterns are sharper than those of conventional masks. The designed phase-shifting masks are shown to result in higher contrast as well as sharper contours than binary masks. An example of phase conflicting mask designed via our algorithm is shown to outperform a simple intuitive design. This example indicates that a fairly general design procedure consisting of alternating phase shifts and our optimized phase-shift mask is a viable candidate for future phase-shifting mask design.
A general characterization and simulation method for deposition and etching technology. SATOSHITAZAWAet al. 1EEE Trans. Semicond. mfg 5, 27 (1992). A topography simulation system and a six-parameter unified process model are proposed for general characterization of deposition and etching technology. This system is fit to use experimentally. This model precisely expresses the process characteristics of deposition and etching equipment. A surface movement vector calculation method suitable for the unified model is also given. This method is used for calculating crosssectional profiles including convex and concave corners, and for general LSI processes where deposition and etching reactions occur simultaneously. The parameters can be extracted from experimental results. The extraction method is also introduced in this paper. The simulated results agree well with the experimental ones of sputter deposition and Bias-ECR deposition. Statistical bin limits---an approach to wafer disposition in IC fabrication. STYEVEILLYESand DAVIDA. G. BAGLEE.1EEE Trans. Semincond. mfg 5, 59 (1992). This paper describes the methodology of selecting and implementing statistical bin limits at wafer level test so as to minimize value added to defective product, improve the overall quality and reliability of product, and provide a tool for helping to drive root cause identification of fabrication problems.
High-level ASIC design tools. SEANREDMOND.Microelectron. 23, 231 (1992). New high-level design tools developed for ASIC designers are making it possible to assess accurately specification priorities at a much earlier stage in the design process. Silicon considerations can be built into the design from the beginning leading to more eflicient and cost effective devices. More accurate evaluations earlier on make it far less likely that designs will be created which cannot be manufactured, eliminating time-consuming, cost revisions and minimizing time-to-market. Technology independent ASIC design methodology. J. ADAMS et al. Electrl Commun. 65, (2), 168 (1992). In this paper a global picture of a VLSI top-down design methodology is presented. This method, which is based on the extensive use of hardware description languages, associated multi-level simulation and logic synthesis tools is pushing the design activities from the gate level to the system level. Some of the CAD tools, such as floorplanning, simulation, and synthesis, and Alcatel-recommended CAE tool vendors, are focused upon. The mapping to an actual gate level implementation where silicon information is needed, is postponed as far as possible in the design cycle. This allows high flexibility to cope with late modifications, or new requirements. For the eventual circuit implementation a choice will be made between the two most important ASIC technologies: cell-based and sea-of-gates. The importance of SOG for large or complex designs is highlighted. SYSTEMS
AND
EQUIPMENT
parameters in digital signal processing. In this paper we describe the use of a technique to produce fast second-order digit sliced IIR digital filter chips. The silicon chip is produced by using an IC design package called CIRCAD II.
A comparison of the optical projection lithography simulators in SAMPLE and PROLITH. OSCAR D. CREALLE et al. IEEE Trans. Semicond. mfg 5, 14 (1992). Although the simulation and modeling of profiles for lithography and etching (SAMPLE) and positive resist optical lithography (PROLITH) photolithography simulators perform the same functions, they rely on different models and numerical algorithms for the calculation of aerial and latent images, differ in the method used for propagating development fronts, and use different development-rate models. This paper documents important algorithmic details not available in the open literature, and illustrates differences and similarities between the programs using representative lithography systems as examples. Numerical comparisons demonstrate that the aerial images calculated by SAMPLE and PROLITH are in generally good agreement. At high numerical resolution the programs provide the same qualitative lithography information, including latent images and edge profile results; however, significant degradation occurs at lower resolutions. Adequate results are obtained using a vertical resolution smaller than one-twentieth of the theoretical standing-wave wavelength. Significant disagreement is found in the output of the post-exposure bake algorithms where SAMPLE predicts much lower standingwave amplitude attenuation effects. Based on the observation that a development-rate model must match experimental data only within a critical inhibitor concentration region, a new guideline is proposed for choosing the parameters for development rate models. Only PROLITH is capable of predicting the asymmetric behaviour observed in experimental data relating critical dimensions to defocus. The band algorithm used in SAMPLE for the calculation of linewidths is found to be a more reliable method for measuring critical dimensions. Binary and phase shifting mask design for optical lithography. YONGLIU and AVIDEHZAKHOR.1EEE Trans. Semicond. mfg 5, 138 (1992). We propose a number of pre-distorted mask design techniques for binary and phase-shifting masks. Our approach is based on modeling the imaging mechanism of a stepper by the Hopkins equations and taking advantage of the contrast-enhancement characteristics of photoresist. Optimization techniques such as the branch and bound algorithm and simulated annealing algorithm are used to systematically design pre-distorted masks under incoherent and partially coherent illumination. Computer simulations are used to show that the intensity contour shapes and
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S ,
The design of secand-order bit sliced Infinite impolse response digital filter chips using CIRCAD IL MASum OTtIMANet aL Microelectron. J. 23, 37 (1992). A digit slicing technique was proposed to speed up the computation of important
1795
developed resist shapes of our designed mask patterns are sharper than those of conventional masks. The designed phase-shifting masks are shown to result in higher contrast as well as sharper contours than binary masks. An example of phase conflicting mask designed via our algorithm is shown to outperform a simple intuitive design. This example indicates that a fairly general design procedure consisting of alternating phase shifts and our optimized phase-shift mask is a viable candidate for future phase-shifting mask design.
A general characterization and simulation method for deposition and etching technology. SATOSHITAZAWAet al. 1EEE Trans. Semicond. mfg 5, 27 (1992). A topography simulation system and a six-parameter unified process model are proposed for general characterization of deposition and etching technology. This system is fit to use experimentally. This model precisely expresses the process characteristics of deposition and etching equipment. A surface movement vector calculation method suitable for the unified model is also given. This method is used for calculating crosssectional profiles including convex and concave corners, and for general LSI processes where deposition and etching reactions occur simultaneously. The parameters can be extracted from experimental results. The extraction method is also introduced in this paper. The simulated results agree well with the experimental ones of sputter deposition and Bias-ECR deposition. Statistical bin limits---an approach to wafer disposition in IC fabrication. STYEVEILLYESand DAVIDA. G. BAGLEE.1EEE Trans. Semincond. mfg 5, 59 (1992). This paper describes the methodology of selecting and implementing statistical bin limits at wafer level test so as to minimize value added to defective product, improve the overall quality and reliability of product, and provide a tool for helping to drive root cause identification of fabrication problems.
High-level ASIC design tools. SEANREDMOND.Microelectron. 23, 231 (1992). New high-level design tools developed for ASIC designers are making it possible to assess accurately specification priorities at a much earlier stage in the design process. Silicon considerations can be built into the design from the beginning leading to more eflicient and cost effective devices. More accurate evaluations earlier on make it far less likely that designs will be created which cannot be manufactured, eliminating time-consuming, cost revisions and minimizing time-to-market. Technology independent ASIC design methodology. J. ADAMS et al. Electrl Commun. 65, (2), 168 (1992). In this paper a global picture of a VLSI top-down design methodology is presented. This method, which is based on the extensive use of hardware description languages, associated multi-level simulation and logic synthesis tools is pushing the design activities from the gate level to the system level. Some of the CAD tools, such as floorplanning, simulation, and synthesis, and Alcatel-recommended CAE tool vendors, are focused upon. The mapping to an actual gate level implementation where silicon information is needed, is postponed as far as possible in the design cycle. This allows high flexibility to cope with late modifications, or new requirements. For the eventual circuit implementation a choice will be made between the two most important ASIC technologies: cell-based and sea-of-gates. The importance of SOG for large or complex designs is highlighted. SYSTEMS
AND
EQUIPMENT
parameters in digital signal processing. In this paper we describe the use of a technique to produce fast second-order digit sliced IIR digital filter chips. The silicon chip is produced by using an IC design package called CIRCAD II.