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ASIC design: progress in the GDR
Update ASIC design: progress in the GDR The emerging microelectronics industries of the eastern bloc countries have only recently turned their attention to semicustom chips. Christoph Suehnel reviews developments in ASIC design and test in the GDR
The paper presents the most important systems for ASIC design developed in the GDR. Hardware is available in modem CMOS technologies at several process levels. The design process is supported by state-of-the-art CAD systems. Thesesystems ensure the correct sequence of the design steps and application of design data. In turn they allow for structural test by means of the level-sensitive scan design method. The test-pattems required are generated by using the circuit description. The design process is demonstrated by the design of gate arrays for digital sound broadcasting equipment. micro~systems semicustom design ASICs
The ever increasing integration rate of ICs and the mastering of CMOS technologies, together with the requirement of greater compactness of highly sophisticated system solutions have led to ASICs acquiring great importance. The development of CPU and memory ICs has played a significant role in the GDR for a long time. Much money was spent on such projects but the results were unimportant. This was a consequence of the high requirements in respect of technology and modem design tools and the limited opportunities. At first the design of ASICs played a small role only, although the automation, communication and computer industries provided a large demand. Above all, such chips were needed for electronic control units in tool machines, for computers and in telephone systems. But the planned economy prevented adequate and timely cultivation of this field. The importance of ASICs has been realized quite late. This is recognized by the recent development of specific ASIC systems based on gate arrays and standard cells in CMOS and bipolar technologies. First, an analogue gate array (ISA)1 in 12Ltechnology was Central Institutefor Cyberneticsand Information Processes,Haeckelstr. 20, 8027 Dresden,GDR This paper is the first in an occasionalseriesthat will surveythe stateof chip designtechnologyin the emergingeasternbloc countriesand other developing nations Paperreceived:16 March 1990. Revised:29 June 1990
developed. This system offers four different master chips with various numbers of bipolar transistors, resistances and capacitances. Later the ISA system was completed by a master chip for digital use. Simultaneously, a CMOS standard cell system (U1500) in a 4pro technology was developed. The design support for these systems was poor. Layout was by hand, using simple graphic editors. For functional verification electrical and logical simulators existed. The4nput of the circuitry was achieved by a net list description. Because the layout was not generated using the circuit description the verification of the layout played an important role. A well-known method for this step works through recognition of the transistor model of the circuit from the graphical layout and subsequent simulation. However, this method is applicable up to a certain complexity only. Later, design support for the ISA system was improved 2, 3 and new semicustom systems in CMOS technologies were developed. These systems are presented here. The development of state-of-the-art design systems did not, however, lead to the solution of the ASIC problem in the GDR. ASICs could now be designed, but the fabrication conditions were poor. Only a small number of the chips required could be produced and the quality and reliability of these ASICs was low. In addition, production costs were high -- about eight to ten times higher than in the West. The same was true of design costs. Design and production were uneconomical. Under the new political and economic conditions microelectronics cannot be supported by the government in the same way as before. Therefore a situation exists where a large number of specialists are able to design microelectronic chips but no foundry in the GDR can produce them. Another aspect is the isolation of the design engineers in the GDR in the past. Because of the embargo on modem computers, design tools and semiconductor technologies, the design work took place under rigid security restrictions. Contacts with foreign design centres, foundries and research institutes were not allowed. But high performance is only possible with international cooperation in all fields. It is hoped that now the blockade can be ended and microelectronics in the GDR will receive a fresh impetus.
0141-9331/90/08531-11 © 1990 ButtenNorth-Heinemann Ltd
Vol 14 No 8 October 1990
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Update GATE ARRAY SYSTEM U 5 2 0 0
• a pad and input protection; • a converter for the input level and a driving unit; • an output unit with facility for the test case.
General description The gate array U52004's is based on a 4/Jm CMOS technology with one metal layer and two polysilicon layers. One silicon layer, the metal layer and the contacts between these two layers are used for the application specific programming of the master. The main features of the system are summarized in Table 1. The U5200 uses the level-sensitive scan design (LSSD) test method. For this procedure information storage is possible in master-slave flip-flops only. Therefore this system uses a static CMOS logic without transmission gates. The parameters of the transistors were optimized for macros with two inputs (i.e. NAND2, NOR2). Typical propagation delay times for NAND and NOR gates are given in Table 2. The gates and flip-flops are arranged in rows on the master chip. Two gate rows alternate with one flip-flop row. The flip-flops are led out for the LSSD test method. This means they are master-slave flip-flops possessing both a work slave and a 'shift slave'. The shift slave is used for test (shift mode). In the shift mode all shift slaves are decoupled from the master. They build a shift register and through the shift input any sequence of 0 and 1 can be written to this shift register. Switching to work or shift mode takes place by a mode control signal. The CAD system ARCHIMEDES completes the U5200 system.
Interface system The pin units available to the designer are built up in the same way. They comprise
Table 1. Main features of the U5200 Chip area Gates Combinatorial gates Master-slave flip-flops Interface units System service pins Ground/voltage pins Total pin count Propagation delay (NAND2)
Table 2.
Clock system All flip-flops are supplied by the system clock and the user is thus restricted to synchronous circuits. Manipulations of the system clock are not possible. The clock path runs from the input-level converter via the drivers of the clock distribution to the 'row drivers'. The clock path for the row drivers contains a polysilicon connection between rows 3 and 4. This causes a time difference between the clock signals for the flip-flop rows 1 to 3 and 4 to 6 (clock skew) with consequences for the upper limit of the clock rate. The maximum clock rate (FFMAX) of a complete routed gate array is restricted by factors other than the clock skew (tSW). These include • the SET UP time of the flip-flops (tSU); • the minimum time for the clock low phase of the individual flip-flops (1/2fMAX); • the propagation delay of the longest combinatorial part (tLK); • the time during which additional inputs are possible (tlNP). Only the last two may be influenced by the designer. The following formula is valid for fTMAX 1/fTMAX = 2tSW + tlNP + tLK + tSK + 1/2fMAX
7.4 mm x 7.4 mm 3000 1020 102 52 7 5 64 5 ns
U5200 delay times
Macro
tdel LH/ns
tdel H L/ns
NAND2 NOR2 NAND3 NOR3 NAND4 NOR4
6.1 9.3 6.7 15.4 7.3 21.0
5.0 4.1 10.3 4.2 13.6 4.4
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The designer determines the function of the interface units (input, output and bidirectional units) by the routing. The output units possess a special service for testing. This part is routed by the system automatically and the designer cannot influence this routing. This testing service enables the electrical parameters to be caught quickly and allows in-circuit test of the IC's on a PCB.
The upper border for fTMAX seems to be 5 MHz.
GATE ARRAY SYSTEM U 5 3 0 0 General description The basis for the development of this gate array was the U52OO, although U53OO6-8 was designed at a higher process level. Based on a 1.5 pm CMOS technology with two metal layers and a polysilicon layer, the &SIC is made by programming the master in the metal 1, metal 2 layers and the contacts between these layers. The system U53OO contains the masters U5301, U5302 and U5303. Their characteristic features are shown in Table 3. All the masters of this gate array are structured in streets, i.e. rows of gate cells alternating with rows of flipflop cells. The interface stages are situated around the chip. The U5302 includes a RAM memory as a speciality. The design of ASICs by this system is performed by the CAD system ARCHIMEDES. The application of the LSSD
Microprocessors and Microsystems
.Update Table 3.
Main features of the U5300 family
Chip area (mm x ram) Pins Clocks (for LSSD) Flip-flops Gates RAM capacity (kbit) Transistors Propagation delay (NAND2, fanout = 2) Max clock rate (MHz)
U5301
U5302
U5303
6.98 x 7.04 124 2 360 3840 40 000
6.98 X 7.04 124 2 200 2640 4.5 70 000
4.32 x 4.24 68 2 120 1200 13 000
0.8... 0.9 >40
0.8... 0.9 >30
0.8... 0.9 >60
technique for the design is essential. In this way the CAD system generates test patterns for the structural test automatically.
G~G4 B!
B~
U 5 3 0 0 master units Gate cells The basic element of the gate array is a cell consisting of four p-channel and four n-channel transistors. The gates of the transistors are connected pairwise (see Figure 1). The p-channel transistors are located under the wiring channels. The power supply of the cells is decided independent of the designer and performed with the routing of the macros.
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N1D y
Flip-flop cells The network of the basic flip-flop is shown in Figure 2. The flip-flop consists of the master (DFF1), the work slave (DFF2) and the shift slave (DFF3). The shift slave is connected directly to the master. The work slave is coupled by a transfer gate of the test mode control. The flip-flop functions in two modes, work mode and test (or shift) mode. In work mode the signal at the input D is stored in the master DFF1 during the low phase of the clock cycle. The slaves DFF2 and DFF3 store the last information. During the high phase the master holds the written information. The work slave reacts according to the mode control signal MT: • MT low (work mode). The work slave performs the same function as the shift slave. Both elements receive the information of the master. • MT high (shift mode). The master input is coupled via the transfer gate TC1 to the input QSI of the basic flipflop. The shift slave accepts the information from the master and the work slave stores the state received during the last work mode. The output QSO is connected with the input QSI of the following flip-flop. In this way a shift register is built which consists of all flip-flops used by the designer. This shift register can be loaded via a special pin.
Vol 14 N o 8 October 1990
It
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Figure 7.
'-tr
Basic U5300 cell
By completing the basic flip-flop with configurable input logic, several types of flip-flops can be performed. The network of the configurable input logic is shown in Figure 3. It consists of the networks SL1 and SL2, the transfer gates TG5 and TG6 and two inverters. By this method the maximum attainable clock frequency can be increased in comparison with the system U5200. Interface units The interface unit is layed out to allow the build up of a bidirectional stage. Input or output stages may also be performed by a special configuration. The input stages comprise
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S DFF1 Figure 2.
Basic U5300 flip-flop
• input protection circuitn/; • input-level converter; • master-slave flip-flop and driver unit. The output stages are configurable as • three-state, push-pull output; • open drain output stage with output enable control; • two-state push-pull output. The power supply and clock signal routing are independent of the designer. A test service function of the interface units enables the in-circuit test of the ASIC on a PCB. R A M unit
The master U5302 contains a RAM unit with a capacity of 4.5 kbit. This block consists of eight memory parts each with 64 x 9 bit. Each part has six address inputs, a chip enable input, a write enable input and nine inputs and outputs for data. All terminals for address, data and control signals are coupled by master-slave flip-flops to the gate array environment. Therefore the memory block functions synchronously for the designer. The input information may change during each clock phase. The basic RAM cell consists of six transistors. The precharge unit, record amplifier, and row and column decoders are performed by conventional circuit techniques.
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The gate array enables unidirectional data ports only. Therefore a data line control switches the data flow in respect to the write enable signal either from the data input flip-flop to the data line or from the data line to the data output flip-flop. The output control allows information exchange at all data output flip-flops only if the preceding cycle was a read cycle.
U5300
macro library
Hardware macros
The system U5300 contains 69 combinatorial macros with a complexity of one to nine gate equivalents. All combinatorial gates of the U5200 were converted for the U5300. By an appropriate configuration of the input logic of the flip-flop, six different flip-flop types can be performed: a JK flip-flop • T flip-flop • D flip-flop
• D flip-flop without clear and preset function • D flip-flop with an enable input • D flip-flop with an input multiplexer for switching two
sources
Microprocessors and Microsystems
Update
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JK flip-flop
Two kinds of interface stages exist, one for TTL signal levels and the other for CMOS signal levels. The following interface macros can be generated by configuration of the basic interface cell: • •
• • • • •
~
input stage with D flip-flop asynchronous input stage asynchronous input stage with double-driver capacity two-state output stage three-state output stage open-drain output stage bidirectional stages as combinations between the input and three-state output stages
The results for the connection of an input and an output stage loaded with a capacity of 100 pF and a TTL load are shown. Simulation results are divided into typical and worst-case times. Where fan out is 3, 0.03 pF load capacity is assumed, originating from the wiring.
A R C H I M E D E S C A D system
ARCHIMEDES is a universal CAD system for the design of gate arrays. It enables a general design from the input of Table 4.
Dynamic parameters
Software macros Software macros are aids for the design engineer. They are formulated in the net description language NBS84 and are handled by the design system as subcircuits. Software macros can be defined by the designer. The system U5300 offers macros for such applications as arithmetic circuitry.
Gate
Fan-out
Measured value ns
Simul. value ns Typ. WC
NAND2
1 3 1 3 1 3 1 3
0.63 1.04 1.20 1.81 0.57 1.10 1.40 2.15 11.9
0.62 0.97 1.43 1.95 0.62 0.97 1.38 1.91
NAND4 NOR2
Dynamic parameters
Table 4 shows a collection of simulation results and measuring values of propagation delay times for NAND and NOR macros. The fan out is one or three in each case.
Vol 14 No 8 October 1990
NOR4 I/O
0.79 1.39 1.73 2.60 0.79 1.41 1.74 2.69
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Update
_
the network description up to the generation of the data for mask making, including the generation of the test pattern for the structural LSSD test. The design process proceeds as follows. • Input of the network description and quasidynamic simulation • Placement and routing • Dynamic simulation • Test pattern generation • Data output for mask making
Network and quasidynamic simulation Input of the network description takes place in a special dialect of the net description language NBS84. This language enables a hierarchical structure of the network, i.e. the functional structure of a logic plan is reflected in its description. The basic elements of the description are the hardware macros (fixed function elements). All networks must be attributed to these elements. The hardware macros are contained in a special library and described by their logical and electrical behaviour as well as their cell layout. Both the simulator and the placement and routing modules refer to the information in this library. Software and complex macros may be used in addition to the hardware macros in the circuit description. Software macros are tested subcircuits offered by the gate array system vendor, and are contained in a software macro library. Complex macros are defined by the circuit designer. They are private software macros. By using software and complex macros the circuit description will be more clear. In preparing the simulation, the description of the circuit is checked syntactically and semantically. Next the hierarchy of the description is resolved, i.e. all subnetworks are traced back to the hardware macros. A check of the circuit is then carried out and consideration of electrical and logical design rules is tested. This procedure searches open inputs and outputs and feedbacks in combinatorial parts (forbidden because of the use of the LSSD method). Besides a correct circuit description the simulation requires appropriate simulation pattern. This pattern must be entered by hand. An appropriate description makes the recording easy. The quasidynamic logic simulation must solve the following essential tasks: • verification of the logic function of the circuit; • determination of the maximal applicable clock frequency; • localization of critical signal paths. The simulator employed is KOSIM9' 10. It uses behaviour models of the hardware macros consisting of a logic part without any delay and a propagation delay part. The simulator acknowledges four types of signal level: low (L), high (H), unknown (X) and high-impedance (Z). The delay times depend on the load and the direction of the signal
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change at the output. The simulator works with worstcase conditions of the circuit model. The simulator kernel functions on the event principle. At a given moment only those elements which experience a signal change at that moment of the circuit are considered for the simulation. By the application of the event principle the program Working time is directly proportional to the activity of the circuit. The simulator offers two kinds of simulation: • simulation of the transient during a variable clock period; • simulation ofthe transient during a fixed clock period. In the first case the maximum transient period is determined automatically. This is a measure for the minimum clock period (high phase of the clock signal), by means of which the maximum possible clock frequency can be estimated. In the last case the simulator works up to the clock edge (high/low change). A test simulation is then performed automatically. In this way subsequent signal changes at the input of the flip-flops can be recognized. The simulator can be controlled by commands in the following branches: • initialization of the design system and the circuit, i.e. preseting of flip-flops, signals, clocks and times, clearing of values, arranging input pattern to circuit inputs; • control of the simulation (start, interrupt, continue, finish, set break points, select the mode of operation); • simulation protocol; • analysis of the circuitry; • service output.
Placement and routing If the logical function of the circuit is verified, the generation of the layout can begin. The placement of the interface units (pins) is a prerequisite. After entering this information the placement and routing of the macros of the circuit is carried out automatically. Some parts of the circuit may be weighted, i.e. placed in a direct neighbourhood. In addition, macros may be placed by hand. Routing occurs in two steps -- global and local routing. During the global routing the potential distribution to the routing channels is decided. If the capacity of a channel is too small, alternative methods may be employed (i.e. subway macros). The goal is minimum resistance of all wires. Critical potentials can be weighted respectively and given routing priority. The routing process functions iteratively until a satisfactory solution is reached. The capacitors and resistances which occur at the connection of the macros are considered during the dynamic simulation. During local routing the connections are made between the macros within a row. Because of the limited number of wires in a channel, complete employment of the capacity is not possible. The amount of use that macros get depends on the type of network. In general, 80% of cells can be used.
Microprocessors and Microsystems
Update Dynamic logic simulation Following routing for each macro the load capacitors are known and the propagation delay times of all macros can be determined. Thus premises are created for valuing the logical behaviour of the circuit. Two methods are used to reduce the expense of estimating the parameters of the circuit from the layout. Uncritical paths are premised to change all signals at the inputs of a macro simultaneously, and the whole propagation delay of the output signal is attributed to the delay caused by the load of the macro. For critical paths, the delay of the output signal of a macro is computed by means of an electrical simulation and the individual signal changes at the input of this macro must be considered. In practice a combination of both techniques is used.
Test pattern generation The LSSD technique must be used for U5200/U5300 circuits. A structural test is possible in this way. The test checks the coincidence between the circuit and the logical description, allowing the vendor to guarantee the integrity of the circuit in silicon. The test patterns for the LSSD test are generated automatically by using the logical description of the circuit. The additional parts of the flipflops necessary for the LSSD test are performed on the master chip. Statements about the dynamic behaviour cannot be made in this way. Therefore the circuits must be checked by an additional functional test.
clock signals is restricted to 16 if chips are to be tested in this way. The maximum clock rate is about 50 MHz, and depends on the complexity of the network. The system U1600 is completed by the CAD system ENSIC.
Hardware components
Standard cell catalogue The cell catalogue contains all elements available to the designer of a standard cell circuit. It consists of about 100 cells including elements with special features for the LSSD test. The catalogue elements can be divided in several groups.
• Combinatorical gates: NAND, NOR, EXOR, EXAND, inverter, transmission gates, etc. • Flip-flops: RS(without clock input), D, T, JK with preset and clear inputs by choice (standard and LSSD), with enable inputs. • Complex gates: half adder, full adder. • Interface units: input, output and bidirectional stages with two- or three-state features or pull-up and pulldown transistors by choice for CMOS and TTL levels. In addition the catalogue offers information about the input capacitance and the maximum output load which can be driven. Typical values for the input capacitance are 0.1-0.3 pF and for the maximal output load, 6-12 pF. By using the maximum output load, raising times of about I 0 ns can be guaranteed. This corresponds to a clock rate of 25 MHz.
VLSl STANDARD CELL SYSTEM U 1 6 0 0
RAM and ROM blocks General description The standard cell system U160011' 12 is based on a 1.5 pm CMOS technology with two metallization layers. By using about I00 different standard cells, circuits with a complexity of about 100k transistors can be designed. The system makes it possible to apply RAM, ROM and PLA structures. The maximum attainable complexity is, for RAM, 16 kbit, ROM 128 kbit, and PLA 20k programming points. Seven different chip sizes between 4mm x 4ram and 9 mm x 9mm are possible. Structural test may be performed by means of the LSSD method. The number of
Table 5.
RAM unit features
Memory capacity (kbit)
Area ( m m x mm)
Access time (ns)
0.25 0.5 1.0 4.0 8.0 16.0
0.45 0.75 1.5 3.0 5.5 10.0
11 12 13 14 16 20
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The control of the adequate function block generator is through a special call in the logic description. A RAM or ROM unit with address and control inputs as well as data lines is generated automatically. If the circuit is to be tested by the LSSD method, the appropriate features (i.e. clock synchronizing) must be considered. During the design process the essential dynamic and geometrical parameters can be displayed by a special command. Tables 5 and 6 show the used chip size and access times (simulation times) for different RAM and ROM blocks.
Circuit interfaces The layout of the output units is such that they can drive two TTL loads (static) and 50 pF at 25 MHz (dynamic). The user can choose packages with 28 to 124 pins, depending on the chip size and the pin demand.
ENSIC CAD system
Components The components of the Ensic CAD system and their interaction are shown in Figure 4. The designer must prepare the following input information.
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Update Table 6.
ROM unit features
Memory capacity (kbit)
Area (mm X mm)
Access time Ins)
0.5 1.0 4.0 8.0 16.0 32.0 64.0 128.0
0.14 0.2 0.4 0.6 0.9 1.6 2.6 4.5
22 24 30 34 40 48 60 75
i
1
IC DESCRIPTION
I TESTPArTERNI
IC ANALYSIS
el) OUASIDYNAMICLOGIC SIHULATION I2)
,1
I21
BLOCK PLACEHENT
• A complete description of the circuit at the logical level in the net description language NBS84. • Data files for RAM, ROM and PLA units (if used). • A pattern for the functional simulation of the circuit. • The arrangement of the circuit pins at the edge of the chip
GLOBAL ROUTING
The individual design steps are executed either automatically or through a dialogue. After successful simulation the CAD system generates a symbolic layout which is independent of process technology and associated design rules. Then the symbolic layout is converted to a technological layout. The design system also generates the test pattern for the structural test if the design of the circuit is intended to make use of the LSSD method. The called tasks are solved through the interaction of dialogue support, circuit description, logical simulation, block placement, block routing and generation of the function blocks. The typical iteration loops of the design process are represented in Figure 4. The individual loops are:
FUNCTIONAL BLOCKS
• Correction of the circuit description to amend syntactical errors, the violation of design restrictions (e.g. LSSD restrictions), or inadmissible circuit structure. • Correction of the circuit description or simulation pattern because of errors during the simulation. • Interactive modification of the symbol layout (block placement, global routing, placement of standard cells within the functional blocks) if the dynamic behaviour of the circuit is unsatisfactory. • Correction of the circuit description or the simulation pattern because of errors identified duffng the certification simulation.
Design system components Dialogue support. The function schedule control, databank and parts of the user interface are included in the dialogue support. This stores all information about the working stage of the design process and the data store in a special file called the status file. The schedule control ensures the correct order of all design steps. In this way it leads the designer and provides security against errors. The faultless completion of a
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1 GENERATIONOF
1 BLOCK ROUTING
1 COI'IPUTATI ON OF DELAY rIMES
i DYNAMIC LOGIC SIHULATION
141
HI
1
1
GENERATIONOF THE
TESTPATTERNGENERATION
TECHNOLOGICALLAYOUT
Figure 4. ENSICCAD system design step is registered in the status file automatically and allows the activation of the following step. The data banking ensures consistency of all design data and provides the program modules of the individual substeps. These files are essential for the design process and contain the information necessary to reconstruct a circuit to the stage that has been reached in its design. The use of design data extracted from ENSIC is prevented.
Circuit description and quasidynamic simulation. Circuit description must be carried out in the net description language NBS84 and must be hierarchical. The highest level must include all interface units (pin stages), subcircuit Microprocessors and Microsystems
Update calls, and regular structures, such as PLA, RAM and ROM. Some individual standard cells are also allowed on this level. All subcircuits and regular structures are implemented as function blocks in the layout. Signal generators for the simulation must exist at the highest description level. On the level below, the subcircuits must be specified. These descriptions can, again, be hierarchically structured. A circuit may contain a maximum 100 subcircuits, while a subcircuit may not include more than 1 000 standard cells. After the circuit description has been entered by the operating system editor the text is checked for syntactic and semantic errors. It is then converted to a special internal description (network code). Next an analysing module tests the circuit description's compliance with design restrictions (e.g. LSSD method requirements) and the propagation delays of the standard cells used for the circuit are recorded in the circuit description. This module also generates the basic file for the automatic layout generation (the block file). This contains the edge description of all function blocks and a list of all standard cells used in these function blocks. Next the KOSIM simulation is prepared. The simulation pattern and a special simulation control file must be entered before the simulation can begin. The time base for the simulation is 0.1 ns. Subcircuits of the whole description can also be simulated using a special function of ENSIC.
Block placement and rout/ng. If the simulation is successful, the generation of the layout can begin. First the designer must enter the position of each circuit pin; then an automatic block placement is made. This is performed in two steps - - relative placement and absolute placement. The relative placement determines the position of all function blocks in relation to each other. The algorithm used is based on a linear spring force model. The absolute placement ensures that the function blocks do not intersect and optimizes the position of the blocks with a fixed edge description (RAM, ROM, PLA). Using a successive partition, the chip is subdivided such that each block has a frame with the same area of the block. Conflicts are resolved by successive movements of the blocks. Finally the units with a fixed edge description are rotated or mirrored so that wire lengths are minimized. This is also the criterion for the division of the terminals of the function blocks. The ENSIC graphic module allows the designer to optimize the block placement interactively. Global routing consists of determining the connections between all function blocks in this way so that the total routing length is minimized. This CAD module is based on a modified LEE algorithm. Global routing is performed three times with different objectives during the design process. This is necessary because the final edge description of the function blocks remains unknown after placement. The objectives of the three operations are: • global routingforafavourable division of the potentials on the edges of the function blocks;
Vol 74 N o 8 O c t o b e r 1990
• global routing without considering the number of the wires in the routing areas; • global routing: inquiry into a routing considering the number of the wires in the routing areas. Between the second and the third global routing a placement step is made. After the third global routing the channel router generates the routing layout on the basis of a GREEDY algorithm. An interactive handling of the routing by means ofthe graphic module is also possible. Generation of the function blocks. The generators for the regular structures RAM, ROM and PLA produce a technological layout and the analysing module enters the final edge description of these units into the block file. The generator for the function blocks performs a symbolic layout. The row structure placement begins by ordering all cells which have connections to the edge terminals. The other cells are combined in groups, using the hierarchical description of the subcircuit. The cells of a group within such a hierarchy are ordered in a row to minimize total wire length. Two alternatives for ordering the groups in the block layout exist. • All groups are placed in a virtual row and this row is fitted into the block. • The groups are placed in several rows in such awaythat the number of connections that must pass through more than two rows is minimized. This layout can be optimized interactively in the placement steps of the standard cells and routing.
ASIC DESIGN FOR DIGITAL SOUND BROADCASTING System concept For the past 25 years the transmission quality of VHF sound broadcasting has kept pace with sound storage technology (such as discs and recording tapes). The introduction of digital techniques in the field of recording requires new quality in broadcasting 13-Is. Digital VHF sound broadcasting via satellites meets this challenge and ensures quality as good as compact disc for radio transmission. With an exclusively digital method the transmission of 16 high quality radio programmes via one satellite transponder channel is possible. This technique also allows the coverage area to be enlarged considerably. The overall reception system is shown in Figure 5. A satellite signal with a frequency of about 12GHz is received by a parabolic antenna. The outdoor unit provides preamplification and conversion to a first intermediate frequency of around 1 GHz. Capacity extension, for the distribution of sound broadcasting programs from foreign satellites is possible through the provision of further channels. This concept requires only a low-cost mixer to convert the signal from the first intermediate frequency position to the lower frequency of the special channels (e.g. 118 MHz). Next, the signal is amplified, demodulated and system
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Update O u t d o o r unit
DSCR I
t
Digital p a r t
Figure 5. Reception equipment clock is recovered. The useful signal is exclusively digital (it is a bit stream). The bit stream is structured in a special way. Besides the sound signal, it contains information about station, programme-type and special services. The sound signal is coded as a floating-point word with a mantissa of 14 bit and an exponent of 3 bit. Because the signal may suffer interference on the way from the satellite to the antenna, particular attention must be given to error protection. A combination of error correction and error identification with subsequent interpolation has been proven to be the best approach. The applied 63/44 Bell-code admits the correction of two errors and the identification and interpolation of a further three errors. In the following stage the bit stream is descrambled and synchronized (DSCR, SYNC1, SYNC2). The demultiplexer unit (DMUX) generates control signals for the following processing stages, subject to the channel control. The mantissa of the useful signal and essential information of the exponent (scale factor) is also separated by this unit. The scale factor is processed in the block SCF. If errors appear in the sound signal they are corrected in EC. The interpolation unit carries out two different tasks. First, it converts the floating-point word to fixed-point. Then the incorrect sound signal is interpolated. Interpolation is followed by a D/A conversion operation, one for each channel.
reception quality, energy and space demands, if the digital processing unit is integrated in one or a small number of Its. The function units DSCR, SYNC1, SYNC2, DMUX, SCF, ED, and IP of the digital processing part were realized in nine system U5200 ICs. The digital unit was not integrated in one IC for two reasons. First, the number of elements on the U5200 master chip is insufficient. Second, the system is provided for community installations and all programmes must be offered simultaneously. This means several function blocks are required for error correction or interpolation must be performed for each radio programme. An individual radio unit is made by placing all ICs on a small PCB. This method guarantees a high degree of flexibility. Dudng design, two particular considerations were paramount. First, the upper efficiency limit of the U5200 system was reached at a working frequency of about 5 MHz and second, the ARCHIMEDES simulator didn't allow the simultaneous simulation of several ICs. The first necessitated application of the following constraints to the logic design:
ASIC design using the U5200
The second problem was solved using the KOSIM simulator. Because the circuit description languages for ARCHIMEDES and KOSIM are similar, the expense was small. Only the following steps were necessary:
The development of a satellite tuner for the transmission system described above is only practical with respect to
540
• storage of all I/O signals; • restriction of gate levels between storage elements to between two and four; • minimization of fan-out of the macros by using parallel structures; • application of special combinatorial circuits instead of complex macros with many gate levels.
Microprocessors and Microsystems
Update • modelling of the U5200 macros as subnetworks using KOSIM; • introduction of a clock signal; • modelling of the cooperation of all ASICs; • consideration of further simple differences between the KOSIM and ARCHIMEDES description languages. The design period for each IC was about one month.
Testing the ASlCs The design system allows a complete structural test by the LSSD method. In this way the ASIC producer guarantees the function of all transistors and their connections, subject to the circuit description. The test is static and cannot evaluate the dynamic behaviour of the circuit. For this reason a functional test is necessary. The test equipment has several special features, the most important being that only hexadecimal patterns can be processed. In most cases simulation results are used as input pattern for a functional test. Usually such patterns are not in hexadecimal code. To solve this problem the KOSIM simulator was used to provide results in binary as well as hexadecimal code. The dynamic test concluded without errors, indicating the measures intended to guarantee a working frequency of about 5 MHz had succeeded.
Gate array integration In general, gate arrays can be designed quickly and at low cost. However, the integration of several gate arrays and further subnetworks into a single IC is often advantageous. This is certainly true in the case of gate arrays designed for use in individual reception units for digital sound broadcasting via satellite. The conversion from nine gate arrays to one IC was thus performed, and the following steps carried out: • Conversion of the logical description usingthe elements of the standard cell library. Of particular importance were differences in the flip-flop functions. • Consideration of special features resulting from different technologies. In general, there were no dynamic problems. • Integration of additional functions. • Conversion of the logical description had to take account of circuit testing. One possibility was a logical function design that would allow division of the circuit into several independently testable function blocks. This is possible through the use of additional circuit parts.
CONCLUSIONS The microelectronics industry in the GDR has available modern ASIC systems for digital applications. Many such circuits have been designed in recent years for diverse applications. Efficient CAD systems have also emerged, reducing development times and increasing product quality.
Vol 14 No 8 October 1990
REFERENCES 1 Neugebauer, G 'Durchgaengiges Entwurfssystem fuer ISA-Kundenschaltkreise' MikroelektronikBauelemente-Symp. (1987) pp 260-267 2 Gross, W 'lSACAD-Entwurfssystem fuer Gate Array Schaltkreise' Mikroprozessortechnik Vol 1 No 4 (1987) pp 104-108 3 Weisse, S, Sachs, H-M and Hahn, U 'Autorouter im schaltkreisentwurfssystem ISACAD' Radio Fernsehen Elektronik Vol 37 No 5 (1988) pp 288-292 4 Fischer, W-J et aL 'CMOS-gate-array-system U5200' Nachrichtentechnik, Elektronik Vol 36 No I (1986) pp 21-23 5 Sorst, M, Gieseler, M and Fischer, W-J 'CMOS-gatearray-system U5200' Mikroprozessortechnik Vol 1 No 1 (1987) pp 4-8 6 Benning, K and Buerger, B 'Anwenderspezifische integrierte Schaltungen (ASIC 7) Radio Fernsehen Elelctronik Vol 38 No 7 (1989) pp 433-436 7 Fischer,W-J etal. 'A CMOS gate arraywith configurable static RAM' Proc. 2nd Hungarian Custom Circuits Conf. (1989) pp 29-34 8 Gieseler, M and So,st, M 'Gate-Array-Schaltkreissystem U5300' Mikroeletctronikbauelemente Syrup. (1989) pp 577-597 9 Donath, U, Schwa,z, P and Trappe, P 'Dynamische Logiksimulation auf B i t - - u n d Wortniveau' Tagung Schaltkreisentwurf (1986) pp 218-228 10 Donath, U, Schwarz, P and Trappe, P 'A multi-level simulator for integrated circuit design' Proc. ECCTD '87 (1987) pp 465-470 11 Mossner, B 'VLSI-Standardzellen-Entwurfssystem U1600' TagungSchaltkreisentwurf(1989) pp 16-22 12 Sieron, W-R 'VLSI-Entwuffssystem U1600' Preprints 13. Mikroelektronikbauelemente Syrup. (1989) pp 353-368 13 Suehnel,C 'Design and test of ASICs for digital sound broadcasting' Proc. 2nd Hungarian Custom Circuits Conf. (1989) pp 311-318 14 Treyll, P (Ed) Digitaler Hoerfunk ueber Rundfunksatelliten Informationsbroschuere des Bundesministers fuer Forschung und Technologie, Bonn 15 "Technische Richtlinie ARD/ZDF Nr. 3R1 Digitaler Satelliten-Rundfunk (DSR) Spezifizierung des HoerfunkUebertragungsverfahrens im TV-SAT' Institut fuer Rundfunktechnik, Munich (1984)
Christoph Suehnel was born in the Ore Mountains, GDR in 1947. He receiveda Dipl Ing degree in information en~neering from the Technical University of Dresden, GDR in 1971 and a Dr Ing degreein 1982. From 1971to 1986 he waswith the CentralInstitutefor Cybernetics and Information Processingat the Academy of Sciences of the GDR. In 1987 he movedto the design centre of the Combined Works Radio and Television, but has now returned to the Central Institutefor Cybernetics. His maininterestsareASICsand CAD
systems.
54"1
PRELIMINARY ANNOUNCEMENT
First International C o n f e r e n c e o n Artificial I n t e l l i g e n c e in D e s i g n 25-27June 1991 Royal Museum of Scotland, Edinburgh, UK A new international conference series on artificial intelligence in design has been established to provide a forum for the presentation and discussion of the state-of-the-art and cutting-edge research and development results in design theory and methodology. Design is becoming a major research topic in engineering and architecture. It is the key to economic competitiveness and the fundamental precursor to manufacturing. However, our understanding of design as a process and our ability' to model it are still very limited. This conference series aims to provide an international forum for developments in artificial intelligence in design. Papers will be rigorously refereed by an international board and accepted papers will be published in book form. The conference will be structured to provide adequate time for both presentation and discussion. Papers on the following areas related to artificial intelligence in design will be considered. • • • • •
Representing designs Cognitive models Machine learning Design processes Design creativW
• • • • •
Knowledge representation Knowledge-based systems Integrated environments User interfaces Applications
A Call for Papers will be issued in mid-1990; full papers are d u e 16 November 1990. Conjerence Chair.. J o h n Gero, University of Sydney Vice Chairs.. /K.. Tim Smithers, Edinburgh University Ken MacCallum, Strathclyde University /SA. Barbara Hayes-Rot]h, Stanford University Duv Sriram, MIT Tetsuo Tomiyama, University o f Tokyo ,Japan: France: Khaldoun Zreik, CIMA The conference series is being sponsored by the major international journals Computer-AidedDesign and Knowledge-Based Systems published by Butterworth Scientific Ltd.
For paper submissions, please contact: John Gero, Department of Architectural and Design Science, University of Sydney; NSW 2006, Australia Tel: 61-2-692 2328 Fax: 61-2-692 3031 E-mail: [email protected] john% [email protected]
For registration details and further information, please contact: Helen Hodge or Tom Whiting, Butterworth Scientific Ltd,Westbury House, Bury Street, Guildford, Surrey GU2 5BH, UK Tel: 0483 300966 Fax: 0483 301563 Telex: 859556 SClTEC G
542
Microprocessors and Microsystems
The paper presents the most important systems for ASIC design developed in the GDR. Hardware is available in modem CMOS technologies at several process levels. The design process is supported by state-of-the-art CAD systems. Thesesystems ensure the correct sequence of the design steps and application of design data. In turn they allow for structural test by means of the level-sensitive scan design method. The test-pattems required are generated by using the circuit description. The design process is demonstrated by the design of gate arrays for digital sound broadcasting equipment. micro~systems semicustom design ASICs
The ever increasing integration rate of ICs and the mastering of CMOS technologies, together with the requirement of greater compactness of highly sophisticated system solutions have led to ASICs acquiring great importance. The development of CPU and memory ICs has played a significant role in the GDR for a long time. Much money was spent on such projects but the results were unimportant. This was a consequence of the high requirements in respect of technology and modem design tools and the limited opportunities. At first the design of ASICs played a small role only, although the automation, communication and computer industries provided a large demand. Above all, such chips were needed for electronic control units in tool machines, for computers and in telephone systems. But the planned economy prevented adequate and timely cultivation of this field. The importance of ASICs has been realized quite late. This is recognized by the recent development of specific ASIC systems based on gate arrays and standard cells in CMOS and bipolar technologies. First, an analogue gate array (ISA)1 in 12Ltechnology was Central Institutefor Cyberneticsand Information Processes,Haeckelstr. 20, 8027 Dresden,GDR This paper is the first in an occasionalseriesthat will surveythe stateof chip designtechnologyin the emergingeasternbloc countriesand other developing nations Paperreceived:16 March 1990. Revised:29 June 1990
developed. This system offers four different master chips with various numbers of bipolar transistors, resistances and capacitances. Later the ISA system was completed by a master chip for digital use. Simultaneously, a CMOS standard cell system (U1500) in a 4pro technology was developed. The design support for these systems was poor. Layout was by hand, using simple graphic editors. For functional verification electrical and logical simulators existed. The4nput of the circuitry was achieved by a net list description. Because the layout was not generated using the circuit description the verification of the layout played an important role. A well-known method for this step works through recognition of the transistor model of the circuit from the graphical layout and subsequent simulation. However, this method is applicable up to a certain complexity only. Later, design support for the ISA system was improved 2, 3 and new semicustom systems in CMOS technologies were developed. These systems are presented here. The development of state-of-the-art design systems did not, however, lead to the solution of the ASIC problem in the GDR. ASICs could now be designed, but the fabrication conditions were poor. Only a small number of the chips required could be produced and the quality and reliability of these ASICs was low. In addition, production costs were high -- about eight to ten times higher than in the West. The same was true of design costs. Design and production were uneconomical. Under the new political and economic conditions microelectronics cannot be supported by the government in the same way as before. Therefore a situation exists where a large number of specialists are able to design microelectronic chips but no foundry in the GDR can produce them. Another aspect is the isolation of the design engineers in the GDR in the past. Because of the embargo on modem computers, design tools and semiconductor technologies, the design work took place under rigid security restrictions. Contacts with foreign design centres, foundries and research institutes were not allowed. But high performance is only possible with international cooperation in all fields. It is hoped that now the blockade can be ended and microelectronics in the GDR will receive a fresh impetus.
0141-9331/90/08531-11 © 1990 ButtenNorth-Heinemann Ltd
Vol 14 No 8 October 1990
531
Update GATE ARRAY SYSTEM U 5 2 0 0
• a pad and input protection; • a converter for the input level and a driving unit; • an output unit with facility for the test case.
General description The gate array U52004's is based on a 4/Jm CMOS technology with one metal layer and two polysilicon layers. One silicon layer, the metal layer and the contacts between these two layers are used for the application specific programming of the master. The main features of the system are summarized in Table 1. The U5200 uses the level-sensitive scan design (LSSD) test method. For this procedure information storage is possible in master-slave flip-flops only. Therefore this system uses a static CMOS logic without transmission gates. The parameters of the transistors were optimized for macros with two inputs (i.e. NAND2, NOR2). Typical propagation delay times for NAND and NOR gates are given in Table 2. The gates and flip-flops are arranged in rows on the master chip. Two gate rows alternate with one flip-flop row. The flip-flops are led out for the LSSD test method. This means they are master-slave flip-flops possessing both a work slave and a 'shift slave'. The shift slave is used for test (shift mode). In the shift mode all shift slaves are decoupled from the master. They build a shift register and through the shift input any sequence of 0 and 1 can be written to this shift register. Switching to work or shift mode takes place by a mode control signal. The CAD system ARCHIMEDES completes the U5200 system.
Interface system The pin units available to the designer are built up in the same way. They comprise
Table 1. Main features of the U5200 Chip area Gates Combinatorial gates Master-slave flip-flops Interface units System service pins Ground/voltage pins Total pin count Propagation delay (NAND2)
Table 2.
Clock system All flip-flops are supplied by the system clock and the user is thus restricted to synchronous circuits. Manipulations of the system clock are not possible. The clock path runs from the input-level converter via the drivers of the clock distribution to the 'row drivers'. The clock path for the row drivers contains a polysilicon connection between rows 3 and 4. This causes a time difference between the clock signals for the flip-flop rows 1 to 3 and 4 to 6 (clock skew) with consequences for the upper limit of the clock rate. The maximum clock rate (FFMAX) of a complete routed gate array is restricted by factors other than the clock skew (tSW). These include • the SET UP time of the flip-flops (tSU); • the minimum time for the clock low phase of the individual flip-flops (1/2fMAX); • the propagation delay of the longest combinatorial part (tLK); • the time during which additional inputs are possible (tlNP). Only the last two may be influenced by the designer. The following formula is valid for fTMAX 1/fTMAX = 2tSW + tlNP + tLK + tSK + 1/2fMAX
7.4 mm x 7.4 mm 3000 1020 102 52 7 5 64 5 ns
U5200 delay times
Macro
tdel LH/ns
tdel H L/ns
NAND2 NOR2 NAND3 NOR3 NAND4 NOR4
6.1 9.3 6.7 15.4 7.3 21.0
5.0 4.1 10.3 4.2 13.6 4.4
532
The designer determines the function of the interface units (input, output and bidirectional units) by the routing. The output units possess a special service for testing. This part is routed by the system automatically and the designer cannot influence this routing. This testing service enables the electrical parameters to be caught quickly and allows in-circuit test of the IC's on a PCB.
The upper border for fTMAX seems to be 5 MHz.
GATE ARRAY SYSTEM U 5 3 0 0 General description The basis for the development of this gate array was the U52OO, although U53OO6-8 was designed at a higher process level. Based on a 1.5 pm CMOS technology with two metal layers and a polysilicon layer, the &SIC is made by programming the master in the metal 1, metal 2 layers and the contacts between these layers. The system U53OO contains the masters U5301, U5302 and U5303. Their characteristic features are shown in Table 3. All the masters of this gate array are structured in streets, i.e. rows of gate cells alternating with rows of flipflop cells. The interface stages are situated around the chip. The U5302 includes a RAM memory as a speciality. The design of ASICs by this system is performed by the CAD system ARCHIMEDES. The application of the LSSD
Microprocessors and Microsystems
.Update Table 3.
Main features of the U5300 family
Chip area (mm x ram) Pins Clocks (for LSSD) Flip-flops Gates RAM capacity (kbit) Transistors Propagation delay (NAND2, fanout = 2) Max clock rate (MHz)
U5301
U5302
U5303
6.98 x 7.04 124 2 360 3840 40 000
6.98 X 7.04 124 2 200 2640 4.5 70 000
4.32 x 4.24 68 2 120 1200 13 000
0.8... 0.9 >40
0.8... 0.9 >30
0.8... 0.9 >60
technique for the design is essential. In this way the CAD system generates test patterns for the structural test automatically.
G~G4 B!
B~
U 5 3 0 0 master units Gate cells The basic element of the gate array is a cell consisting of four p-channel and four n-channel transistors. The gates of the transistors are connected pairwise (see Figure 1). The p-channel transistors are located under the wiring channels. The power supply of the cells is decided independent of the designer and performed with the routing of the macros.
N341~
N1D y
Flip-flop cells The network of the basic flip-flop is shown in Figure 2. The flip-flop consists of the master (DFF1), the work slave (DFF2) and the shift slave (DFF3). The shift slave is connected directly to the master. The work slave is coupled by a transfer gate of the test mode control. The flip-flop functions in two modes, work mode and test (or shift) mode. In work mode the signal at the input D is stored in the master DFF1 during the low phase of the clock cycle. The slaves DFF2 and DFF3 store the last information. During the high phase the master holds the written information. The work slave reacts according to the mode control signal MT: • MT low (work mode). The work slave performs the same function as the shift slave. Both elements receive the information of the master. • MT high (shift mode). The master input is coupled via the transfer gate TC1 to the input QSI of the basic flipflop. The shift slave accepts the information from the master and the work slave stores the state received during the last work mode. The output QSO is connected with the input QSI of the following flip-flop. In this way a shift register is built which consists of all flip-flops used by the designer. This shift register can be loaded via a special pin.
Vol 14 N o 8 October 1990
It
P1.-~
Figure 7.
'-tr
Basic U5300 cell
By completing the basic flip-flop with configurable input logic, several types of flip-flops can be performed. The network of the configurable input logic is shown in Figure 3. It consists of the networks SL1 and SL2, the transfer gates TG5 and TG6 and two inverters. By this method the maximum attainable clock frequency can be increased in comparison with the system U5200. Interface units The interface unit is layed out to allow the build up of a bidirectional stage. Input or output stages may also be performed by a special configuration. The input stages comprise
533
Update TP I ICC
rP
rAKTI~
DFF3 MTEz)
Mr~
TP I
TP
Q$l ~
S DFF1 Figure 2.
Basic U5300 flip-flop
• input protection circuitn/; • input-level converter; • master-slave flip-flop and driver unit. The output stages are configurable as • three-state, push-pull output; • open drain output stage with output enable control; • two-state push-pull output. The power supply and clock signal routing are independent of the designer. A test service function of the interface units enables the in-circuit test of the ASIC on a PCB. R A M unit
The master U5302 contains a RAM unit with a capacity of 4.5 kbit. This block consists of eight memory parts each with 64 x 9 bit. Each part has six address inputs, a chip enable input, a write enable input and nine inputs and outputs for data. All terminals for address, data and control signals are coupled by master-slave flip-flops to the gate array environment. Therefore the memory block functions synchronously for the designer. The input information may change during each clock phase. The basic RAM cell consists of six transistors. The precharge unit, record amplifier, and row and column decoders are performed by conventional circuit techniques.
534
The gate array enables unidirectional data ports only. Therefore a data line control switches the data flow in respect to the write enable signal either from the data input flip-flop to the data line or from the data line to the data output flip-flop. The output control allows information exchange at all data output flip-flops only if the preceding cycle was a read cycle.
U5300
macro library
Hardware macros
The system U5300 contains 69 combinatorial macros with a complexity of one to nine gate equivalents. All combinatorial gates of the U5200 were converted for the U5300. By an appropriate configuration of the input logic of the flip-flop, six different flip-flop types can be performed: a JK flip-flop • T flip-flop • D flip-flop
• D flip-flop without clear and preset function • D flip-flop with an enable input • D flip-flop with an input multiplexer for switching two
sources
Microprocessors and Microsystems
Update
rt ,,
SL1
TG5
1
I GFF
O
J"D s.=
oL.~
ON
as~ TF
OSOl~
SL2
TG6
z
°
Figure 3.
JK flip-flop
Two kinds of interface stages exist, one for TTL signal levels and the other for CMOS signal levels. The following interface macros can be generated by configuration of the basic interface cell: • •
• • • • •
~
input stage with D flip-flop asynchronous input stage asynchronous input stage with double-driver capacity two-state output stage three-state output stage open-drain output stage bidirectional stages as combinations between the input and three-state output stages
The results for the connection of an input and an output stage loaded with a capacity of 100 pF and a TTL load are shown. Simulation results are divided into typical and worst-case times. Where fan out is 3, 0.03 pF load capacity is assumed, originating from the wiring.
A R C H I M E D E S C A D system
ARCHIMEDES is a universal CAD system for the design of gate arrays. It enables a general design from the input of Table 4.
Dynamic parameters
Software macros Software macros are aids for the design engineer. They are formulated in the net description language NBS84 and are handled by the design system as subcircuits. Software macros can be defined by the designer. The system U5300 offers macros for such applications as arithmetic circuitry.
Gate
Fan-out
Measured value ns
Simul. value ns Typ. WC
NAND2
1 3 1 3 1 3 1 3
0.63 1.04 1.20 1.81 0.57 1.10 1.40 2.15 11.9
0.62 0.97 1.43 1.95 0.62 0.97 1.38 1.91
NAND4 NOR2
Dynamic parameters
Table 4 shows a collection of simulation results and measuring values of propagation delay times for NAND and NOR macros. The fan out is one or three in each case.
Vol 14 No 8 October 1990
NOR4 I/O
0.79 1.39 1.73 2.60 0.79 1.41 1.74 2.69
535
Update
_
the network description up to the generation of the data for mask making, including the generation of the test pattern for the structural LSSD test. The design process proceeds as follows. • Input of the network description and quasidynamic simulation • Placement and routing • Dynamic simulation • Test pattern generation • Data output for mask making
Network and quasidynamic simulation Input of the network description takes place in a special dialect of the net description language NBS84. This language enables a hierarchical structure of the network, i.e. the functional structure of a logic plan is reflected in its description. The basic elements of the description are the hardware macros (fixed function elements). All networks must be attributed to these elements. The hardware macros are contained in a special library and described by their logical and electrical behaviour as well as their cell layout. Both the simulator and the placement and routing modules refer to the information in this library. Software and complex macros may be used in addition to the hardware macros in the circuit description. Software macros are tested subcircuits offered by the gate array system vendor, and are contained in a software macro library. Complex macros are defined by the circuit designer. They are private software macros. By using software and complex macros the circuit description will be more clear. In preparing the simulation, the description of the circuit is checked syntactically and semantically. Next the hierarchy of the description is resolved, i.e. all subnetworks are traced back to the hardware macros. A check of the circuit is then carried out and consideration of electrical and logical design rules is tested. This procedure searches open inputs and outputs and feedbacks in combinatorial parts (forbidden because of the use of the LSSD method). Besides a correct circuit description the simulation requires appropriate simulation pattern. This pattern must be entered by hand. An appropriate description makes the recording easy. The quasidynamic logic simulation must solve the following essential tasks: • verification of the logic function of the circuit; • determination of the maximal applicable clock frequency; • localization of critical signal paths. The simulator employed is KOSIM9' 10. It uses behaviour models of the hardware macros consisting of a logic part without any delay and a propagation delay part. The simulator acknowledges four types of signal level: low (L), high (H), unknown (X) and high-impedance (Z). The delay times depend on the load and the direction of the signal
536
change at the output. The simulator works with worstcase conditions of the circuit model. The simulator kernel functions on the event principle. At a given moment only those elements which experience a signal change at that moment of the circuit are considered for the simulation. By the application of the event principle the program Working time is directly proportional to the activity of the circuit. The simulator offers two kinds of simulation: • simulation of the transient during a variable clock period; • simulation ofthe transient during a fixed clock period. In the first case the maximum transient period is determined automatically. This is a measure for the minimum clock period (high phase of the clock signal), by means of which the maximum possible clock frequency can be estimated. In the last case the simulator works up to the clock edge (high/low change). A test simulation is then performed automatically. In this way subsequent signal changes at the input of the flip-flops can be recognized. The simulator can be controlled by commands in the following branches: • initialization of the design system and the circuit, i.e. preseting of flip-flops, signals, clocks and times, clearing of values, arranging input pattern to circuit inputs; • control of the simulation (start, interrupt, continue, finish, set break points, select the mode of operation); • simulation protocol; • analysis of the circuitry; • service output.
Placement and routing If the logical function of the circuit is verified, the generation of the layout can begin. The placement of the interface units (pins) is a prerequisite. After entering this information the placement and routing of the macros of the circuit is carried out automatically. Some parts of the circuit may be weighted, i.e. placed in a direct neighbourhood. In addition, macros may be placed by hand. Routing occurs in two steps -- global and local routing. During the global routing the potential distribution to the routing channels is decided. If the capacity of a channel is too small, alternative methods may be employed (i.e. subway macros). The goal is minimum resistance of all wires. Critical potentials can be weighted respectively and given routing priority. The routing process functions iteratively until a satisfactory solution is reached. The capacitors and resistances which occur at the connection of the macros are considered during the dynamic simulation. During local routing the connections are made between the macros within a row. Because of the limited number of wires in a channel, complete employment of the capacity is not possible. The amount of use that macros get depends on the type of network. In general, 80% of cells can be used.
Microprocessors and Microsystems
Update Dynamic logic simulation Following routing for each macro the load capacitors are known and the propagation delay times of all macros can be determined. Thus premises are created for valuing the logical behaviour of the circuit. Two methods are used to reduce the expense of estimating the parameters of the circuit from the layout. Uncritical paths are premised to change all signals at the inputs of a macro simultaneously, and the whole propagation delay of the output signal is attributed to the delay caused by the load of the macro. For critical paths, the delay of the output signal of a macro is computed by means of an electrical simulation and the individual signal changes at the input of this macro must be considered. In practice a combination of both techniques is used.
Test pattern generation The LSSD technique must be used for U5200/U5300 circuits. A structural test is possible in this way. The test checks the coincidence between the circuit and the logical description, allowing the vendor to guarantee the integrity of the circuit in silicon. The test patterns for the LSSD test are generated automatically by using the logical description of the circuit. The additional parts of the flipflops necessary for the LSSD test are performed on the master chip. Statements about the dynamic behaviour cannot be made in this way. Therefore the circuits must be checked by an additional functional test.
clock signals is restricted to 16 if chips are to be tested in this way. The maximum clock rate is about 50 MHz, and depends on the complexity of the network. The system U1600 is completed by the CAD system ENSIC.
Hardware components
Standard cell catalogue The cell catalogue contains all elements available to the designer of a standard cell circuit. It consists of about 100 cells including elements with special features for the LSSD test. The catalogue elements can be divided in several groups.
• Combinatorical gates: NAND, NOR, EXOR, EXAND, inverter, transmission gates, etc. • Flip-flops: RS(without clock input), D, T, JK with preset and clear inputs by choice (standard and LSSD), with enable inputs. • Complex gates: half adder, full adder. • Interface units: input, output and bidirectional stages with two- or three-state features or pull-up and pulldown transistors by choice for CMOS and TTL levels. In addition the catalogue offers information about the input capacitance and the maximum output load which can be driven. Typical values for the input capacitance are 0.1-0.3 pF and for the maximal output load, 6-12 pF. By using the maximum output load, raising times of about I 0 ns can be guaranteed. This corresponds to a clock rate of 25 MHz.
VLSl STANDARD CELL SYSTEM U 1 6 0 0
RAM and ROM blocks General description The standard cell system U160011' 12 is based on a 1.5 pm CMOS technology with two metallization layers. By using about I00 different standard cells, circuits with a complexity of about 100k transistors can be designed. The system makes it possible to apply RAM, ROM and PLA structures. The maximum attainable complexity is, for RAM, 16 kbit, ROM 128 kbit, and PLA 20k programming points. Seven different chip sizes between 4mm x 4ram and 9 mm x 9mm are possible. Structural test may be performed by means of the LSSD method. The number of
Table 5.
RAM unit features
Memory capacity (kbit)
Area ( m m x mm)
Access time (ns)
0.25 0.5 1.0 4.0 8.0 16.0
0.45 0.75 1.5 3.0 5.5 10.0
11 12 13 14 16 20
Vol 74 No 8 October "/990
The control of the adequate function block generator is through a special call in the logic description. A RAM or ROM unit with address and control inputs as well as data lines is generated automatically. If the circuit is to be tested by the LSSD method, the appropriate features (i.e. clock synchronizing) must be considered. During the design process the essential dynamic and geometrical parameters can be displayed by a special command. Tables 5 and 6 show the used chip size and access times (simulation times) for different RAM and ROM blocks.
Circuit interfaces The layout of the output units is such that they can drive two TTL loads (static) and 50 pF at 25 MHz (dynamic). The user can choose packages with 28 to 124 pins, depending on the chip size and the pin demand.
ENSIC CAD system
Components The components of the Ensic CAD system and their interaction are shown in Figure 4. The designer must prepare the following input information.
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Update Table 6.
ROM unit features
Memory capacity (kbit)
Area (mm X mm)
Access time Ins)
0.5 1.0 4.0 8.0 16.0 32.0 64.0 128.0
0.14 0.2 0.4 0.6 0.9 1.6 2.6 4.5
22 24 30 34 40 48 60 75
i
1
IC DESCRIPTION
I TESTPArTERNI
IC ANALYSIS
el) OUASIDYNAMICLOGIC SIHULATION I2)
,1
I21
BLOCK PLACEHENT
• A complete description of the circuit at the logical level in the net description language NBS84. • Data files for RAM, ROM and PLA units (if used). • A pattern for the functional simulation of the circuit. • The arrangement of the circuit pins at the edge of the chip
GLOBAL ROUTING
The individual design steps are executed either automatically or through a dialogue. After successful simulation the CAD system generates a symbolic layout which is independent of process technology and associated design rules. Then the symbolic layout is converted to a technological layout. The design system also generates the test pattern for the structural test if the design of the circuit is intended to make use of the LSSD method. The called tasks are solved through the interaction of dialogue support, circuit description, logical simulation, block placement, block routing and generation of the function blocks. The typical iteration loops of the design process are represented in Figure 4. The individual loops are:
FUNCTIONAL BLOCKS
• Correction of the circuit description to amend syntactical errors, the violation of design restrictions (e.g. LSSD restrictions), or inadmissible circuit structure. • Correction of the circuit description or simulation pattern because of errors during the simulation. • Interactive modification of the symbol layout (block placement, global routing, placement of standard cells within the functional blocks) if the dynamic behaviour of the circuit is unsatisfactory. • Correction of the circuit description or the simulation pattern because of errors identified duffng the certification simulation.
Design system components Dialogue support. The function schedule control, databank and parts of the user interface are included in the dialogue support. This stores all information about the working stage of the design process and the data store in a special file called the status file. The schedule control ensures the correct order of all design steps. In this way it leads the designer and provides security against errors. The faultless completion of a
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1 GENERATIONOF
1 BLOCK ROUTING
1 COI'IPUTATI ON OF DELAY rIMES
i DYNAMIC LOGIC SIHULATION
141
HI
1
1
GENERATIONOF THE
TESTPATTERNGENERATION
TECHNOLOGICALLAYOUT
Figure 4. ENSICCAD system design step is registered in the status file automatically and allows the activation of the following step. The data banking ensures consistency of all design data and provides the program modules of the individual substeps. These files are essential for the design process and contain the information necessary to reconstruct a circuit to the stage that has been reached in its design. The use of design data extracted from ENSIC is prevented.
Circuit description and quasidynamic simulation. Circuit description must be carried out in the net description language NBS84 and must be hierarchical. The highest level must include all interface units (pin stages), subcircuit Microprocessors and Microsystems
Update calls, and regular structures, such as PLA, RAM and ROM. Some individual standard cells are also allowed on this level. All subcircuits and regular structures are implemented as function blocks in the layout. Signal generators for the simulation must exist at the highest description level. On the level below, the subcircuits must be specified. These descriptions can, again, be hierarchically structured. A circuit may contain a maximum 100 subcircuits, while a subcircuit may not include more than 1 000 standard cells. After the circuit description has been entered by the operating system editor the text is checked for syntactic and semantic errors. It is then converted to a special internal description (network code). Next an analysing module tests the circuit description's compliance with design restrictions (e.g. LSSD method requirements) and the propagation delays of the standard cells used for the circuit are recorded in the circuit description. This module also generates the basic file for the automatic layout generation (the block file). This contains the edge description of all function blocks and a list of all standard cells used in these function blocks. Next the KOSIM simulation is prepared. The simulation pattern and a special simulation control file must be entered before the simulation can begin. The time base for the simulation is 0.1 ns. Subcircuits of the whole description can also be simulated using a special function of ENSIC.
Block placement and rout/ng. If the simulation is successful, the generation of the layout can begin. First the designer must enter the position of each circuit pin; then an automatic block placement is made. This is performed in two steps - - relative placement and absolute placement. The relative placement determines the position of all function blocks in relation to each other. The algorithm used is based on a linear spring force model. The absolute placement ensures that the function blocks do not intersect and optimizes the position of the blocks with a fixed edge description (RAM, ROM, PLA). Using a successive partition, the chip is subdivided such that each block has a frame with the same area of the block. Conflicts are resolved by successive movements of the blocks. Finally the units with a fixed edge description are rotated or mirrored so that wire lengths are minimized. This is also the criterion for the division of the terminals of the function blocks. The ENSIC graphic module allows the designer to optimize the block placement interactively. Global routing consists of determining the connections between all function blocks in this way so that the total routing length is minimized. This CAD module is based on a modified LEE algorithm. Global routing is performed three times with different objectives during the design process. This is necessary because the final edge description of the function blocks remains unknown after placement. The objectives of the three operations are: • global routingforafavourable division of the potentials on the edges of the function blocks;
Vol 74 N o 8 O c t o b e r 1990
• global routing without considering the number of the wires in the routing areas; • global routing: inquiry into a routing considering the number of the wires in the routing areas. Between the second and the third global routing a placement step is made. After the third global routing the channel router generates the routing layout on the basis of a GREEDY algorithm. An interactive handling of the routing by means ofthe graphic module is also possible. Generation of the function blocks. The generators for the regular structures RAM, ROM and PLA produce a technological layout and the analysing module enters the final edge description of these units into the block file. The generator for the function blocks performs a symbolic layout. The row structure placement begins by ordering all cells which have connections to the edge terminals. The other cells are combined in groups, using the hierarchical description of the subcircuit. The cells of a group within such a hierarchy are ordered in a row to minimize total wire length. Two alternatives for ordering the groups in the block layout exist. • All groups are placed in a virtual row and this row is fitted into the block. • The groups are placed in several rows in such awaythat the number of connections that must pass through more than two rows is minimized. This layout can be optimized interactively in the placement steps of the standard cells and routing.
ASIC DESIGN FOR DIGITAL SOUND BROADCASTING System concept For the past 25 years the transmission quality of VHF sound broadcasting has kept pace with sound storage technology (such as discs and recording tapes). The introduction of digital techniques in the field of recording requires new quality in broadcasting 13-Is. Digital VHF sound broadcasting via satellites meets this challenge and ensures quality as good as compact disc for radio transmission. With an exclusively digital method the transmission of 16 high quality radio programmes via one satellite transponder channel is possible. This technique also allows the coverage area to be enlarged considerably. The overall reception system is shown in Figure 5. A satellite signal with a frequency of about 12GHz is received by a parabolic antenna. The outdoor unit provides preamplification and conversion to a first intermediate frequency of around 1 GHz. Capacity extension, for the distribution of sound broadcasting programs from foreign satellites is possible through the provision of further channels. This concept requires only a low-cost mixer to convert the signal from the first intermediate frequency position to the lower frequency of the special channels (e.g. 118 MHz). Next, the signal is amplified, demodulated and system
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Update O u t d o o r unit
DSCR I
t
Digital p a r t
Figure 5. Reception equipment clock is recovered. The useful signal is exclusively digital (it is a bit stream). The bit stream is structured in a special way. Besides the sound signal, it contains information about station, programme-type and special services. The sound signal is coded as a floating-point word with a mantissa of 14 bit and an exponent of 3 bit. Because the signal may suffer interference on the way from the satellite to the antenna, particular attention must be given to error protection. A combination of error correction and error identification with subsequent interpolation has been proven to be the best approach. The applied 63/44 Bell-code admits the correction of two errors and the identification and interpolation of a further three errors. In the following stage the bit stream is descrambled and synchronized (DSCR, SYNC1, SYNC2). The demultiplexer unit (DMUX) generates control signals for the following processing stages, subject to the channel control. The mantissa of the useful signal and essential information of the exponent (scale factor) is also separated by this unit. The scale factor is processed in the block SCF. If errors appear in the sound signal they are corrected in EC. The interpolation unit carries out two different tasks. First, it converts the floating-point word to fixed-point. Then the incorrect sound signal is interpolated. Interpolation is followed by a D/A conversion operation, one for each channel.
reception quality, energy and space demands, if the digital processing unit is integrated in one or a small number of Its. The function units DSCR, SYNC1, SYNC2, DMUX, SCF, ED, and IP of the digital processing part were realized in nine system U5200 ICs. The digital unit was not integrated in one IC for two reasons. First, the number of elements on the U5200 master chip is insufficient. Second, the system is provided for community installations and all programmes must be offered simultaneously. This means several function blocks are required for error correction or interpolation must be performed for each radio programme. An individual radio unit is made by placing all ICs on a small PCB. This method guarantees a high degree of flexibility. Dudng design, two particular considerations were paramount. First, the upper efficiency limit of the U5200 system was reached at a working frequency of about 5 MHz and second, the ARCHIMEDES simulator didn't allow the simultaneous simulation of several ICs. The first necessitated application of the following constraints to the logic design:
ASIC design using the U5200
The second problem was solved using the KOSIM simulator. Because the circuit description languages for ARCHIMEDES and KOSIM are similar, the expense was small. Only the following steps were necessary:
The development of a satellite tuner for the transmission system described above is only practical with respect to
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• storage of all I/O signals; • restriction of gate levels between storage elements to between two and four; • minimization of fan-out of the macros by using parallel structures; • application of special combinatorial circuits instead of complex macros with many gate levels.
Microprocessors and Microsystems
Update • modelling of the U5200 macros as subnetworks using KOSIM; • introduction of a clock signal; • modelling of the cooperation of all ASICs; • consideration of further simple differences between the KOSIM and ARCHIMEDES description languages. The design period for each IC was about one month.
Testing the ASlCs The design system allows a complete structural test by the LSSD method. In this way the ASIC producer guarantees the function of all transistors and their connections, subject to the circuit description. The test is static and cannot evaluate the dynamic behaviour of the circuit. For this reason a functional test is necessary. The test equipment has several special features, the most important being that only hexadecimal patterns can be processed. In most cases simulation results are used as input pattern for a functional test. Usually such patterns are not in hexadecimal code. To solve this problem the KOSIM simulator was used to provide results in binary as well as hexadecimal code. The dynamic test concluded without errors, indicating the measures intended to guarantee a working frequency of about 5 MHz had succeeded.
Gate array integration In general, gate arrays can be designed quickly and at low cost. However, the integration of several gate arrays and further subnetworks into a single IC is often advantageous. This is certainly true in the case of gate arrays designed for use in individual reception units for digital sound broadcasting via satellite. The conversion from nine gate arrays to one IC was thus performed, and the following steps carried out: • Conversion of the logical description usingthe elements of the standard cell library. Of particular importance were differences in the flip-flop functions. • Consideration of special features resulting from different technologies. In general, there were no dynamic problems. • Integration of additional functions. • Conversion of the logical description had to take account of circuit testing. One possibility was a logical function design that would allow division of the circuit into several independently testable function blocks. This is possible through the use of additional circuit parts.
CONCLUSIONS The microelectronics industry in the GDR has available modern ASIC systems for digital applications. Many such circuits have been designed in recent years for diverse applications. Efficient CAD systems have also emerged, reducing development times and increasing product quality.
Vol 14 No 8 October 1990
REFERENCES 1 Neugebauer, G 'Durchgaengiges Entwurfssystem fuer ISA-Kundenschaltkreise' MikroelektronikBauelemente-Symp. (1987) pp 260-267 2 Gross, W 'lSACAD-Entwurfssystem fuer Gate Array Schaltkreise' Mikroprozessortechnik Vol 1 No 4 (1987) pp 104-108 3 Weisse, S, Sachs, H-M and Hahn, U 'Autorouter im schaltkreisentwurfssystem ISACAD' Radio Fernsehen Elektronik Vol 37 No 5 (1988) pp 288-292 4 Fischer, W-J et aL 'CMOS-gate-array-system U5200' Nachrichtentechnik, Elektronik Vol 36 No I (1986) pp 21-23 5 Sorst, M, Gieseler, M and Fischer, W-J 'CMOS-gatearray-system U5200' Mikroprozessortechnik Vol 1 No 1 (1987) pp 4-8 6 Benning, K and Buerger, B 'Anwenderspezifische integrierte Schaltungen (ASIC 7) Radio Fernsehen Elelctronik Vol 38 No 7 (1989) pp 433-436 7 Fischer,W-J etal. 'A CMOS gate arraywith configurable static RAM' Proc. 2nd Hungarian Custom Circuits Conf. (1989) pp 29-34 8 Gieseler, M and So,st, M 'Gate-Array-Schaltkreissystem U5300' Mikroeletctronikbauelemente Syrup. (1989) pp 577-597 9 Donath, U, Schwa,z, P and Trappe, P 'Dynamische Logiksimulation auf B i t - - u n d Wortniveau' Tagung Schaltkreisentwurf (1986) pp 218-228 10 Donath, U, Schwarz, P and Trappe, P 'A multi-level simulator for integrated circuit design' Proc. ECCTD '87 (1987) pp 465-470 11 Mossner, B 'VLSI-Standardzellen-Entwurfssystem U1600' TagungSchaltkreisentwurf(1989) pp 16-22 12 Sieron, W-R 'VLSI-Entwuffssystem U1600' Preprints 13. Mikroelektronikbauelemente Syrup. (1989) pp 353-368 13 Suehnel,C 'Design and test of ASICs for digital sound broadcasting' Proc. 2nd Hungarian Custom Circuits Conf. (1989) pp 311-318 14 Treyll, P (Ed) Digitaler Hoerfunk ueber Rundfunksatelliten Informationsbroschuere des Bundesministers fuer Forschung und Technologie, Bonn 15 "Technische Richtlinie ARD/ZDF Nr. 3R1 Digitaler Satelliten-Rundfunk (DSR) Spezifizierung des HoerfunkUebertragungsverfahrens im TV-SAT' Institut fuer Rundfunktechnik, Munich (1984)
Christoph Suehnel was born in the Ore Mountains, GDR in 1947. He receiveda Dipl Ing degree in information en~neering from the Technical University of Dresden, GDR in 1971 and a Dr Ing degreein 1982. From 1971to 1986 he waswith the CentralInstitutefor Cybernetics and Information Processingat the Academy of Sciences of the GDR. In 1987 he movedto the design centre of the Combined Works Radio and Television, but has now returned to the Central Institutefor Cybernetics. His maininterestsareASICsand CAD
systems.
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PRELIMINARY ANNOUNCEMENT
First International C o n f e r e n c e o n Artificial I n t e l l i g e n c e in D e s i g n 25-27June 1991 Royal Museum of Scotland, Edinburgh, UK A new international conference series on artificial intelligence in design has been established to provide a forum for the presentation and discussion of the state-of-the-art and cutting-edge research and development results in design theory and methodology. Design is becoming a major research topic in engineering and architecture. It is the key to economic competitiveness and the fundamental precursor to manufacturing. However, our understanding of design as a process and our ability' to model it are still very limited. This conference series aims to provide an international forum for developments in artificial intelligence in design. Papers will be rigorously refereed by an international board and accepted papers will be published in book form. The conference will be structured to provide adequate time for both presentation and discussion. Papers on the following areas related to artificial intelligence in design will be considered. • • • • •
Representing designs Cognitive models Machine learning Design processes Design creativW
• • • • •
Knowledge representation Knowledge-based systems Integrated environments User interfaces Applications
A Call for Papers will be issued in mid-1990; full papers are d u e 16 November 1990. Conjerence Chair.. J o h n Gero, University of Sydney Vice Chairs.. /K.. Tim Smithers, Edinburgh University Ken MacCallum, Strathclyde University /SA. Barbara Hayes-Rot]h, Stanford University Duv Sriram, MIT Tetsuo Tomiyama, University o f Tokyo ,Japan: France: Khaldoun Zreik, CIMA The conference series is being sponsored by the major international journals Computer-AidedDesign and Knowledge-Based Systems published by Butterworth Scientific Ltd.
For paper submissions, please contact: John Gero, Department of Architectural and Design Science, University of Sydney; NSW 2006, Australia Tel: 61-2-692 2328 Fax: 61-2-692 3031 E-mail: [email protected] john% [email protected]
For registration details and further information, please contact: Helen Hodge or Tom Whiting, Butterworth Scientific Ltd,Westbury House, Bury Street, Guildford, Surrey GU2 5BH, UK Tel: 0483 300966 Fax: 0483 301563 Telex: 859556 SClTEC G
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Microprocessors and Microsystems