- Email: [email protected]
Development of plasma etching process for sub-50 nm TaN gate
Thin Solid Films 504 (2006) 140 – 144 www.elsevier.com/locate/tsf
Development of plasma etching process for sub-50 nm TaN gate Vladimir Bliznetsov a,*, Rakesh Kumar a, Lakshmi Kanta Bera a, Loh Wei Yip a, Anyan Du a, Tang Ern Hui b b
a Institute of Microelectronics, 11 Science Park Rd, Singapore Science Park II, Singapore 117685, Singapore Department of Materials Science, National University of Singapore, 10 Science Dr. 4, Singapore 117543 Singapore
Available online 25 October 2005
Abstract TaN has been identified as a possible candidate to replace polysilicon for sub-50 nm gate CMOS transistors. However, TaN gate etching in CD (critical dimensions) range below 100 nm presents a great challenge and not much information is available in this area. Using thin layer of SiO2 as a hard mask, TaN etching was evaluated in DPS (decoupled plasma source) etcher with four gas chemistries: Cl2, Cl2/BCl3/Ar, Cl2/BCl3, and Cl2/ Ar. Due to lesser CD gain and higher selectivity to gate dielectrics, Cl2/Ar was chosen for further optimization by DOE. Based on the analysis of the effects of input parameters on the etch responses, we developed a two-step etch process with sub-50 nm minimal CD, profile close to vertical, and capability to stop on 5 nm HfAlO high-k dielectric. 60-nm gate transistors with TaN-HfAlO gate stack (equivalent oxide thickness of 2.5 nm) were fabricated with reasonably low gate leakage of 10 2 A/cm2 at gate bias of 1 V and absence of polysilicon depletion effect. D 2005 Elsevier B.V. All rights reserved. Keywords: TaN etching; HfAlO; DPS; Plasma etching
1. Introduction TaN is widely evaluated as a metal gate material for sub-50 nm gate CMOS transistors. Stoichiometric TaN on high-k dielectric has midgap work function which is suitable for dual gate FETs with high thermal stability (up to 1000 -C). However, scaling critical dimensions (CD) of CMOS devices below 50 nm poses great challenges both for lithography and etch modules. Since resolution capability of 193 and 248 nm DUV lithography is limited to 80 nm even with introduction of advanced phase shift masks, 50 nm gate patterning should include photoresist (PR) trimming process to narrow lines after lithography. Besides, hard mask (HM) should be used in most cases. However, the most critical step is TaN etching itself due to low volatility of Ta halogenides. Thus, the subject of present study is development of plasma etching processes for sub-50 nm TaN gate. A few works dealt recently with TaN plasma etching [1 –5]. In [1], SF6/SiCl4 chemistry was proposed which enabled to achieve selectivity 50:1 to SiO2 and 100:1 to SiN gate dielectrics. Using PR mask, gate lines of 150 nm CD were * Corresponding author. E-mail address: [email protected] (V. Bliznetsov). 0040-6090/$ - see front matter D 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2005.09.158
demonstrated. In patent [2], the mixture of HBr/Cl2 was claimed for TaN gate etching selectively to SiO2 gate dielectric but no selectivity and etch CD bias data have been provided. In [3], TaN comprised part of multilayer magnetic random access memories, and it was found that UV illumination can result in multiple increase of TaN etch rate in Cl2/Ar inductively coupled plasma (ICP). In [4], it was shown than TaN etching with PR mask using Cl2/BCl3 plasma is applicable to gate patterning in respect to profile controllability. In [5], TaN etching with PR or SiO2 HM using ICP etcher and Cl2 chemistry provided TaN lines of about 110 nm. However, none of the cited works reported performance of TaN etching in sub-100 nm CD range. 2. Experimental For most of etch experiments gate stack on 8-in. wafers was comprised by 10 nm thermal SiO2 followed by 100 nm TaN deposited by reactive sputtering. For device integration, SiO2 gate dielectric was replaced by 5 nm HfAlO deposited by atomic layer chemical vapour deposition (ALCVD). Lithography was performed in Nikon 248-nm DUV step and scan system with phase shift mask using 300 nm DUV PR with organic antireflective coating. Post development CD were 80– 85 nm. In most experiments TaN etching was performed with
V. Bliznetsov et al. / Thin Solid Films 504 (2006) 140 – 144
80 nm SiO2 hard mask (HM) deposited by PECVD. Integrated process of PR trimming and HM etching with final CD 40 –45 nm was performed in Tokyo Electron Ltd. dipole ring magnetron etcher, followed by PR stripping in Mattson ICP reactor. TaN etching was performed in DPS metal etch chamber from Applied Materials with both source (coil) and bias (chuck) power at 13.56 MHz. Etching results were evaluated by scanning and transmission electron microscopes (SEM and TEM). Gate CD measurements were performed in Hitachi CD SEM. TEM analysis was performed in Philips CM 200FEG with EDAX EDX (energy dispersive X-ray) detector and Gatan GIF 200 system at 200 kV. Study of effects of various process parameters and optimization was performed by design of experiment (DOE) using Cornestonei software. 3. Results and discussion 3.1. Screening experiments Initially we evaluated TaN etching with PR mask and found that in Cl2/Ar plasma etch process is accompanied by substantial by-products deposition on sidewalls, and etch CD gain can be as high as 100 nm. Besides, on top of the etched TaN lines, we found heavy fences which were difficult to remove without damaging gate lines itself. By-products deposition was much less in etching with SiO2 HM, therefore, the latter was chosen for subsequent etch process development. Next, we evaluated four gas chemistries: Cl2, Cl2/BCl3, Cl2/ BCl3/Ar, and Cl2/Ar and found that, compared to others, pure Cl2 chemistry gave larger CD gain while Cl2/Ar mixture provided the best results in terms of CD gain and selectivity to SiO2 gate dielectric. Besides, by varying chuck temperature in the range of 45 to 55 -C it was found that at a higher temperature selectivity increases and CD gain decreases which is explained by the low volatility of TaClx etch products.
141
Thus, based on the results of screening experiment we determined for subsequent process optimization mask material, SiO2; gas chemistry, Cl2/Ar; and chuck temperature, 55 -C. 3.2. DOE study of TaN etching in Cl2/Ar chemistry Five variable parameters were chosen for DOE, namely, argon percentage in gas mixture Ar/Cl2, total gas flow rate and pressure, source and bias power. The chuck temperature was maintained at 55 -C. Output process parameters (responses) were the following: TaN etch rate, selectivity TaN/SiO2, sidewall angle and etch CD gain. As a number of variable parameters are relatively high, to minimize the number of experiments we chose a simple linear model with interaction term for source and bias power. In this case Cornestonei D-optimal design requested to run only 12 experiments. However, each experiment was repeated twice. One run, for patterned wafers of TaN with SiO2 hard mask, was performed by endpoint with 3 s of overetching. Overetching was required to offset non-uniformity and reduce footing at the profile bottom. TaN etch rate was calculated based on endpoint time. Second run, for blanket thermal oxide wafers, was performed by time to determine SiO2 etch rate. The results were subjected to regression analysis and the etching model was generated. From the model it was found that, with an increase of total gas flow rate, TaN etch rate slightly goes up but other responses do not change noticeably. Effects of other input process parameters on etching results are presented in Fig. 1. As seen, the etch rate increases dramatically with bias power which can be explained by predominance of ion-assisted etch mechanism over chemical plasma etching due to low volatility of TaCl5 (boiling temperature 239 -C). Much smaller increase of TaN etch rate happens with the increase of source power and gas pressure. Increase of Ar percentage in gas chemistry causes gradual decrease of etch rate due to dilution. TaN/SiO2 selectivity depends mostly on bias power. As bond energy Si-O (799.6 kJ/mol) is higher than that of Ta-N
Fig. 1. TaN etch rate, selectivity TaN/SiO2, CD gain and sidewall slope angle versus process parameters.
142
V. Bliznetsov et al. / Thin Solid Films 504 (2006) 140 – 144
From the above analysis it follows that contradicting requirements of minimal CD gain, steep sidewall and maximal selectivity to SiO2 can be satisfied by two-step process: first step—main etch with bias power of 60– 80 W for minimizing CD gain and keeping straight profile and second step— overetching at 30 W bias for higher selectivity to SiO2. 3.3. Sidewall profile and by-products
Fig. 2. TEM cross-section of TaN gate produced by optimized etching recipe. The insert shows profile after sidewall products removal by 0.5% HF. Numbers 1 – 3 represent points of EDX analysis.
(611 kJ/mol), SiO2 etch rate should decrease more with a decrease of ion energy than the etch rate of TaN. Hence, selectivity TaN/SiO2 decreases with increase of bias power, which controls ion energy. CD gain decreases noticeably with increase of bias power and, in a lesser extent, with a decrease of pressure, an increase of argon percentage and source power. Both increase of bias power and decrease of pressure result in the increase of energy of ions bombarding the surface which, in turn, promotes more effective etching, with less by-products deposited on sidewalls and, in this way reduces etch CD gain. However, at the bias power of 100 W an excessive faceting of HM happens, therefore, preferable range of bias should not be more than 80 W. Interesting is that CD gain also decreases with an increase of source power. This may be the case if etch rate is limited by insufficient delivery of etchant at a low source power resulting in the increased part of the etch products to be generated in a less volatile form of TaClx where x is less than 5. Sidewall angle increases noticeably with an increase of bias power and in a lesser extent with an increase of Ar percentage and decrease of power that, as in the case with CD gain, can be attributed to a decrease of by-product deposition on sidewalls.
Fig. 2 presents TEM cross-section for TaN gate produced by etching with optimized two-step recipe. Sidewall is quite smooth, with the angle of 85.4-. However, noticeable layer of by-products is found on it. The TEM EDX results for point 2 revealed that sidewall by-products are silicon-based (Si content varies from 47.4 to 57.7%) and also contain carbon, oxygen and nitrogen. The results obtained by EDX were confirmed by TEM electron energy loss spectra (EELS) presented in Fig. 3, where panel (a) is zero loss image for the sidewall by-product layer between TaN gate and SiN cover layer; panel (b)is the carbon mapping of the same area (bright contrast in the area of sidewall indicates presence of carbon); panel (c) is the oxygen mapping of the same area (bright contrast indicates presence of oxygen in gate oxide layer, HM layer and sidewall by-product layer); panel (d) is silicon mapping of the same area (presence of Si is indicated by brighter contrast in SiN cover layer, gate dielectric, HM and sidewall layer). Thus, element mapping results show that the sidewall layer has high concentration of C, O and Si. This correlates well with EDX data. However, in our case EDX has a restricted capability to detect Ta. The reason is that two strongest peaks of tantalum—Ta Ma and Ta La are overlapped by peaks of Si and Cu, respectively. The third peak used for Ta identification, Ta Lh, is the weakest and it was not found in the sidewall layer spectrum. Thus, we should not exclude possibility of the presence of insignificant fraction of Ta in sidewall byproducts. In [5], for somewhat different etching conditions, 5.6– 12.7% of Ta was found in sidewall by-products by XPS (X-ray photoelectron spectroscopy). We presume that silicon and most of oxygen in sidewall by-products originated from SiO2 HM and came to sidewall by re-deposition through the chain of plasma events. Carbon and part of oxygen originated from chamber walls which in our experiments were always coated by polymer created by special seasoning procedure. It was found that
Fig. 3. TEM EELS analysis of gate sidewall layer: a—zero loss image, b—carbon mapping, c—oxygen mapping, d—silicon mapping.
V. Bliznetsov et al. / Thin Solid Films 504 (2006) 140 – 144
143
ID (µA/µm)
102 101
W=2.0 µm
100
LG=60nm
VT=1.63 V
10-1 10-2 10-3
SS=151 mV/dec
10-4 10-5 10-6 0.0
0.5
1.0
1.5
2.0
2.5
3.0
VG (V) Fig. 4. TEM of TaN-HfAlO gate stack. Etching stopped at HfAlO layer.
Fig. 6. I d – V g characteristics of the 60 nm n-MOSFET.
sidewall layer thickness was only slightly reduced after a 30 min treatment in a widely used organic based stripper ACT\690C from Air Products. However, sidewall layer was fully removed by 10 s of wet etch in 0.5% HF:H2O (see the insert in Fig. 2).
carrier mobility. The mobility degradation in high-k is believed to be due to the following factors [6]: (a) phonon scattering, (b) coulumbic scattering by interface or near interface charges and (c) poor interface between Si substrate and high-k dielectrics (see intermediate layer between HfAlO and silicon substrate in Fig. 4). Improvement of the drive current requires surface passivation before high-k deposition and suitable high-k dielectric with minimal bulk charges. Fig. 6 shows the I d – V g characteristics of the 60 nm nMOSFET. The off-state drain leakage current at drain bias V d of 0.1 V is 5 pA/Am which is compatible with ITRS requirements. Sub-threshold slope is high in this case due to high well and threshold implant doping, and needs to be further improved by channel implant engineering. The linear threshold voltage (V t) roll-off is shown in Fig. 7. The V t is high due to the presence of charges in high-k dielectric as mentioned above. Good short channel immunity was achieved down to 60 nm.
3.4. Device integration The achieved TaN/SiO2 etch selectivity is not sufficient to stop etching reliably at ultra-thin SiO2 (2.0 nm) and punchthrough into silicon may happen. Metal diffusion through gate oxide is another concern in integration of TaN with SiO2 gate dielectric. To avoid such issues HfAlO high-k gate dielectric was used for device integration instead of SiO2. The physical thickness of HfAlO was 4.7 –5.5 nm with equivalent oxide thickness (EOT) 2.0 –2.5 nm. As selectivity of TaN etching to HfAlO is better than to SiO2, etching process can be stopped properly at gate dielectric (Fig. 4). The n-MOSFETs were fabricated using HfAlO/TaN gate stack. The capacitance – voltage measurement (not shown) revealed no poly depletion effect, as expected, however, the drive current is low compared to conventional poly CMOS device. Fig. 5 shows the I d –V d characteristics of a 60 nm n-MOSFET with HfAlO (EOT = 2.5 nm). The lower drive current is due to the degradation of
200
LG=60 nm
VG-VT =1.5 V
4. Conclusions We developed plasma etching process for TaN gate with SiO2 HM which provides close to vertical profile with CD gain not exceeding 10 nm; the process is capable to stop at 5 nm HfAlO high-k dielectric. Sidewall by-products composition was studied and the method to remove them was identified. Performance of etch process was validated by manufacturing of 2.6
150 2.4
VG-VT =1.14 V 100
2.2
VG-VT =0.78 V 50 VG-VT =0.42 V 0 0.0
VG-VT =0 V 0.2
0.4
0.6
0.8
1.0
VD (V)
Vth (V)
ID (µA/µm)
W=2 µm EOT=2 nm
2.0 1.8 1.6 50
100
150
200
250
300
LG (nm) Fig. 5. I d – V d characteristics of a 60 nm n-MOSFET with gate dielectric HfAlO of 4.7 nm.
Fig. 7. Threshold voltage roll-off for TaN/HfAlO n-MOSFET.
144
V. Bliznetsov et al. / Thin Solid Films 504 (2006) 140 – 144
n-MOSFET transistors with gate length of 60 nm. At the same time problems associated with quality of high-k dielectric and silicon interface were revealed. References [1] H. Shimada, Koichi Maruyama, Jpn. J. Appl. Phys. 43 (2004) 1768. [2] S.I. Yi, S. Nam, K. Huang, P.C. Nallan, US Patent 6638874 B2, publ. 28 Oct. 2003.
[3] H. Cho, K.-P. Lee, K.B. Jung, S.J. Pearton, J. Appl. Phys. 87 (9) (2000) 6397. [4] J. Tonotani, S. Takagi, S. Ohmi, H. Iwai, 205th Meeting of the Electrochem. Soc. Inc., San Antonio, USA, May 9 – 13, 2004, p. 144, (Abstract). [5] W.S. Hwang, J.-H. Chen, W.J. Yoo, V. Bliznetsov, J. Vac. Sci. Technol., A 23 (2005) 964. [6] S. Mathew, L.K. Bera, N. Balasubramanian, M.S. Joo, B.J. Cho, Thin Solid Films 462 – 463 (2004) 11.
Development of plasma etching process for sub-50 nm TaN gate Vladimir Bliznetsov a,*, Rakesh Kumar a, Lakshmi Kanta Bera a, Loh Wei Yip a, Anyan Du a, Tang Ern Hui b b
a Institute of Microelectronics, 11 Science Park Rd, Singapore Science Park II, Singapore 117685, Singapore Department of Materials Science, National University of Singapore, 10 Science Dr. 4, Singapore 117543 Singapore
Available online 25 October 2005
Abstract TaN has been identified as a possible candidate to replace polysilicon for sub-50 nm gate CMOS transistors. However, TaN gate etching in CD (critical dimensions) range below 100 nm presents a great challenge and not much information is available in this area. Using thin layer of SiO2 as a hard mask, TaN etching was evaluated in DPS (decoupled plasma source) etcher with four gas chemistries: Cl2, Cl2/BCl3/Ar, Cl2/BCl3, and Cl2/ Ar. Due to lesser CD gain and higher selectivity to gate dielectrics, Cl2/Ar was chosen for further optimization by DOE. Based on the analysis of the effects of input parameters on the etch responses, we developed a two-step etch process with sub-50 nm minimal CD, profile close to vertical, and capability to stop on 5 nm HfAlO high-k dielectric. 60-nm gate transistors with TaN-HfAlO gate stack (equivalent oxide thickness of 2.5 nm) were fabricated with reasonably low gate leakage of 10 2 A/cm2 at gate bias of 1 V and absence of polysilicon depletion effect. D 2005 Elsevier B.V. All rights reserved. Keywords: TaN etching; HfAlO; DPS; Plasma etching
1. Introduction TaN is widely evaluated as a metal gate material for sub-50 nm gate CMOS transistors. Stoichiometric TaN on high-k dielectric has midgap work function which is suitable for dual gate FETs with high thermal stability (up to 1000 -C). However, scaling critical dimensions (CD) of CMOS devices below 50 nm poses great challenges both for lithography and etch modules. Since resolution capability of 193 and 248 nm DUV lithography is limited to 80 nm even with introduction of advanced phase shift masks, 50 nm gate patterning should include photoresist (PR) trimming process to narrow lines after lithography. Besides, hard mask (HM) should be used in most cases. However, the most critical step is TaN etching itself due to low volatility of Ta halogenides. Thus, the subject of present study is development of plasma etching processes for sub-50 nm TaN gate. A few works dealt recently with TaN plasma etching [1 –5]. In [1], SF6/SiCl4 chemistry was proposed which enabled to achieve selectivity 50:1 to SiO2 and 100:1 to SiN gate dielectrics. Using PR mask, gate lines of 150 nm CD were * Corresponding author. E-mail address: [email protected] (V. Bliznetsov). 0040-6090/$ - see front matter D 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2005.09.158
demonstrated. In patent [2], the mixture of HBr/Cl2 was claimed for TaN gate etching selectively to SiO2 gate dielectric but no selectivity and etch CD bias data have been provided. In [3], TaN comprised part of multilayer magnetic random access memories, and it was found that UV illumination can result in multiple increase of TaN etch rate in Cl2/Ar inductively coupled plasma (ICP). In [4], it was shown than TaN etching with PR mask using Cl2/BCl3 plasma is applicable to gate patterning in respect to profile controllability. In [5], TaN etching with PR or SiO2 HM using ICP etcher and Cl2 chemistry provided TaN lines of about 110 nm. However, none of the cited works reported performance of TaN etching in sub-100 nm CD range. 2. Experimental For most of etch experiments gate stack on 8-in. wafers was comprised by 10 nm thermal SiO2 followed by 100 nm TaN deposited by reactive sputtering. For device integration, SiO2 gate dielectric was replaced by 5 nm HfAlO deposited by atomic layer chemical vapour deposition (ALCVD). Lithography was performed in Nikon 248-nm DUV step and scan system with phase shift mask using 300 nm DUV PR with organic antireflective coating. Post development CD were 80– 85 nm. In most experiments TaN etching was performed with
V. Bliznetsov et al. / Thin Solid Films 504 (2006) 140 – 144
80 nm SiO2 hard mask (HM) deposited by PECVD. Integrated process of PR trimming and HM etching with final CD 40 –45 nm was performed in Tokyo Electron Ltd. dipole ring magnetron etcher, followed by PR stripping in Mattson ICP reactor. TaN etching was performed in DPS metal etch chamber from Applied Materials with both source (coil) and bias (chuck) power at 13.56 MHz. Etching results were evaluated by scanning and transmission electron microscopes (SEM and TEM). Gate CD measurements were performed in Hitachi CD SEM. TEM analysis was performed in Philips CM 200FEG with EDAX EDX (energy dispersive X-ray) detector and Gatan GIF 200 system at 200 kV. Study of effects of various process parameters and optimization was performed by design of experiment (DOE) using Cornestonei software. 3. Results and discussion 3.1. Screening experiments Initially we evaluated TaN etching with PR mask and found that in Cl2/Ar plasma etch process is accompanied by substantial by-products deposition on sidewalls, and etch CD gain can be as high as 100 nm. Besides, on top of the etched TaN lines, we found heavy fences which were difficult to remove without damaging gate lines itself. By-products deposition was much less in etching with SiO2 HM, therefore, the latter was chosen for subsequent etch process development. Next, we evaluated four gas chemistries: Cl2, Cl2/BCl3, Cl2/ BCl3/Ar, and Cl2/Ar and found that, compared to others, pure Cl2 chemistry gave larger CD gain while Cl2/Ar mixture provided the best results in terms of CD gain and selectivity to SiO2 gate dielectric. Besides, by varying chuck temperature in the range of 45 to 55 -C it was found that at a higher temperature selectivity increases and CD gain decreases which is explained by the low volatility of TaClx etch products.
141
Thus, based on the results of screening experiment we determined for subsequent process optimization mask material, SiO2; gas chemistry, Cl2/Ar; and chuck temperature, 55 -C. 3.2. DOE study of TaN etching in Cl2/Ar chemistry Five variable parameters were chosen for DOE, namely, argon percentage in gas mixture Ar/Cl2, total gas flow rate and pressure, source and bias power. The chuck temperature was maintained at 55 -C. Output process parameters (responses) were the following: TaN etch rate, selectivity TaN/SiO2, sidewall angle and etch CD gain. As a number of variable parameters are relatively high, to minimize the number of experiments we chose a simple linear model with interaction term for source and bias power. In this case Cornestonei D-optimal design requested to run only 12 experiments. However, each experiment was repeated twice. One run, for patterned wafers of TaN with SiO2 hard mask, was performed by endpoint with 3 s of overetching. Overetching was required to offset non-uniformity and reduce footing at the profile bottom. TaN etch rate was calculated based on endpoint time. Second run, for blanket thermal oxide wafers, was performed by time to determine SiO2 etch rate. The results were subjected to regression analysis and the etching model was generated. From the model it was found that, with an increase of total gas flow rate, TaN etch rate slightly goes up but other responses do not change noticeably. Effects of other input process parameters on etching results are presented in Fig. 1. As seen, the etch rate increases dramatically with bias power which can be explained by predominance of ion-assisted etch mechanism over chemical plasma etching due to low volatility of TaCl5 (boiling temperature 239 -C). Much smaller increase of TaN etch rate happens with the increase of source power and gas pressure. Increase of Ar percentage in gas chemistry causes gradual decrease of etch rate due to dilution. TaN/SiO2 selectivity depends mostly on bias power. As bond energy Si-O (799.6 kJ/mol) is higher than that of Ta-N
Fig. 1. TaN etch rate, selectivity TaN/SiO2, CD gain and sidewall slope angle versus process parameters.
142
V. Bliznetsov et al. / Thin Solid Films 504 (2006) 140 – 144
From the above analysis it follows that contradicting requirements of minimal CD gain, steep sidewall and maximal selectivity to SiO2 can be satisfied by two-step process: first step—main etch with bias power of 60– 80 W for minimizing CD gain and keeping straight profile and second step— overetching at 30 W bias for higher selectivity to SiO2. 3.3. Sidewall profile and by-products
Fig. 2. TEM cross-section of TaN gate produced by optimized etching recipe. The insert shows profile after sidewall products removal by 0.5% HF. Numbers 1 – 3 represent points of EDX analysis.
(611 kJ/mol), SiO2 etch rate should decrease more with a decrease of ion energy than the etch rate of TaN. Hence, selectivity TaN/SiO2 decreases with increase of bias power, which controls ion energy. CD gain decreases noticeably with increase of bias power and, in a lesser extent, with a decrease of pressure, an increase of argon percentage and source power. Both increase of bias power and decrease of pressure result in the increase of energy of ions bombarding the surface which, in turn, promotes more effective etching, with less by-products deposited on sidewalls and, in this way reduces etch CD gain. However, at the bias power of 100 W an excessive faceting of HM happens, therefore, preferable range of bias should not be more than 80 W. Interesting is that CD gain also decreases with an increase of source power. This may be the case if etch rate is limited by insufficient delivery of etchant at a low source power resulting in the increased part of the etch products to be generated in a less volatile form of TaClx where x is less than 5. Sidewall angle increases noticeably with an increase of bias power and in a lesser extent with an increase of Ar percentage and decrease of power that, as in the case with CD gain, can be attributed to a decrease of by-product deposition on sidewalls.
Fig. 2 presents TEM cross-section for TaN gate produced by etching with optimized two-step recipe. Sidewall is quite smooth, with the angle of 85.4-. However, noticeable layer of by-products is found on it. The TEM EDX results for point 2 revealed that sidewall by-products are silicon-based (Si content varies from 47.4 to 57.7%) and also contain carbon, oxygen and nitrogen. The results obtained by EDX were confirmed by TEM electron energy loss spectra (EELS) presented in Fig. 3, where panel (a) is zero loss image for the sidewall by-product layer between TaN gate and SiN cover layer; panel (b)is the carbon mapping of the same area (bright contrast in the area of sidewall indicates presence of carbon); panel (c) is the oxygen mapping of the same area (bright contrast indicates presence of oxygen in gate oxide layer, HM layer and sidewall by-product layer); panel (d) is silicon mapping of the same area (presence of Si is indicated by brighter contrast in SiN cover layer, gate dielectric, HM and sidewall layer). Thus, element mapping results show that the sidewall layer has high concentration of C, O and Si. This correlates well with EDX data. However, in our case EDX has a restricted capability to detect Ta. The reason is that two strongest peaks of tantalum—Ta Ma and Ta La are overlapped by peaks of Si and Cu, respectively. The third peak used for Ta identification, Ta Lh, is the weakest and it was not found in the sidewall layer spectrum. Thus, we should not exclude possibility of the presence of insignificant fraction of Ta in sidewall byproducts. In [5], for somewhat different etching conditions, 5.6– 12.7% of Ta was found in sidewall by-products by XPS (X-ray photoelectron spectroscopy). We presume that silicon and most of oxygen in sidewall by-products originated from SiO2 HM and came to sidewall by re-deposition through the chain of plasma events. Carbon and part of oxygen originated from chamber walls which in our experiments were always coated by polymer created by special seasoning procedure. It was found that
Fig. 3. TEM EELS analysis of gate sidewall layer: a—zero loss image, b—carbon mapping, c—oxygen mapping, d—silicon mapping.
V. Bliznetsov et al. / Thin Solid Films 504 (2006) 140 – 144
143
ID (µA/µm)
102 101
W=2.0 µm
100
LG=60nm
VT=1.63 V
10-1 10-2 10-3
SS=151 mV/dec
10-4 10-5 10-6 0.0
0.5
1.0
1.5
2.0
2.5
3.0
VG (V) Fig. 4. TEM of TaN-HfAlO gate stack. Etching stopped at HfAlO layer.
Fig. 6. I d – V g characteristics of the 60 nm n-MOSFET.
sidewall layer thickness was only slightly reduced after a 30 min treatment in a widely used organic based stripper ACT\690C from Air Products. However, sidewall layer was fully removed by 10 s of wet etch in 0.5% HF:H2O (see the insert in Fig. 2).
carrier mobility. The mobility degradation in high-k is believed to be due to the following factors [6]: (a) phonon scattering, (b) coulumbic scattering by interface or near interface charges and (c) poor interface between Si substrate and high-k dielectrics (see intermediate layer between HfAlO and silicon substrate in Fig. 4). Improvement of the drive current requires surface passivation before high-k deposition and suitable high-k dielectric with minimal bulk charges. Fig. 6 shows the I d – V g characteristics of the 60 nm nMOSFET. The off-state drain leakage current at drain bias V d of 0.1 V is 5 pA/Am which is compatible with ITRS requirements. Sub-threshold slope is high in this case due to high well and threshold implant doping, and needs to be further improved by channel implant engineering. The linear threshold voltage (V t) roll-off is shown in Fig. 7. The V t is high due to the presence of charges in high-k dielectric as mentioned above. Good short channel immunity was achieved down to 60 nm.
3.4. Device integration The achieved TaN/SiO2 etch selectivity is not sufficient to stop etching reliably at ultra-thin SiO2 (2.0 nm) and punchthrough into silicon may happen. Metal diffusion through gate oxide is another concern in integration of TaN with SiO2 gate dielectric. To avoid such issues HfAlO high-k gate dielectric was used for device integration instead of SiO2. The physical thickness of HfAlO was 4.7 –5.5 nm with equivalent oxide thickness (EOT) 2.0 –2.5 nm. As selectivity of TaN etching to HfAlO is better than to SiO2, etching process can be stopped properly at gate dielectric (Fig. 4). The n-MOSFETs were fabricated using HfAlO/TaN gate stack. The capacitance – voltage measurement (not shown) revealed no poly depletion effect, as expected, however, the drive current is low compared to conventional poly CMOS device. Fig. 5 shows the I d –V d characteristics of a 60 nm n-MOSFET with HfAlO (EOT = 2.5 nm). The lower drive current is due to the degradation of
200
LG=60 nm
VG-VT =1.5 V
4. Conclusions We developed plasma etching process for TaN gate with SiO2 HM which provides close to vertical profile with CD gain not exceeding 10 nm; the process is capable to stop at 5 nm HfAlO high-k dielectric. Sidewall by-products composition was studied and the method to remove them was identified. Performance of etch process was validated by manufacturing of 2.6
150 2.4
VG-VT =1.14 V 100
2.2
VG-VT =0.78 V 50 VG-VT =0.42 V 0 0.0
VG-VT =0 V 0.2
0.4
0.6
0.8
1.0
VD (V)
Vth (V)
ID (µA/µm)
W=2 µm EOT=2 nm
2.0 1.8 1.6 50
100
150
200
250
300
LG (nm) Fig. 5. I d – V d characteristics of a 60 nm n-MOSFET with gate dielectric HfAlO of 4.7 nm.
Fig. 7. Threshold voltage roll-off for TaN/HfAlO n-MOSFET.
144
V. Bliznetsov et al. / Thin Solid Films 504 (2006) 140 – 144
n-MOSFET transistors with gate length of 60 nm. At the same time problems associated with quality of high-k dielectric and silicon interface were revealed. References [1] H. Shimada, Koichi Maruyama, Jpn. J. Appl. Phys. 43 (2004) 1768. [2] S.I. Yi, S. Nam, K. Huang, P.C. Nallan, US Patent 6638874 B2, publ. 28 Oct. 2003.
[3] H. Cho, K.-P. Lee, K.B. Jung, S.J. Pearton, J. Appl. Phys. 87 (9) (2000) 6397. [4] J. Tonotani, S. Takagi, S. Ohmi, H. Iwai, 205th Meeting of the Electrochem. Soc. Inc., San Antonio, USA, May 9 – 13, 2004, p. 144, (Abstract). [5] W.S. Hwang, J.-H. Chen, W.J. Yoo, V. Bliznetsov, J. Vac. Sci. Technol., A 23 (2005) 964. [6] S. Mathew, L.K. Bera, N. Balasubramanian, M.S. Joo, B.J. Cho, Thin Solid Films 462 – 463 (2004) 11.