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Development review of transient recorders with onboard isolation on JET M. Jennison ∗ , B. Alper, S. Dorling, K. Fullard, A. Horton, R. Lucock, C. Perry, P. Thomas, JET EFDA contributors1 Euratom/UKAEA Fusion Association, Culham Science Centre, Abingdon, Oxon OX14 3DB, United Kingdom Available online 6 May 2006
Abstract The JET tokamak is currently using about 7000 transient recorder channels for data acquisition, mainly sampling at 5 kHz but including a few at 1 MHz or higher. Nearly half of the channels are provided by module designs with front ends that are galvanically isolated to over 1000 V. Performing analogue-to-digital conversion before isolation provides many benefits. This paper reviews three such designs that have been commissioned or developed by control and data acquisition systems (CODAS) personnel over the past 10 years and examines the trends. © 2006 Elsevier B.V. All rights reserved. Keywords: Transient recorder; Isolated; ADC; DAQ
1. The advantages and disadvantages of isolation In the early days of JET it was realised that measurement equipment attached to the torus vessel could reach dangerously high voltages due to an earth fault on the poloidal field coils. It was calculated [1] that, to be safe, connections to the vessel should be protected from
∗ Corresponding author. Tel.: +44 1235 46 5259; fax: +44 1235 46 4404. E-mail address:
[email protected] (M. Jennison). 1 See the appendix of J. Pamela et al., Fusion Energy 2004 (Proc. 20th Int. Conf. Vilamoura, 2004) IAEA, Vienna (2004).
0920-3796/$ – see front matter © 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.fusengdes.2006.04.019
voltages of 1000 V dc. These voltages must not damage the transient recorder modules and they must not result in large currents, which could damage the wiring. The inputs could satisfy these requirements without isolation, but they would need high common mode input impedance. The three transient recorders described here are summarised in Table 1. They all have analogue inputs that are individually isolated to over 1000 V. As well as satisfying the safety requirements, isolated inputs provide other system benefits. Because there is no dc path, and a high impedance ac path, there are no ground loops and many noise problems are avoided. In principle there is an infinite common mode input impedance and common mode rejection ratio.
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Table 1 Comparative specification
Sample rate Isolation Number of channels Input configuration Input ranges Input range control Basic resolution Memory/channel Timing and trigger Approximately cost per channel First used on JET
UXD1
BAD2
UXD7 (provisional data)
10 ksamples/s (fixed) 1500 V dc 8 Single ended ±100 V to ±50 mV Component selection 16 bit 64 ksamples JET clock D 120 1994
2 Msamples/s (max) 1000 V ac 4 Differential ±10 V to ±125 mV Programmable gain amp 14 bit 64 Msamples JET clock or external D 700 2003
200 ksamples/s (max) 1500 V dc 8 Differential ±10 V to ±50 mV Programmable gain amp 16 bit 8 Msamples JET clock D 200 2006
The biggest disadvantage in requiring each channel to be separately isolated to 1000 V is that JET cannot use Commercial-Off-The-Shelf modules. So the isolated transient recorders used on JET are specially commissioned and cost more. However if the costs are low enough, the modules can be used even when isolation is not essential; quantities go up and costs come down.
2. System architecture Measuring the voltages on magnetic sensor coils is a major use for all these modules. As the sensor coils are inside the torus, the designs include isolated front ends. In all the modules described here, isolation comes directly after a serial ADC as this is the easiest and cheapest way to provide it. Before the UXD1, ADCs consumed too much power to be supplied with isolated power within the module; so either external (isolated) power was required or analogue isolation was used, resulting in problems of linearity and stability. When the UXD1 was designed, memory was expensive and it was not possible to store the whole pulse, so timing was complicated, using ‘importance sampling windows’ and variable-speed sample clocks. The newer designs benefit from cheap, small memory devices; they capture the whole pulse and timing is much simpler. All that is now required is the central synchronisation clock and a start (of pulse) trigger. As components continue to get smaller and more powerful, more of the transient recorder system can be built on a single module. A major contributor to this trend is the low-cost microprocessor; so in the case of
the UXD7, the entire system fits a single board and includes an embedded microprocessor with Ethernet interface.
3. Timing system The JET timing system distributes a ‘start of pulse’ trigger and a ‘JET clock’, a 1 MHz reference clock for synchronising subsystems. This allows correlations to be made between different diagnostics. All three ADC’s use these two signals to keep in step with the JET clock and to trigger sampling at a pre-set time in the pulse. The 2 MHz basic sampling rate of the BAD2 is generated by frequency multiplication of the 1 MHz reference. Simple frequency division is sufficient for the slower designs and the dc/dc convertors are synchronised to the clock, removing most of the coupled noise from the power supplies. The UXD1 system has provision for recording windows around JET ‘event triggers’, also distributed by the JET timing system. However, pre-programmed sampling sequences must leave memory storage available for recording an event, like a JET disruption. This complication is not required in the later designs because their larger memories enable the whole JET pulse to be recorded. Provided the time of the event is known, the data around it can be recovered after the pulse.
4. Data outputs In all three designs, the module simultaneously handles data in two different ways, as a transient recorder
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and as a real-time data source. To be a transient recorder, the module (usually) records data in local memory during the pulse, then it is archived directly after the pulse. All the modules output 2’s compliment 16-bit binary numbers. However there is a trend in large physics experiments to pass ‘physics units’ and the newest design (UXD7) also scales the output so that the measured input voltage can be read directly. In all cases, data is recovered from the transient recorders via JET’s Ethernet-based “DataNet”, (a protected data collection network). Recently CODAS’ preferred protocol to interface with the transient recorder system has become an HTTP server [2], but
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only in the case of the UXD7 is it a part of the module. Real-time data always goes by a separate lowlatency path. The UXD1 and UXD7 use dedicated serial interfaces; the BAD2 uses a dedicated DMA channel.
5. UXD1 module, 10 kHz sampling This module was developed originally for recording JET Magnetics signals and was first used in 1994. It is a 3U Eurocard with 8 channels simultaneously sampling to 16 bits.
Fig. 1. System based on UXD1 (and VPL1) modules.
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The sampling rate is fixed at 10 ksamples/s. To sample at a lower rate, the analogue signal is passed through an analogue filter before the UXD1 module and samples are collected at the required rate, the other samples are simply discarded. The input amplifier is component-configurable for different voltage ranges, from 50 mV to 100 V; it can also be configured for current input or as a precision integrator. Fig. 1 shows a system diagram, several of these modules are connected to a VPL1 (a 6U VME module) via a custom protocol running on a RS485 serial connection. The VME module stores the data during a pulse, and then the data is read from the VME system via an Ethernet port. Real-time data is available on the front panel of the VME module via a dedicated 8-bit serial port (a Texas Instruments TMS320C40 DSP comport). About 2500 channels have been deployed, of which about 400 have been recently added for the JET enhancements. Production of this module is coming to an end due to obsolete parts.
6. BAD2 module, 2000 kHz sampling As part of the recent JET enhancements, this module was developed by CODAS in collaboration with
INCAA Computers B.V. [3] and is based on PCI technology. Each PCI module contains 4 channels sampling to 14 bits. The maximum sampling rate is 2 Msamples/s and the ADC hardware is fixed to sample at this rate. However, lower sampling rates are software-selectable down to 30 samples/s. This is achieved by ‘downsampling’ in an FPGA containing programmable filters and decimators. The front end includes a softwaresettable gain stage. Fig. 2 is a system diagram. Up to five modules are fitted into a PC running Linux, a total of 20 channels. Up to 32 s of 2 MHz samples (per channel) are recorded in on-board memory; after a pulse the data is transferred to the PC’s local hard disk for inter-shot recovery. There is so much hard disk space available that archiving can be deferred for many pulses; to reduce the load on the networks the PC uses loss-less data compression. The interface to DataNet is via an HTTP server running on the PC. The Linux PC receives real-time data from the BAD2 module via the PCI bus using a dedicated DMA channel. The data is processed locally or passed on to other real-time computers by adding an ATM port on a standard PCI module. The BAD2 was initially used in 2003 for magnetic fluctuation studies when 64 channels were deployed.
Fig. 2. System based on BAD2 modules.
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Fig. 3. System based on UXD7 modules.
7. UXD7 module, 200 kHz sampling Currently CODAS are developing a medium speed design, see Fig. 3. It is a 3U Eurocard module with 8 channels simultaneously sampling to 16 bits. The maximum sampling rate is 200 ksamples/s and the ADC hardware is fixed to sample at this rate. In a similar way to the BAD2, the user can select lower sampling rates and again this is achieved using an FPGA containing programmable filters and decimators. The front end will have software-settable gain and offset. The FPGA is an Altera device and it contains a Nios microprocessor [3,4]. The Nios is a soft-core microprocessor, which means that it is synthesised directly from the FPGA gates, it only exists when the chip is programmed. This flexibility allows us to custom-design the microprocessor for the application. The Nios microprocessor is a powerful 32 bit device and can run a TCP/IP stack, so it will be used to run the HTTP server that interfaces directly to DataNet. This interface handles all the transient recorder duties along with any control functions. The interface for real-time applications has not been defined yet. The most likely solution will be an low voltage differential signal (LVDS) port on the UXD7 that
connects to a PCI Mezzanine Card (PMC) module containing an FPGA. The PMC module would be hosted on a VME or PCI-based real-time platform. Such a system would achieve a very low latency connection between 16 UXD7s (128 channels) and a VME/PCI platform. The UXD7 module will be fitted to JET as part of an upgrade to the Ion Cyclotron Resonance Heating (ICRH) system in the autumn of 2006.
8. Conclusions JET transient recorder systems have changed significantly in the last 10 years. Systems are more compact; what used to require several boards now fits on a small Eurocard. For modules with serial interfaces, Eurocard remains a convenient mechanical format. Flexible, software-configurable hardware has replaced hardwired component selection. Intelligence on the module is increasing with the inclusion of dedicated microprocessors. The computer interfaces to DAQ modules are moving from parallel standards such as VME to serial interfaces including Ethernet. There are many standards for connecting real-time signals, but there is no single, obvious choice.
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Acknowledgement This work has been conducted under the European Fusion Development Agreement. References [1] P. Noll, Earthing of JET components, JTS/H(02)768, CODAS documentation centre, 1986. http://www.iop.org/Jet/article? EFDR02003.
[2] C. Hogben, S. Griph, Interfacing to JET plant equipment using the HTTP protocol, JDN/H(02)11, CODAS documentation centre, 2002. http://www.iop.org/Jet/article?EFDR02004. [3] INCAA Computers bv, Apeldoorn, Netherlands. http://www. incaacomputers.com/. [4] Altera Corporation, San Jose, California, USA. http://www. altera.com/products/ip/processors/nios2/ni2-index.html.