Devices meeting probes the limits of semiconductors and circuitry

Devices meeting probes the limits of semiconductors and circuitry

World Abstracts on Microelectronics and Reliability 997 reasons of a practical and theoretical nature), it will be shown that the unconditional fail...

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World Abstracts on Microelectronics and Reliability

997

reasons of a practical and theoretical nature), it will be shown that the unconditional failure rate decreases hyperbolically with time. Consequently, a new "bath-curve" profile is obtained in which the horizontal line becomes slightly inclined. Lastly, the proposed model reveals a simple relationship between the burn-in time for a batch of components and the unconditional failure rate of the same batch after burn-in.

software to hardware in current high reliability real time systems, and how this relationship is likely to change in the future. Discussion in the paper centres around issues such as: factors that contribute to effective maintenance design; hardware characteristics that affect software; partitioning of maintenance functions between software, firmware and hardware: and current trends in maintenance of real time systems.

Maintenance of reliable real time systems: hardware versus software tradeoffs. INDER M. SOI and K. K. AGGARWAL. Microelectron. Reliab. 22 (3), 357 (1982). The maintenance features in a high reliability real time control system form an important component in the total system. It is essential that software and hardware maintenance features function in an effective manner to ensure a high level of reliability in real time systems. Hardware maintenance features include redundant processors, self-checking circuits, diagnostic microcode etc., while software maintenance features include fault recovery programmes, audits, diagnostics etc. In this paper, we examine briefly the relationship of maintenance

Designing reliable communication networks in a planned failure environment. INDER M. Sol and K. K. AGGARWAL. Microelectron. Reliab. 22 (3), 363 (1982). A very important issue in many network applications is to provide protection against planned failures. In this paper we first define the concept of a planned failure and then analyse the cost implications in the design of a network for survivability (i.e. protection against planned failure), as against designing a network against random failures. We suggest a simple and systematic approach for designing survivable communication networks and also discuss briefly the consequences of availability of partial knowledge only.

4. M I C R O E L E C T R O N I C S - - G E N E R A L Evaluating the MIL-STD-883B alternate die visual screen for LSI. ALBERTO. BENDURE.IEEE Trans. Components Hybrids mj~7 Technol. CHMT-5 (4), 355 (1982). Trends towards further miniaturization in very high speed integrated circuits (VHSIC), as well as complex large-scale integrated (LSI) circuits, support the fact that visual inspection will not be able to adequately screen future microcircuits. Method 5004 in MIL-STD-883B offers an alternative to the standard method 2010 visual inspection. An evaluation was performed to see if the method 5004 alternate could be implemented on 7 gm technology metal-gate complementary metal oxide-semiconductor (CMOS) devices while maintaining the same reliability and performance as devices inspected to method 2010 criteria. The results show no degradation in reliability or performance while increasing visual inspection yield by 90 per cent and reducing inspection time from 250 to 500 per cent. Devices meeting probes the limits of semiconductors and circuitry. RODERIC BERESFORD.Electronics, 138 (15 December

1982). Aggressive scaling and isolation schemes improve MOS and bipolar processes; transistor designs cut a path to fast memories and high-voltage chips; and gallium arsenide gears up for its role in future ultrafast logic circuitry. Services for monitoring hazardous conditions. PETER H. SINGER. Semiconductor Int., 83 (November 1982). Employee safety is continuing to be of paramount importance to the semiconductor industry. A wide variety of services are available to help device manufacturers manage and monitor possible hazardous conditions, a job as important as it is challenging. Success with handling hazardous gases. PIETERS. BURGGRAAF. Semiconductor Int., 55 (November 1982). Why are the many potentially hazardous gases used in semiconductor processing handled rather well? Generally, the complexity of semi-conductor fabrication--its engineering, processing and equipment--has included a sophisticated-hazard-control strategy.

5. M I C R O E L E C T R O N I C S - - D E S I G N A N D C O N S T R U C T I O N Packaging reliability--how to define and measure it. ROBERTT. HOWARD. IEEE Trans. Components Hybrids mfo Technol. CHMT-5 (4), 454 (1982). Microelectronic packaging employs many combinations of materials and processes to effect the interconnection of active and passive components and to provide interfaces with system levels of equipment. Reliability of these first-level packages is a key element in user acceptance and economics of electronic equipment. Complex interactions of design, materials, and processes may significantly affect package reliability. A tutorial approach to reliability methodology for first-level packaging as practised in one company is presented. It emphasizes the identification of physical processes of degradation, approaches for mathematical modelling to relate accelerated testing to field application, and statistical quantification of unreliability (the complement of reliability). Application of this methodology is exemplified in the evaluation of several potential failure mechanisms discovered during the introduction of a new alloy for flipchip interconnection to the IBM packaging technology. L P C V D of aluminium and AI-Si alloys for semiconductor metallization. M. J. COOKE,R. A. HEINECKE,R. C. STERN and J. W. C. MAES. Solid St. Technol., 62 (December 1982). Aluminium films have been deposited on silicon and oxidized

silicon wafer substrates by the pyrolysis of tri-isobutyl aluminium vapour (TIBA) at low pressure in a hot wall furnace reactor. The films have been subsequently alloyed with silicon in a new way by further heating in the presence of silane. A deposition temperature in the range of 250-300°C is used, and alloys up to 0.8 weight per cent Si have been produced. Up to 25 3-inch wafers can be coated simultaneously in the present apparatus; the thickness uniformity is + 10 % with a deposition rate in the range 10-30 nm min- 1. The films are relatively rough, but have good electromigration resistance and exceptionally good step coverage; even overhanging edges have been uniformly coated. Interconnection and circuit packaging for electromagnetic compatibility. JERRY H. BOGAR and ERIC VANDERHEYDEN. IEEE Trans. Components Hybrids mJ9 Technol. CHMT-5 (4), 470 (1982). Electromagnetic compatibility (EMC) has become a desirable and necessary feature of almost all modern electronic products. EMC as a design objective requires a careful study and understanding of a technically complex subject and involves such diverse technical disciplines as shielding, grounding, filtering, and fibre optics. The unique attributes of each of these methods, properly applied and implemented, offer effective alternatives in inter-