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Dielectric breakdown characteristics and interface trapping of hafnium oxide films
Microelectronics Journal 36 (2005) 29–33 www.elsevier.com/locate/mejo
Dielectric breakdown characteristics and interface trapping of hafnium oxide films N. Zhana, M.C. Poona, Hei Wongb,*, K.L. Nga, C.W. Koka a
Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong b Department of Electronic Engineering, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong, China Received 7 July 2004; received in revised form 29 September 2004; accepted 6 October 2004 Available online 10 December 2004
Abstract The reliability and integrity of HfO2 prepared by direct sputtering of hafnium were studied. By monitoring the current-voltage and currentstressing duration characteristics, we found a significant charge trapping effect in thin film with very short stressing time (!30 s) but the stress-induced trap generation is insignificant. The breakdown characteristics of hafnium gate oxide were also investigated in detail. We found that several soft breakdowns take place before a hard breakdown. Area and stress-voltage effects of the time-dependent dielectric breakdown were observed. Results suggest that the soft and hard breakdowns should have different precursor defects. A two-layer breakdown model of is proposed to explain these observations. q 2004 Elsevier Ltd. All rights reserved.
1. Introduction MOS technology has become the prevailing technology for today’s IC manufacturing. For 65-nm technology node, the equivalent thickness of gate oxide for MOS devices should be in the range of 1 to 2 nm [1–2]. Conventional thermal oxide in this thickness will result in unacceptable large gate leakage current (O100 A/cm2) due to the direct tunneling effect. Hence alternative high dielectric constant (k) gate dielectric materials have to be used [1–2]. Hafnium oxide (HfO2) was proposed to be one of the possible candidates for this resolution because of the relatively high dielectric constant, high free energy of reaction with Si, larger band gap than other high-k contenders [3]. Several investigations on the material properties and applications of HfO2 have been conducted [3–8]. However, besides the higher k value, most of the electrical characteristics of HfO2 cannot be comparable with silicon oxide and silicon oxynitride [8–12]. Balog et al. [4] performed capacitance-voltage (C–V) measurements in Al/HfO2/Si structures with very thick (O300 nm) polycrystalline HfO2 film and observed a large hysteresis in * Corresponding author. Tel.: C86 2788 7722; fax: C86 2788 7791. E-mail address: [email protected] (H. Wong). 0026-2692/$ - see front matter q 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2004.10.006
the C–V characteristics, high mid-gap interface state density and small breakdown field. Kim et al. [6] recently studied the time dependent dielectric breakdown (TDDB) of a very thin (w4.5 nm) HfO2 films and found that the soft and hard breakdown has different statistical distributions. These results need further experimental confirmation and the physical mechanism for giving these observations need to be explored further. With this connection, the instabilities of the DC-sputtering hafnium oxide under constant voltage stressing will be investigated in details with the current-voltage measurement. Time Dependent Dielectric Breakdown (TDDB) characteristics will be measured to characterize the lifetime and integrity of the HfO2 film. 2. Experiments The fabrication process was started with the standard RCA cleaning on the silicon wafers with resistivity of about 20 U cm. The wafers were loaded into the ARC-12M chamber for Hf sputtering. Prior to sputtering, the chamber was vacuumed to 10K6 Torr, ionized Ar and oxygen gas (with O2/Ar ratio of 8% or16%) was then pumped into the chamber. The pressure is maintained at 10K3 Torr during the Hf sputtering and the sputtering power was 120 W. After the Hf sputtering, the samples were rapid thermal annealed
30
N. Zhan et al. / Microelectronics Journal 36 (2005) 29–33
at temperature in the range of 500 to 800 8C for several different durations. The ambience for rapid thermal annealing (RTA) could be either pure N2 or pure O2 gas. An aluminum layer with thickness of 600 nm was then deposited. Finally, Al electrodes were patterned using photolithography technique and a number of MOS capacitors in different sizes were formed. To study the electrical characteristics, capacitance-voltage (C–V), current-voltage (I–V) and constant voltage stressing characteristics of the MOS capacitors were measured using HP4284 precision meter and HP4155A pico-ammeter in dark chamber at room temperature. 3. Results and discussion The leakage current is an important issue for the high-k material using as the gate dielectric in nanoscale device. The current transport mechanism and the related reliability issues need to be understood well. Although constant-field scaling rule may be adopted in designing a nanoscale device structure, the high electric field region near the drain region will still cause serious trap generation at the dielectric/ silicon interface and charge injection into the gate dielectric [10–11]. It is one of the major sources causing device instabilities and failure of small-sized MOS devices [10–11]. Thus the reliability assurance of the device properties often involves the stressing of a MOS device at high electric field. Fig. 1 depicts the stress-induced changes of the I–V characteristics for the 30-nm sample with RTA in nitrogen at 600 8C for 20 min. The I–V curves of the fresh device were first measured. A positive bias of the device at accumulation region was applied for 30 s and then I–V characteristic was measured again. The procedure was repeated for another 30 s. As shown in Fig. 1, the 30-nm sample clearly exhibits a pronounced enhancement of leakage at 3.2 V. The leakage conduction before 3.2 V should be due to the trap-assisted conduction and for larger voltage Fowler-Nordheim (FN)
conduction took place [9]. After positive voltage stressing, lateral shift in the I–V curve was observed. This result can be explained with the effect of electron trapping in the hafnium oxide which induced a cathode field lowering and hence a reduction in the post-stressed current. Further (60 s) stressing did not result in further significant current lowering. The first 30-s stressing at 8 V was sufficient to fill most of the traps and the generation of new trap is insignificant for further stressing. This observation is confirmed with high-frequency (1 MHz) capacitance-voltage (C–V) measurement as depicted in Fig. 2. Fig. 3 shows the effects of constant voltage stressing on the I–V characteristics of the 10-nm sample with 600 8C RTA for 20 min. The measurement procedure was the same as that for the 30-nm sample. A large direct tunneling (DT) current is observed in the 10-nm sample because of low barrier height (!1.13 eV [8]). Direct tunneling is not obvious for silicon oxide in this thickness as the electronic
Fig. 1. Current-voltage characteristics of the 30-nm HfO2 film before and after constant-voltage stressing.
Fig. 3. Current-voltage characteristics of the 10-nm HfO2 film before and after constant voltage stressing.
Fig. 2. Effects of constant voltage stressing on the C–V characteristics for 30-nm sample.
N. Zhan et al. / Microelectronics Journal 36 (2005) 29–33
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Fig. 4. Time evolution of charge transport behaviors at four positive gate voltages.
barrier for direct tunneling is much larger (w3.1 eV). Again, it seems that 30 s stressing at 5 V can fill most of the electron traps in the dielectric film. Negative stressing results in upshift of the DT current as a result of depopulation of trapped charges. Positive stressing again results in the right shift of the I–V curve for voltage greater than 4 V. However, positive and negative voltage stresses have some effect on I–V characteristics for gate voltage greater than 5 V where the current conduction is mainly due to FN tunneling. To have a clearer picture on the charge trapping during stressing, the transient current behaviors during the stressing were recorded. Fig. 4(a) and (b) show the current as a function of time after constant voltage stressing for the 30 nm and 10 nm sample, respectively. A large current is record as soon as the stressing commences and then the current decay exponentially. The stressing current becomes steady after 20 s stressing for both samples. These results agree with the I–V results reported in Figs. 1 and 3. In addition, it is obvious that the amount of trapped charge is function of the stressing voltage for both samples. The larger the stressing voltage, the more serve band bending of the Al/HfO2/Si structure and larger current is detected and more trips can be filled. TDDB measurement was conducted to study the oxide integrity. Since the breakdown voltage was around 9 V for the 10-nm HfO2 film, constant voltage stressing that near
Fig. 5. (a) Time-dependent dielectric breakdown characteristics of the capacitor with area of 3.14!10K4 cm2 at different stressing voltage; and (b) area dependent TDDB of three different size capacitors stressed at 6 V.
this voltage was applied. Fig. 5 shows the typical breakdown behavior of 10-nm sample. As shown in Fig. 5(a), there is a clear breakdown with about six orders of magnitude gate current change for constant-voltage stress at 8 V for 5 min. For smaller stress voltage, time-to-breakdown increases by several orders. In addition, the current remains fairly unchanged after the major runaway. Before the breakdown, the leakage current decreases as the stressing proceeds because of charge trapping in the dielectric. Fig. 5(b) compares the area dependent TDDB characteristics for 10 nm thick samples. With the same physical thickness, both soft and hard breakdown are found to be strong area dependent. The TDDB time was shorter in larger area capacitors. As the area increases, the effect of soft breakdown on I–V characteristic is reduced. The soft breakdown distribution is very irregular regardless the basing voltage and capacitor area. The 2!10K4 cm2 capacitor shows about an order of magnitude increases on gate current before reaching the big runaway. If the size of the capacitor is reduced to 1!10K4 cm2, we observed about two orders of
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N. Zhan et al. / Microelectronics Journal 36 (2005) 29–33
magnitude gate current increases before reaching the runaway. After the big runaway, the area dependency of the gate current is insignificant. Time-to-breakdown also increases significantly for the smaller sized capacitors and current change after a major runaway is obvious. The longer breakdown time should be due to the soft breakdown phenomena exist in the gate dielectrics. Soft breakdown is often ascribed to a weak localized percolation path between the gate electrode and the substrate. If the defect density generated in the gate dielectric layer and the interface reaches to a critical number, a percolation cluster will be formed and induced the soft breakdown [13]. The large fluctuation in the leakage current in the soft breakdown region should be due to the charge trapping-detrapping in the percolation clusters [13]. The statistics of oxide breakdown can be described by the Weibull distribution: ln½Klnð1 K FÞ Z b ln tBD K b ln a
(1)
where b is the Weibull slope which governs the breakdown distribution. In SiO2 or oxynitride, the Weibull slope of hard breakdown is in the range of 1.8 to 1.95 [12]. The breakdown mechanism is often attributed to the breakage of Si–Si in the oxide. If the breakdown spots are distributed according to the Poisson rule, we have A ln½Klnð1KFðtBD1 ÞÞKln½Klnð1KFðtBD2 Þ Zln 1 A2 (2) Combining (1) and (2), the Weibull slope (b) of gate dielectic can be readily extracted from area dependence TDDB [13]: 1=b tBD1 A Z 2 (3) tBD2 A1 where tBD1 and tBD2 are time-to-breakdown for capacitor with area A1 and A2, respectively. Similarly, the charge to breakdown also follows the area dependency as the leakage current density should be the same for different size capacitors, i.e. 1=b QBD1 A Z 2 (4) QBD2 A1 Based on the TDDB results, b was calculated to be 1.43 for soft breakdown and 1.95 for hard breakdown. These values are slightly smaller than those reported by Kim et al. [6]. Although the time-to-soft breakdown shows irregular Weibull distribution, the time to hard breakdown still agree with (3). The different value of Weibull shape factor for soft and hard breakdown suggest a different scenario from the breakdown mechanism of silicon oxide [11]. The Weibull slope of hard breakdown is very close to that of silicon oxide. This observation can be explained with the two-layer model of dielectric breakdown. A low-k silicate interfacial layer is found with x-ray photoelectron
Fig. 6. Proposed structure of the transition silicate layer for thermallyannealed HfO2/Si interface.
spectroscopy (XPS) in between the hafnium oxide and silicon substrate (see Fig. 6) [14–15]. For high-k/low-k stacked dielectric film structure, the applied electric field will be largely distributed in the low-k region according to the Gauss’s law (i.e. Elow-k/Ehigh-kZkhigh-k/klow-k). In addition, the critical defect density for causing the low-k layer to break down is much lower because it is much thinner than the bulk high-k layer. As a result, the first breakdown (soft breakdown) happens in the low-k layer. Fig. 7 shows a projection of the maximum operating voltage for 10-nm hafnium oxide film. The ten-year lifetime operating voltage was predicted to be 0.9 V for capacitor with size of 3.14!10K4 cm2 whereas for the 1!10K4 cm2 capacitor the operating voltage can be greatly increased to about 1.4 V as the amount of defect that cause the failure in the small area device is much smaller than that of the large area device. In nanoscale devices, the operating voltage for the 10-year lifetime could be greatly increased due to the much smaller area of the device structure. That is the oxide lifetime would be long enough for operation voltage of 1.2 V in the 65-nm technology node application [2] provides that the E-model is still valid. However, we still need to find ways to decrease the origin of the defects so as to improve the reliability and stability of device characteristics [15].
Fig. 7. Device lifetime projection of the 10 nm hafnium oxide film.
N. Zhan et al. / Microelectronics Journal 36 (2005) 29–33
4. Conclusions In summary, hafnium oxide films were prepared by direct sputtering of Hf with rapid thermal annealing in nitrogen or oxygen. To characterize the lifetime and integrity of the HfO2 gate oxide, constant-voltage stressing on the dielectric films was conducted. Area and stress–voltage effects of the time-dependent dielectric breakdown (TDDB) were also studied. It was found that the Weibull shape factors for soft and hard breakdown are different and their values are 1.43 and 1.95, respectively. These results suggested that the soft breakdown should have different precursor defects from those of the hard breakdown.
Acknowledgements The work described in this paper was support by a UGC Competitive Earmarked Research Grant of Hong Kong (Project No: HKUST6174/01E).
References [1] Y. Taur, D.A. Buchanan, W. Chen, D.J. Frank, K.E. Ismail, H.S.P. Wong, CMOS scaling into the nanometer regime, Proc. IEEE 85 (1997) 486–503. [2] H. Iwai, S. Ohmi, Silicon integrated circuit technology from past to future, Microelectron. Reliab. 42 (2002) 465–491. [3] G.D. Wilk, R.M. Wallace, J.M. Anthony, High-k gate dielectrics: current status and materials properties considerations, J. Appl. Phys. 89 (10) (2001) 5243–7275.
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[4] M. Balog, M. Schieber, M. Michman, S. Patai, Chemical vapor deposition and characterization of HfO2 films from organo-hafnium compounds, Thin Solid Films 41 (1977) 247–259. [5] P.D. Kirsch, C.S. Kangl, J. Lozano, J.C. Lee, J.G. Ekerdt, Electrical and spectroscopic comparison of HfO2/Si interfaces on nitrided and un-nitrided Si(100), J. Appl. Phys. 91 (2002) 4353–4363. [6] Y.H. Kim, K. Onishi, C.S. Kang, H.-J. Cho, R. Nieh, S. Gopalan, R. Choi, J. Han, S. Krishnan, J.C. Lee, Area dependence of TDDB characteristics for HfO2 gate dielectrics, IEEE Electron Device Lett. 23 (2002) 594–596. [7] W.J. Zhu, T.P. Ma, S. Zafar, T. Tamagawa, Charge trapping in ultrathin hafnium oxide, IEEE Electron Device Lett. 23 (2002) 597–599. [8] K.L. Ng, N. Zhan, C.W. Kok, M.C. Poon, H. Wong, Electrical characterization of the hafnium oxide prepared by direct sputtering of Hf in oxygen with rapid thermal annealing, Microelectron. Reliab. 43 (2003) 1289–1293. [9] H. Wong, Y.C. Cheng, Electronic conduction mechanism in thin oxynitride films, J. Appl. Phys. 70 (1991) 1078–1080. [10] H. Wong, A physically based drain avalanche breakdown model for MOSFET’s, IEEE Trans Electron Devices 42 (1995) 2197–2202. [11] H. Wong, Y.C. Cheng, Generation of interface states at the silicon/oxide interface due to hot electron injection, J. Appl. Phys. 74 (1993) 7364–7368. [12] M.L. Green, E.P. Gusev, R. Degraeve, E.L. Garfunkel, Ultrathin (!4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: understanding the processing, structure, and physical and electrical limits, J. Appl. Phys. 90 (2001) 2057–2121. [13] T. Nigam, R. Degraeve, G. Groeseneken, M.M. Heyns, H.E. Maes, Constant current charge-to-breakdown: still a valid tool to study the reliability of MOS structures?, Proc. IRPS 1998; 62–69. [14] N. Zhan, K.L. Ng, M.C. Poon, C.W. Kok, H. Wong, XPS study of the thermal instability of HfO2 prepared by Hf sputtering in oxygen with RTA, J. Electrochem. Soc. 150 (2003) F200–F202. [15] H. Wong, K.L. Ng, N. Zhan, M.C. Poon, C.W. Kok, Interface bonding structure of hafnium oxide prepared by direct sputtering of hafnium in oxygen, J. Vac. Sci. Technol. B 22 (2004) 1094–1100.
Dielectric breakdown characteristics and interface trapping of hafnium oxide films N. Zhana, M.C. Poona, Hei Wongb,*, K.L. Nga, C.W. Koka a
Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong b Department of Electronic Engineering, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong, China Received 7 July 2004; received in revised form 29 September 2004; accepted 6 October 2004 Available online 10 December 2004
Abstract The reliability and integrity of HfO2 prepared by direct sputtering of hafnium were studied. By monitoring the current-voltage and currentstressing duration characteristics, we found a significant charge trapping effect in thin film with very short stressing time (!30 s) but the stress-induced trap generation is insignificant. The breakdown characteristics of hafnium gate oxide were also investigated in detail. We found that several soft breakdowns take place before a hard breakdown. Area and stress-voltage effects of the time-dependent dielectric breakdown were observed. Results suggest that the soft and hard breakdowns should have different precursor defects. A two-layer breakdown model of is proposed to explain these observations. q 2004 Elsevier Ltd. All rights reserved.
1. Introduction MOS technology has become the prevailing technology for today’s IC manufacturing. For 65-nm technology node, the equivalent thickness of gate oxide for MOS devices should be in the range of 1 to 2 nm [1–2]. Conventional thermal oxide in this thickness will result in unacceptable large gate leakage current (O100 A/cm2) due to the direct tunneling effect. Hence alternative high dielectric constant (k) gate dielectric materials have to be used [1–2]. Hafnium oxide (HfO2) was proposed to be one of the possible candidates for this resolution because of the relatively high dielectric constant, high free energy of reaction with Si, larger band gap than other high-k contenders [3]. Several investigations on the material properties and applications of HfO2 have been conducted [3–8]. However, besides the higher k value, most of the electrical characteristics of HfO2 cannot be comparable with silicon oxide and silicon oxynitride [8–12]. Balog et al. [4] performed capacitance-voltage (C–V) measurements in Al/HfO2/Si structures with very thick (O300 nm) polycrystalline HfO2 film and observed a large hysteresis in * Corresponding author. Tel.: C86 2788 7722; fax: C86 2788 7791. E-mail address: [email protected] (H. Wong). 0026-2692/$ - see front matter q 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2004.10.006
the C–V characteristics, high mid-gap interface state density and small breakdown field. Kim et al. [6] recently studied the time dependent dielectric breakdown (TDDB) of a very thin (w4.5 nm) HfO2 films and found that the soft and hard breakdown has different statistical distributions. These results need further experimental confirmation and the physical mechanism for giving these observations need to be explored further. With this connection, the instabilities of the DC-sputtering hafnium oxide under constant voltage stressing will be investigated in details with the current-voltage measurement. Time Dependent Dielectric Breakdown (TDDB) characteristics will be measured to characterize the lifetime and integrity of the HfO2 film. 2. Experiments The fabrication process was started with the standard RCA cleaning on the silicon wafers with resistivity of about 20 U cm. The wafers were loaded into the ARC-12M chamber for Hf sputtering. Prior to sputtering, the chamber was vacuumed to 10K6 Torr, ionized Ar and oxygen gas (with O2/Ar ratio of 8% or16%) was then pumped into the chamber. The pressure is maintained at 10K3 Torr during the Hf sputtering and the sputtering power was 120 W. After the Hf sputtering, the samples were rapid thermal annealed
30
N. Zhan et al. / Microelectronics Journal 36 (2005) 29–33
at temperature in the range of 500 to 800 8C for several different durations. The ambience for rapid thermal annealing (RTA) could be either pure N2 or pure O2 gas. An aluminum layer with thickness of 600 nm was then deposited. Finally, Al electrodes were patterned using photolithography technique and a number of MOS capacitors in different sizes were formed. To study the electrical characteristics, capacitance-voltage (C–V), current-voltage (I–V) and constant voltage stressing characteristics of the MOS capacitors were measured using HP4284 precision meter and HP4155A pico-ammeter in dark chamber at room temperature. 3. Results and discussion The leakage current is an important issue for the high-k material using as the gate dielectric in nanoscale device. The current transport mechanism and the related reliability issues need to be understood well. Although constant-field scaling rule may be adopted in designing a nanoscale device structure, the high electric field region near the drain region will still cause serious trap generation at the dielectric/ silicon interface and charge injection into the gate dielectric [10–11]. It is one of the major sources causing device instabilities and failure of small-sized MOS devices [10–11]. Thus the reliability assurance of the device properties often involves the stressing of a MOS device at high electric field. Fig. 1 depicts the stress-induced changes of the I–V characteristics for the 30-nm sample with RTA in nitrogen at 600 8C for 20 min. The I–V curves of the fresh device were first measured. A positive bias of the device at accumulation region was applied for 30 s and then I–V characteristic was measured again. The procedure was repeated for another 30 s. As shown in Fig. 1, the 30-nm sample clearly exhibits a pronounced enhancement of leakage at 3.2 V. The leakage conduction before 3.2 V should be due to the trap-assisted conduction and for larger voltage Fowler-Nordheim (FN)
conduction took place [9]. After positive voltage stressing, lateral shift in the I–V curve was observed. This result can be explained with the effect of electron trapping in the hafnium oxide which induced a cathode field lowering and hence a reduction in the post-stressed current. Further (60 s) stressing did not result in further significant current lowering. The first 30-s stressing at 8 V was sufficient to fill most of the traps and the generation of new trap is insignificant for further stressing. This observation is confirmed with high-frequency (1 MHz) capacitance-voltage (C–V) measurement as depicted in Fig. 2. Fig. 3 shows the effects of constant voltage stressing on the I–V characteristics of the 10-nm sample with 600 8C RTA for 20 min. The measurement procedure was the same as that for the 30-nm sample. A large direct tunneling (DT) current is observed in the 10-nm sample because of low barrier height (!1.13 eV [8]). Direct tunneling is not obvious for silicon oxide in this thickness as the electronic
Fig. 1. Current-voltage characteristics of the 30-nm HfO2 film before and after constant-voltage stressing.
Fig. 3. Current-voltage characteristics of the 10-nm HfO2 film before and after constant voltage stressing.
Fig. 2. Effects of constant voltage stressing on the C–V characteristics for 30-nm sample.
N. Zhan et al. / Microelectronics Journal 36 (2005) 29–33
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Fig. 4. Time evolution of charge transport behaviors at four positive gate voltages.
barrier for direct tunneling is much larger (w3.1 eV). Again, it seems that 30 s stressing at 5 V can fill most of the electron traps in the dielectric film. Negative stressing results in upshift of the DT current as a result of depopulation of trapped charges. Positive stressing again results in the right shift of the I–V curve for voltage greater than 4 V. However, positive and negative voltage stresses have some effect on I–V characteristics for gate voltage greater than 5 V where the current conduction is mainly due to FN tunneling. To have a clearer picture on the charge trapping during stressing, the transient current behaviors during the stressing were recorded. Fig. 4(a) and (b) show the current as a function of time after constant voltage stressing for the 30 nm and 10 nm sample, respectively. A large current is record as soon as the stressing commences and then the current decay exponentially. The stressing current becomes steady after 20 s stressing for both samples. These results agree with the I–V results reported in Figs. 1 and 3. In addition, it is obvious that the amount of trapped charge is function of the stressing voltage for both samples. The larger the stressing voltage, the more serve band bending of the Al/HfO2/Si structure and larger current is detected and more trips can be filled. TDDB measurement was conducted to study the oxide integrity. Since the breakdown voltage was around 9 V for the 10-nm HfO2 film, constant voltage stressing that near
Fig. 5. (a) Time-dependent dielectric breakdown characteristics of the capacitor with area of 3.14!10K4 cm2 at different stressing voltage; and (b) area dependent TDDB of three different size capacitors stressed at 6 V.
this voltage was applied. Fig. 5 shows the typical breakdown behavior of 10-nm sample. As shown in Fig. 5(a), there is a clear breakdown with about six orders of magnitude gate current change for constant-voltage stress at 8 V for 5 min. For smaller stress voltage, time-to-breakdown increases by several orders. In addition, the current remains fairly unchanged after the major runaway. Before the breakdown, the leakage current decreases as the stressing proceeds because of charge trapping in the dielectric. Fig. 5(b) compares the area dependent TDDB characteristics for 10 nm thick samples. With the same physical thickness, both soft and hard breakdown are found to be strong area dependent. The TDDB time was shorter in larger area capacitors. As the area increases, the effect of soft breakdown on I–V characteristic is reduced. The soft breakdown distribution is very irregular regardless the basing voltage and capacitor area. The 2!10K4 cm2 capacitor shows about an order of magnitude increases on gate current before reaching the big runaway. If the size of the capacitor is reduced to 1!10K4 cm2, we observed about two orders of
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N. Zhan et al. / Microelectronics Journal 36 (2005) 29–33
magnitude gate current increases before reaching the runaway. After the big runaway, the area dependency of the gate current is insignificant. Time-to-breakdown also increases significantly for the smaller sized capacitors and current change after a major runaway is obvious. The longer breakdown time should be due to the soft breakdown phenomena exist in the gate dielectrics. Soft breakdown is often ascribed to a weak localized percolation path between the gate electrode and the substrate. If the defect density generated in the gate dielectric layer and the interface reaches to a critical number, a percolation cluster will be formed and induced the soft breakdown [13]. The large fluctuation in the leakage current in the soft breakdown region should be due to the charge trapping-detrapping in the percolation clusters [13]. The statistics of oxide breakdown can be described by the Weibull distribution: ln½Klnð1 K FÞ Z b ln tBD K b ln a
(1)
where b is the Weibull slope which governs the breakdown distribution. In SiO2 or oxynitride, the Weibull slope of hard breakdown is in the range of 1.8 to 1.95 [12]. The breakdown mechanism is often attributed to the breakage of Si–Si in the oxide. If the breakdown spots are distributed according to the Poisson rule, we have A ln½Klnð1KFðtBD1 ÞÞKln½Klnð1KFðtBD2 Þ Zln 1 A2 (2) Combining (1) and (2), the Weibull slope (b) of gate dielectic can be readily extracted from area dependence TDDB [13]: 1=b tBD1 A Z 2 (3) tBD2 A1 where tBD1 and tBD2 are time-to-breakdown for capacitor with area A1 and A2, respectively. Similarly, the charge to breakdown also follows the area dependency as the leakage current density should be the same for different size capacitors, i.e. 1=b QBD1 A Z 2 (4) QBD2 A1 Based on the TDDB results, b was calculated to be 1.43 for soft breakdown and 1.95 for hard breakdown. These values are slightly smaller than those reported by Kim et al. [6]. Although the time-to-soft breakdown shows irregular Weibull distribution, the time to hard breakdown still agree with (3). The different value of Weibull shape factor for soft and hard breakdown suggest a different scenario from the breakdown mechanism of silicon oxide [11]. The Weibull slope of hard breakdown is very close to that of silicon oxide. This observation can be explained with the two-layer model of dielectric breakdown. A low-k silicate interfacial layer is found with x-ray photoelectron
Fig. 6. Proposed structure of the transition silicate layer for thermallyannealed HfO2/Si interface.
spectroscopy (XPS) in between the hafnium oxide and silicon substrate (see Fig. 6) [14–15]. For high-k/low-k stacked dielectric film structure, the applied electric field will be largely distributed in the low-k region according to the Gauss’s law (i.e. Elow-k/Ehigh-kZkhigh-k/klow-k). In addition, the critical defect density for causing the low-k layer to break down is much lower because it is much thinner than the bulk high-k layer. As a result, the first breakdown (soft breakdown) happens in the low-k layer. Fig. 7 shows a projection of the maximum operating voltage for 10-nm hafnium oxide film. The ten-year lifetime operating voltage was predicted to be 0.9 V for capacitor with size of 3.14!10K4 cm2 whereas for the 1!10K4 cm2 capacitor the operating voltage can be greatly increased to about 1.4 V as the amount of defect that cause the failure in the small area device is much smaller than that of the large area device. In nanoscale devices, the operating voltage for the 10-year lifetime could be greatly increased due to the much smaller area of the device structure. That is the oxide lifetime would be long enough for operation voltage of 1.2 V in the 65-nm technology node application [2] provides that the E-model is still valid. However, we still need to find ways to decrease the origin of the defects so as to improve the reliability and stability of device characteristics [15].
Fig. 7. Device lifetime projection of the 10 nm hafnium oxide film.
N. Zhan et al. / Microelectronics Journal 36 (2005) 29–33
4. Conclusions In summary, hafnium oxide films were prepared by direct sputtering of Hf with rapid thermal annealing in nitrogen or oxygen. To characterize the lifetime and integrity of the HfO2 gate oxide, constant-voltage stressing on the dielectric films was conducted. Area and stress–voltage effects of the time-dependent dielectric breakdown (TDDB) were also studied. It was found that the Weibull shape factors for soft and hard breakdown are different and their values are 1.43 and 1.95, respectively. These results suggested that the soft breakdown should have different precursor defects from those of the hard breakdown.
Acknowledgements The work described in this paper was support by a UGC Competitive Earmarked Research Grant of Hong Kong (Project No: HKUST6174/01E).
References [1] Y. Taur, D.A. Buchanan, W. Chen, D.J. Frank, K.E. Ismail, H.S.P. Wong, CMOS scaling into the nanometer regime, Proc. IEEE 85 (1997) 486–503. [2] H. Iwai, S. Ohmi, Silicon integrated circuit technology from past to future, Microelectron. Reliab. 42 (2002) 465–491. [3] G.D. Wilk, R.M. Wallace, J.M. Anthony, High-k gate dielectrics: current status and materials properties considerations, J. Appl. Phys. 89 (10) (2001) 5243–7275.
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