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Dielectric insulating method VM for manufacturing transistors and integrated circuits
480
W O R L D A B S T R A C T S ON M I C R O E L E C T R O N I C S
Part 2 will continue with the effecta on intesmted cireuits, MOS devices and padmging. It wilt conclude with d u i s n suidelines, and proMems of ~ c s . S. W. Swm~smKow. N a c ~ / m / k 22, No. 6 (1972), p. 177. (In German.) The author proceeds from
5. M I C R O ~ O N I C S - - ~ N Analysis of cremes of /~ilure in solderlm~ T. MIYAMA. ~ Of the Second S3n~Oo~m~ on R ~ a/d//ty, JUSE, Tokyo, Japan. 17-18 April (1972), p. 189. (In Japanese.) The present report specializes the causes of failure in soldering printed circuit plates so as to enhance their reliability. In the present experiment the temperature of solder at 240,~250°C was verified to be at its best condition, so also the conveyor speed of shifting the printed circuit plate was ascertained to be the best at 90 cm/min. If they were out of these limits icicles, dents and grains are apt to develop. It was also found that existence of oil or grease st~'nl or oxidation on the printed circuit plate or other parts would cause segregetion of Sn and Pb or pinhole and the strength of soldered parts will he lowered. These defects are, at the time of soldering, not easy to locate, and would pass unnoticed, but they would be the cause of disturbance in the future,
AND RELIABILITY
the present state of microelectronies, the physical development, and pmmneters tmderlyin8 the principles to consider pc~ibiliti~ of improvins exi~ing technologies. In this respect the development of high-speed digital circuits must not be forBotxen, which are based on modern circuitry. The tendency of a renunciation of traditloml principles has recently been observed by ~ to functional electronics and optoelectronies.
AND CONSINtUCTION ~ c ~ ~ V M f o r ~ ~ ~ aad ~ ~ D. AaMOAaTH.Nachr/cht~jdm/& 22, No. $ (1972), p. 152. (In German.) The dielectric insulating method VM is distinSuished from the EPIC method in that minor components, and in particular transistors, can be realized at an equal accuracysof positioning, in that minor collector path resistances can be attained and higher breakdown voltages Uceo can be guaranteed by suppressing the marginal curvature of the collector-base transition. Compared w/th the EPIC method, however, some more process steps are necessary when using the VM method.
E~'4x~c~tlLly-c~¥o ~Ide~-todmy111 mltt~l for ~ F. W. Ktn=_~gA. M/croe/ectrom~$ 4, No. I (1972), p. 15. The use of electrically-conductive epoxies for chip-bonding applications has truly come of abe. Today epoxies are universally recognized and accepted as an effective alternative to conventiowl eutectic bonding techniques. The transformation of epoxies in bonding techniques has come about for a number of r e s i n s . In this article the in-depth ¢~_eacteristica and techniques are presented as a guide for future application.
Procemlng of e m u l s i o n photommks for s e m i c m u l u c t ~ a l N d i ~ m m . K. G. CLA~. M/crodectromi~ 4, No. I (1972), p. 26. Serniconductor device technology has advanced rapidly over the past five years in the fields of discrete devices, ICs and the larger wafer sizes upon which these semiconductors are produced. This has provided the resultant effect that photomask making has undergone ever-chengin. " g requirements for the element dimemions, circuit sizes and overall mask sizes, with new equipment for the improved emulsion processing technologies. Here a comparison of applications in high resolution processing is made, highlighting the extreme care taken in emulsion photoplate processing for semiconductor applications,
Plastic cavity packalles for MOB LSI fill a very ~ ~ / ~ h o w l o n g | S. E. Sc~uPsIa. E/ectrom/~, 22 May (1972), p. 102. Pre-molded cavity packages are now being made by several manufacturers, but their ultimate staying power in the business is threatened by the specters of low-coet ceramics and fully molded plastics.
The generatioa of artwork for int, qpm~Kl clrculm.
L S I ~ ~ F a h r l c a t t ~ a h l g h
J. W. GRACZ. M / o ~ / ~ t r o m ~ 4, No. 1 (1972), p. 46. The layout and artwork design stage is the slowest and most tedious in the whole process of integrated circuit manufacture. It will be considered purely from the point of view of the layout engineer/draughtsman who is assumed to be a specialist in this field and not concerned with the problems of circuit design,
~ h ~ array. M. D. N w J t O T H end R.H. zmmq. EPP ~ , Mey-June (1972), p. 19. Described are design considerations, process controls and testing required to achieve a multilayer thick-film hybrid circuit consisti~ of continuous, fine line metaHzation patterns sepmted by smooth, void-free, high resolution insulati~ layers.
6. MICROELECTRONICS--4X)MI'O~ SYSTlg~ AND EQUIPMENTS A small llMihrument m l m ~ s c ~ 8 e~ll~l~al~e 72CH0577-7R. 25-27 January (1972), p. 251. If mature with m e d i c a l lnstnameat t~lah~qty. H. Ro~. of the 1972 Ammal Rd/abH/ty am/Ma/mta/nab///ty ~ympos/um, San Francisco. IEEE Cat. No.
PrOs
logic and common sense is used; if a company ensures its development of an interdisciplinary capability; if the staff is really ready to get its hands "bloody"; if the
W O R L D A B S T R A C T S ON M I C R O E L E C T R O N I C S
Part 2 will continue with the effecta on intesmted cireuits, MOS devices and padmging. It wilt conclude with d u i s n suidelines, and proMems of ~ c s . S. W. Swm~smKow. N a c ~ / m / k 22, No. 6 (1972), p. 177. (In German.) The author proceeds from
5. M I C R O ~ O N I C S - - ~ N Analysis of cremes of /~ilure in solderlm~ T. MIYAMA. ~ Of the Second S3n~Oo~m~ on R ~ a/d//ty, JUSE, Tokyo, Japan. 17-18 April (1972), p. 189. (In Japanese.) The present report specializes the causes of failure in soldering printed circuit plates so as to enhance their reliability. In the present experiment the temperature of solder at 240,~250°C was verified to be at its best condition, so also the conveyor speed of shifting the printed circuit plate was ascertained to be the best at 90 cm/min. If they were out of these limits icicles, dents and grains are apt to develop. It was also found that existence of oil or grease st~'nl or oxidation on the printed circuit plate or other parts would cause segregetion of Sn and Pb or pinhole and the strength of soldered parts will he lowered. These defects are, at the time of soldering, not easy to locate, and would pass unnoticed, but they would be the cause of disturbance in the future,
AND RELIABILITY
the present state of microelectronies, the physical development, and pmmneters tmderlyin8 the principles to consider pc~ibiliti~ of improvins exi~ing technologies. In this respect the development of high-speed digital circuits must not be forBotxen, which are based on modern circuitry. The tendency of a renunciation of traditloml principles has recently been observed by ~ to functional electronics and optoelectronies.
AND CONSINtUCTION ~ c ~ ~ V M f o r ~ ~ ~ aad ~ ~ D. AaMOAaTH.Nachr/cht~jdm/& 22, No. $ (1972), p. 152. (In German.) The dielectric insulating method VM is distinSuished from the EPIC method in that minor components, and in particular transistors, can be realized at an equal accuracysof positioning, in that minor collector path resistances can be attained and higher breakdown voltages Uceo can be guaranteed by suppressing the marginal curvature of the collector-base transition. Compared w/th the EPIC method, however, some more process steps are necessary when using the VM method.
E~'4x~c~tlLly-c~¥o ~Ide~-todmy111 mltt~l for ~ F. W. Ktn=_~gA. M/croe/ectrom~$ 4, No. I (1972), p. 15. The use of electrically-conductive epoxies for chip-bonding applications has truly come of abe. Today epoxies are universally recognized and accepted as an effective alternative to conventiowl eutectic bonding techniques. The transformation of epoxies in bonding techniques has come about for a number of r e s i n s . In this article the in-depth ¢~_eacteristica and techniques are presented as a guide for future application.
Procemlng of e m u l s i o n photommks for s e m i c m u l u c t ~ a l N d i ~ m m . K. G. CLA~. M/crodectromi~ 4, No. I (1972), p. 26. Serniconductor device technology has advanced rapidly over the past five years in the fields of discrete devices, ICs and the larger wafer sizes upon which these semiconductors are produced. This has provided the resultant effect that photomask making has undergone ever-chengin. " g requirements for the element dimemions, circuit sizes and overall mask sizes, with new equipment for the improved emulsion processing technologies. Here a comparison of applications in high resolution processing is made, highlighting the extreme care taken in emulsion photoplate processing for semiconductor applications,
Plastic cavity packalles for MOB LSI fill a very ~ ~ / ~ h o w l o n g | S. E. Sc~uPsIa. E/ectrom/~, 22 May (1972), p. 102. Pre-molded cavity packages are now being made by several manufacturers, but their ultimate staying power in the business is threatened by the specters of low-coet ceramics and fully molded plastics.
The generatioa of artwork for int, qpm~Kl clrculm.
L S I ~ ~ F a h r l c a t t ~ a h l g h
J. W. GRACZ. M / o ~ / ~ t r o m ~ 4, No. 1 (1972), p. 46. The layout and artwork design stage is the slowest and most tedious in the whole process of integrated circuit manufacture. It will be considered purely from the point of view of the layout engineer/draughtsman who is assumed to be a specialist in this field and not concerned with the problems of circuit design,
~ h ~ array. M. D. N w J t O T H end R.H. zmmq. EPP ~ , Mey-June (1972), p. 19. Described are design considerations, process controls and testing required to achieve a multilayer thick-film hybrid circuit consisti~ of continuous, fine line metaHzation patterns sepmted by smooth, void-free, high resolution insulati~ layers.
6. MICROELECTRONICS--4X)MI'O~ SYSTlg~ AND EQUIPMENTS A small llMihrument m l m ~ s c ~ 8 e~ll~l~al~e 72CH0577-7R. 25-27 January (1972), p. 251. If mature with m e d i c a l lnstnameat t~lah~qty. H. Ro~. of the 1972 Ammal Rd/abH/ty am/Ma/mta/nab///ty ~ympos/um, San Francisco. IEEE Cat. No.
PrOs
logic and common sense is used; if a company ensures its development of an interdisciplinary capability; if the staff is really ready to get its hands "bloody"; if the