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Digital filtering using the NEC μPD7720 signal processor
North-Holland Microprocessing and Microprogramming 14 (1984) 67-78
67
Digital Filtering using the NEC/ PD7720 Signal Processor Robert J. Simpson and Trevor J. Terrell Systems and Instrumentation Division, Preston Polytechnic, Preston, PRI 2TQ, England. The concepts of digital filtering using the NEC pPD7720 single-chip digital signal processor are presented. The architecture and instruction formats of the device are summarised. The design philosophy and practical hardware and software considerations of using the 7720 as a peripheral to a host 8085 microprocessor system are discussed.
Keywords: Digital filter, Signal Processor, Chip Architecture, NEC pPD7720, host mpu, system evaluation, mpu, system evaluation, microprocessors.
I. Introduction
In recent years digital signal processing has played a more important role in telecommunication applications. This has occurred due to the increased availability and relatively low cost of LSI chips for system implementation. In many cases the single-chip stored program approach provides a versatile and cost-effective method of implementing real-time digital signal processing operations [1-4]. In particular the NEC/tPD7720 signal processor chip has an architecture design philosophy which makes the device suitable for voiceband digital filter applications. Realization of a digital filter requires a linear difference equation for calculating the discrete-time values used for the filtering process, There are a number of established design methods for deriving the required equation via the corresponding Zplane representation of the digital filter transfer function [5-7]. The approach may involve the selection or derivation of a suitable transfer function, G(s), corresponding to an analogue filter which meets the appropriate specification. The digital filter transfer function G(z) is then derived from knowledge of G(s), using s-plane to z-plane mapping.
In some digital filter designs an objective may be to achieve a time-domain specification, in which case the time response of the analogue filter is used as the basis for deriving G(z). This method is suitable if the digital filter is required to have the same impulse-response or step-response as the prototype analogue filter G(s). That is, the s-plane to z-plane mapping is achieved via the corresponding impulseinvariant or step-invariant design methods. A point to note is that for the step-invariant design method, if the analogue prototype filter has fast rise-time and short settling time, these characteristics will be preserved in the digital filter. It should also be noted that for both methods, the frequency response characteristic of G(z) may not match that of G(s), the closeness of the match depends upon the frequency response of G(s) being adequately bandlimited. However, filters are often specified in terms of frequency response characteristics and in many digital filter designs these are the main considerations. In such cases time-invariant design methods are generally not satisfactory. An s-plane to z-plane mapping, which is characteristically bandlimiting in its action, is the bilinear z-transform [8]. This method is easy to apply because it is simply a matter of substituting a function of : for each Laplace operator s appearing in G(s). This is a common approach to digital filter design, and G(s) may be based on prototype Butterworth, Chebyschev, Elliptic or Bessel analogue filters which have the desired frequency-domain characteristics. The transfer function, G(z) of a digital filter may be expressed in the directjbrm as a rational polynominal in z -J, yielding
G(z)
=
Y(z) X(z)
~M
L~=o -
a
iz
i
N ~i=obi z i '
where b0 = 1 and for realisability N >~ M.
(1)
68
R.J. Simpson, T.J. Terrell / Digital Filtering
If the assumption is made that the order of the numerator and the denominator are identical then the corresponding difference equation may be written in the form
N
N
y(n) = ~ aix(n- i ) - ~ biy(n- i). i=O
(2)
i- I
This paper describes how the implementation of this form of linear difference equation may be achieved using the NEC/~PD7720 signal processor controlled by an Intel 8085 host microprocessor system.
2. Chip Architecture The functional block diagram of the ~PD7720 is shown in Fig. 1. The device is fabricated in highspeed NMOS and is a complete 16-bit microcomputer on a single-chip. The device has a 16-bit 2's complement ALU and a separate 16 x 16 bit parallel multiplier, and this combination permits the implementation of a sum of products operation (see equation 2) in a single in-
struction cycle. Data transfer to and from the device may be achieved using the serial or parallel ports. Handshaking signals, including DMA controls, allow the device to act as a sophisticated programmable peripheral as well as a stand alone microcomputer. Memory is divided into three types: Program ROM, Data ROM, and Data RAM. The 512 x 23bit words of Program ROM are adressed by a 9-bit Program Counter, PC, and this can be modified by an external reset, interrupt, call, jump, or return instruction. The Data ROM is organized in 512 x 13bit words and is addressed through a 9-bit ROM pointer, RP, which may be modified as part of an arithmetic instruction so that the next value is available for the next instruction. The Data ROM is used for storing the necessary coefficients, conversion tables and other constants. The Data RAM is 128 x 16-bit words and is addressed through a 7bit Data Pointer, DP, which has addressing features that operate simultaneously with arithmetic instructions. It may be seen from the functional block diagram that the device contains a number of registers, and these hold 16-bit 2's complement data words. Two independent sets of accumulator and flag registers facilitate the arithmetic and logic operations in the
¢K
~AY
.... ~;,.;.-o..oo,.
Fig. 1. Block Diagram of NEC/,tpD7720.
R.J. Simpson, T.J. Terrell / Digital Filtering
instructions set. Multiplication is performed between the K and L registers in every instruction cycle, thereby producing a 31-bit 2's complement result. For this 31-bit result, the sign-bit and the fifteen higher weighted bits are output to the N register (the least significant bit is always set to 0). Under program control, data in a register may be moved (copied) into another specified register or a specified R A M location. Data can also be moved from a specified memory location into a specified register.
Table 1 D e s t i n a t i o n ( D S T ) Field S u m m a r y
DST Field Mnemonic
3. Instructions
There are three types of one word 23-bit instructions which are executed in 250ns when the chip is clocked at 8MHz. Each type is summarised below. 3. l. Load Data Instruction This type of instruction has the format shown in Fig. 2, and it takes the 16-bit value held in the ID field (bits 5 to 20 inclusive) and loads it into the location specified by the DST field (bits 0 to 3 inclusive), see Table 1. It is seen therefore that any specified destination register may be preset with any 16-bit data word. For example the instruction LDI (a RP, 0007H; loads the Data R O M Pointer, RP, immediately with the data word 0007 (hexadecimal), which in this case enables access to R O M Location 007H using subsequent instructions.
This type of instruction has the format shown in Fig. 3. The field specification (bits 13 to 20 inclusive) determines the instruction to be executed, see Table 2. If the instruction is unconditional or the
22
21
I-1
20
19
18
17
16
15
14
(~) (~) (~) (~)
13
12
11
10
9
8
7
6
5
4
,o Fig. 2. Load Data ( L D ) I n s t r u c t i o n F o r m a t
3
2
10
o,,t
Specified Register
D3 D 2 O 1 D O
@NON
0
0
0
0
NO Register
@A
0
0
0
1
ACC A (Accumulator A)
@B
0
0
1
0
ACC B (Accumulator 8)
@TR
0
0
1
1
TR
@DP
0
1
0
0
DP Data Pointer
@RP
0
1
0
1
RP ROM Pointer
@DR
0
1
1
0
DR
@SR
0
1
1
1
SR Status Register
Temporary Register
Data Register
@SOL
1
0
0
0
SO Serial Out LSB
C)
@SOM
1
0
0
1
SO Serial Out MSB
(~)
@K
1
0
1
0
K
(Mult)
@KLR
1
0
1
1
IDB ~ K ROM ~ L
@KLM
1
1
0
0
Hi RAM ~ K IDB ~ L
(~
@L
1
1
0
1
L
(~)
(Muir)
@NON
1
1
1
0
NO
@MEM
1
1
1
1
RAM
Register
LSB is first bit out. MSB is first bit out. Internal data bus to K and ROM to L. register. Contents of RAM address specified by DP 6 = 1 (i.e., 1, DP5, DP4,-DP0) is placed in K register. IDB is placed in L.
specified condition is true, the Program Counter content, (PC), is the address specified by the NA field (bits 4 to 12 inclusive), otherwise (PC) = (PC) + 1. Examples of this type of instruction are (a)
JMP
WAI;
which causes the program to unconditionally jump to the line of program having the lable WAI. (b)
3.2. Jump~Call~Branch
69
JNZBLoop;
which causes the program to conditionally j u m p to the line of program having the lable Loop if the content of accumulator B is non-zero, otherwise the next line of program is executed. The conditional operations depend on the state
22
21
20
19
18
17
16
15
14
13
[,otB.c.I Fig. 3. J u m p / C a l l / B r a n c h
~2
11
10
9
8
7
6
5
4
3
2
] ( J P ) I n s t r u c t i o n Format.
!
0
R.J. Simpson, T.J. Terrell / Digital Filtering
70
Table 2 Condition Field Specification
MSB
LSB
I.o+,.lo, ol .efo A[o.cl.ool.,c BRCH/CND Fields
Mnemonic
D20
O19
D18
D17
D16
D15
D14
D13
Conditions
JMP
1
0
0
0
0
0
0
0
Unconditional
CALL
1
0
1
0
0
0
0
0
Unconditional
JNCA
0
1
0
0
0
0
0
0
CA= 0
JCA
0
1
0
0
0
0
0
1
CA = 1
JNCB
0
1
0
0
0
0
1
0
C8 = 0
JCB
0
1
0
0
0
0
1
1
CB=I
JNZA
0
1
0
0
0
1
0
0
ZA = 0
JZA
0
1
0
0
0
1
0
I
ZA= 1
JNZB
0
1
0
0
0
1
1
0
ZB- 0
JZB
0
1
0
0
0
1
1
1
Z8= 1
JNOVA0
0
1
0
0
1
0
0
0
OVA0 = 0
JOVA0
0
1
0
0
1
0
0
1
OVA0 = 1
JNOVB0
0
1
0
0
1
0
1
0
OVB0 = 0
JOVB0
0
1
0
0
1
0
1
1
OVB0 = 1
JNOVA1
0
1
0
0
1
1
0
0
OVA1 = 0
JOVA1
0
1
0
0
1
1
0
1
OVA1 = 1 OVB1 = 0
JNOVB1
0
1
0 [
0
1
1
1
0
JOVB1
0
1
0
0
1
1
1
1
OVB1 = 1
JNSA0
0
1
0
1
0
0
0
0
SA0 = 0
JSA0
0
1
0
1
0
0
0
1
SA0 = 1
JNSB0
0
1
0
1
0
0
1
0
SB0 = 0
JS80
0
1
0
1
0
0
1
1
SB0 = 1
JNSA1
0
1
0
1
0
1
0
0
SA1 = 0
JSA1
0
1
0
1
0
1
0
1
SA1 = 1
JNSBI
0
I
0
1
0
1
1
0
SB1 = 0
JSB1
0
1
0
1
0
1
1
1
SB1 = 1
JDPLO
0
1
0
1
1
0
0
0
DP L = 0
JDPLF
0
1
0
1
1
0
0
1
DP L = F (HEX}
JNSIAK
0
1
0
1
1
0
1
0
SI ACK = 0
JSIAK
0
1
0
1
1
0
1
1
SI A C K = 1
JNSOAK
0
1
0
1
1
1
0
0'
SO A C K = 0
JSOAK
0
1
0
1
1
1
0
1
SO A C K = 1
JNRQM
0
1
0
1
1
1
1
0
RQM = 0
JRQM
0
1
0
1
1
1
1
1
RQM = 1
of the accumulators' flags, the state of the DP leastsignificant byte, the Status Register RQM-bit (see Fig. 4) or the serial I/O timing signals SI ACK and SO ACK [9]. Each set of accumulator flags (see Fig. 5) are updated at the end of each arithmetic instruction (except NOP). In addition to the Zero Result (ZA/ZB), Sign Carry (SAO/SBO) and Overflow (OVAO/OVBO) flags the 7720 has Auxilary Sign (SAI/SBI) and Auxilary Overflow (OVAI/OVBI) flags. These flags enable detection of an overflow condition and the correct sign is maintained for up to three successive subtractions or additions. When the OVAI (or OVBI) flag is set, the SA1 (SBI) flag
I E, re J o i o f o Io I" I'°J
The status register is a 16-bit register in which the 8 most significant bits may be read by the system's MPU for the latest I/O end processing status. RQM - (Request for Master): A read or write from DR to IDB sets RQM = 1. An Ext read (write) resets ROM = 0. USF1 - (User Flag 1):~ USF0 - (User Flag 0):~
General purpose flags which may be read by an external processor for user defined signalling
DRS - (DR Status):
For 16 bit DR transfers (DRC = 0) DRS = 1 after first 8 bits have been transferred, ORS = 0 after all 16 bits
D M A - (DMA Enable):
DMA = 0 (Non DMA transfer mode) DMA = 1 (DMA transfer mode)
DRC - (DR Control):
DRC = 0 (16 bit mode), ORC = 1 (8 bit mode)
SOC - (SO Control):
SOC = 0 {16 bit mode), SOC = 1 (8 bit mode)
SIC - (5;I Control):
SIC = 0 (16 bit mode), SIC = 1 (8 bit mode)
El - (Enable Interrupt):
El = 0 (interrupts disabled), EI = 1 (interrupts enabled)
P0/P1 (Ports 0 and 1):
P0 and Pl directly control the state of output pins P0 and P1
Fig. 4. Status Register Format and Bit Assignments.
F.AGAISA I SA0ICA I ZA J OVA OVA0 FLAG B
SB1
SB0
CB
ZB
OVB1
OVB0
Fig. 5. Flags for Accumulators A and B.
holds the corrected sign of the overflow. The SGN Register then automatically uses SAI (SBI) to saturate the corresponding accumulator with constants 7 F F F H ( + ) or 8000H(-), which effectively limits a calculated value. It is seen that conditional control of the program may be achieved by testing the state of the appropriate flag(s) in the 7720. 3.3. Arithmetic/Move or Return
This type of instruction has the format shown in Fig. 6. There are two instructions of this type, and both can execute the A L U functions given in Table 3 on the selected ALU input defined by the P-select field (bits 19 and 20), see Table 4(c). The form of the instruction to be executed is defined by the fields sammarised in Table 4(a) to (f). In addition to the ALU operations defined in Table 3 these instructions can also modify: (a) the RAM Data Pointer, DP, (b) the ROM Pointer, RP, and
R.J. Simpson, T.J. Terre# / Digital Filtering
22 21 ]' 20 OP
0 0
RT
01
19
P[ SELECT
18 17 16 15 14 13 12 11 10 9 8 ALU
!
DPL
DPH'M
c°
71
7 6 5 4 3 2 1 0 SRC
DST
Same as OP instruction
Fig. 6. A r i t h m e t i c / M o v e
or Return Instruction
Format•
Table 3 ALU
Field Specification FlagsAffect~
A L U Field Mnemonic
D18 D17 D16 D15
A L U Function
Flag A
SA1 ! SA0
CA
ZA
OVA1 O V A 0
Flag B
SB1
SB0
CB
ZB
OVB10VB0
NOP
0
0
0
0
No Operation
OR
0
0
0
1
OR
X
t
~
t
@
AND
0
0
1
0
AND
X
t
~
t
@
XOR
0
0
1
1
Exclusive OR
X
t
¢
t
0
SUB
0
1
0
0
Subtract
t
t
t
$
$
t
ADD
0
1
0
1
ADD
t
t
t
SBB
0
1
1
0
Subtract with Borrow
t
t
t
t
t
t
ADC
0
1
1
1
Add with Carry
t
DEC
1
O
0
0
Decrement ACC
INC
l
t
t
t
t
$
t
t
t
t
1
0
0
1
Increment ACC
t
t
t
$
CMP
1
0
1
0
Complement ACC (1 's Complement)
X
t
@
t
SHR1
1
0
1
1
1-bit R-Shift
X
t
t
t
SHL1
1
1
0
0
1-bit L-Shift
X
SHL2
I
1
0
1
2-bit L-Shift
X
t t
t @
t t
SHL4 XCHG
1 1
1 1
1 1
0 1
4-bit L-Shift 8-bit Exchange
X
t t
@
t t
X
@
0 0 @ ¢
@
Q ¢
May be affected, depending on the relultl -- Previoui ItltUll can be helj g Rm!
X indefinite
(c) move data (copy) from a source register to a destination register. The difference in the two forms of instructions is that the RT type executes a subroutine or interrupt return at the end of the instruction cycle, but the OP type does not. Examples of typical instructions of this type are given below: (a) OP A D D A C C A , M ; which adds the content of the M-register to the current content of accumulator A and leaves the result in this accumulator (the value in M is preserved). (b) RT D P I N C MOV (~ L , M E M ; which moves (copies) the data R A M location, addressed by the current content of the DP register,
into the L-register, then increments the Data Pointer, DPL, least-significant byte, and then causes a r e t u r n to the main program. (c) OP SHL1 ACCB ; shifts the current content of accumulator B one place left, see Fig. 10(b). It is seen therefore that a useful selection of A L U functions, data moves and memory pointer modifications may be achieved using the multi-operation instructions [9]. F r o m the above it will be appreciated that the 7720 signal processing interface is an advanced-architecture microcomputer having an instruction and register set which provides flexible and relatively fast processing functions, which are suitable for
R.J. Simpson, T.J. Terre#/ Digital Filtering
72
Table 4 OP/RT
Instruction Fields
ASL Field
Mnemonic
DPH-M Field ACC Selection
D14
ACCA
0 1
ACC6
Mnemonic
ACC A ACC B
(a)
I
DPL Field Mnemonic
D13
D12
DPNOP DPINC DPDEC DPCLR
0 0 1 1
0 1 0 1
DP3-DP 0 NO Operation Increment DPL Decrement DPL Clear DPL
Dll
Exclusive OR
D10 D9
M0
0
0
0
(DP6
DP5 DP4) V (0
0 0)
M1
0
0
I
DP6
DP5 DP4 V (0
0
M2
0
I
0
DP6
DP5 DP4 ¥ (0
1 0)
M3
0
I
I
DP6 DP5 DP4 V (0
I
1)
M4
I
0
0
DP6
DP5 DP4 V (1
0
0)
M5
I
0
I
Dp 6 D% DP4 V (1
0
1)
M6
I
I
0
DP6
DP5 0P4 V (1
I
0)
M7
I
I
I
DP6 DP5 DP4 V (1
1
1)
1)
(d)
(b) P Select Field
Mnemonic
020
D19
RAM
0
0
IDB
0
1
ALU Input RPDCR
RAM Internal Data Bus
M
1
0
M Register
N
1
I
N Register
i
Mnemonic
D8
RPNOP
0
RPDEC
1
Operation No Operation Decrement RP
(e)
(c) SRC Field Mnemonic
J
D7 D6 D5 D4
NON
0
0
0
A
0
0
B
0
0
TR
0
DP
Specified Register
0
NO Register
0
1
ACC A (Accumulator A)
1
0
AC C B (Accumulato~ B)
0
1
1
TR Temporary Register
0
1
0
0
DP Data Pointer
RP
0
1
0
1
RP ROM Pointer
RO
0
1
1
0
RO ROM Output Data
SGN
0
1
1
1
SGN Sign Register
DR
1
0
0
0
DR Data Register
DRNF
1
0
0
1
DR' Data No Flag (~
SR
1. 0
1
0
SR Status
SIM
1
0
1
1
SI Serial in MSR (~)
SIL
1
1
0
0
SI Serial in LS8 (~)
k
1
1
0
1
K Register
L
1
1
1
0
L Register
MEM
1
1
1
I
RAM
(~ DR to l o g ROM not set. IN DMA DRO not set. (~) First bit in goes to MSB, last bit to LSB. (~) First bit in goes to LSB, last bit to MSB (bit reversed).
(f)
many digital processing applications. A typical application is destribed below to illustrate the practical considerations necessary for the effective implementation of a digital signal processor using the 7720.
4. System Configuration The 7720 Signal Processor has three communication ports: two serial and one 8-bit parallel, each having their own control signals for interface handshaking modes of operation. For many applications
R.J. Simpson, T.J. Terrell / Digital Filtering
the parallel mode of data transfer is most appropriate because a comparatively higher rate of data transfer is required, and because the acquisition and storage of the sampled-data input samples is often achieved in parallel-byte form. Furthermore, in many cases for flexibility of application it is more appropriate to use the 7720 as a memory-mapped peripheral to a host MPU system. To assit in this respect the 7720 can operate in a parallel communication mode using its compatible Z80, 8085 or 8086 microprocessor bus signals. Also in the parallel mode of operation the processing power can easily be enhanced because the connection of additional 7720s is a straightforward operation, and the associated software modifications generally present no major difficulties. In contrast, enhancements and modifications of serial-based configurations are generally difficult processes. The parallel-based system shown in Fig. 7 was developed by the authors to implement digital filters of the type defined by equation 2. This form of implementation was used because it gives the advantage of comparatively higher data transfer rates and because of the configuration flexibility offered (it is planned to enhance the system to form a bank of 7720 filters controlled by the single host MPU). Referring to Fig. 7 it is seen that the host controller is an SDK85 evaluation system, and it is con-
73
nected to the 7720 so that it may be operated in a handshaking mode. The flowchart pertaining to the 8085 system operation is shown in Fig. 8(a), and that for the 7720 is shown in Fig. 8(b). It may be noted that the 8085 and the 7720 programs may be started independently, but they are linked via the INT interrupt signal and the software set/reset SR flag, which collectively form the handshaking link. Let us consider the basic operation depicted in these flowcharts. This is summarised as follows: (a) assuming that the 7720 has been started, then it will loop around waiting for the INT signal from the 8085. (b) after the three initialisation steps the 8085 sends the INT signal to the 7720, and then generates an A/D convert signal on the PC3 output. The 7720 will then have progressed beyond the operation of resetting the SR flag, and consequently the 8085 will loop around waiting for the SR flag to be set in the 7720. (c) after calculating the y, output value and updating the sampled-data values for the linear difference equation the 7720 sets the SR flag and enters the wait for the 8085 interrupt loop. (d) the above step releases the 8085 from its wait operation, and the computed y, value is transferred from the 7720 to the D/A converter, via the 8085.
Address
FFFO for DR
~!
V2Z--I
[~
I
I
for SR
chip°nd I
Mode
Select
+ 5v Analogue
inpun
l
I
|
7~0 DACK
Analogue
Output
Exr~
|
~----~__
|
(sDx85)
(7720) -D7 RST
/
I
,,
INT lk
Fig. 7. Host MPU Configuration.
R.J. Simpson, T.J. Terrell / Digital Filtering
74
( Start
Ise=
)
Enable 6.5 Interrupt
I Initialise Stack Pointer
I I Wait for A/D Status
Initialise ~/O Ports (Fig.7)
Disable 6.5 Interrupt
Send Interrupt to 7720
Generate A/D Convert
Start
Signal
~6.5Interrupt
t
7720 SR Flag
No
+
xn
Read
1
Write xn to 7720
I
Calculate and Output Yn
t
Update Stored Samples
DR
Read Yn
I Output Yn to D/A
(a)
(b)
Fig. 8. Digital Filter System Flowcharts (a) 8085 and (b) 7720.
(e) Recall that during the execution of steps (c) and (d) above the A / D converter has been obtaining a sample, and the 8085 is now waiting for the status signal on PC2 to signal a 6.5 interrupt. When this is recognised the A / D sends the new input sample, xn, to the 7720 via the 8085. However, to synchronise the data transfer to the correct point in the operation cycle, it was necessary to delay the status signal using the CR differentiating circuit and the monostable circuit.
4.1. System Evaluation Programs may be edited and assembled using an Intel MDS system and subsequently run on an NEC emulator system [10], connected to the SDK85 host system. However, the development of a program depends upon the definition of an appropriate memory map (see Fig. 9) and correct data and coefficient formats. Data from the internal 16-bit data bus of the
R.J, Simpson, T.J. Terrell / Digital Filtering
RP
ao
002
aI
003
a2
004
b1
005
b2
)06
7F80
307
Data R O M
DP xn
OO
Xn_ 1
Ol
Xn_ 2
02
75
mulator B via DR, the high and low bytes of Accumulator B were exchanged, it was shifted one bit right and ANDed with 7F80. These operations are shown diagrammatically in Fig. 10(a). A similar set of operations is required for outputting a 16-bit d a t a word in an unsigned 8-bit format, see Fig. 10(b). The coefficients of the difference equation (2) are stored in Data ROM. Each coefficient is represented by a 13-bit 2's complement binary fraction, but is is stored as a 16-bit word with the least significant 3-bits always zero. The most significant bit of the word is the sign bit. For example, a coefficient of value 0.2066 is represented in binary as 0.001101001110 but is stored as 000110100Ill0000
Data RAM Yn.
03
Yn-i
04
Yn-2
05
(scratchpad)
06
Fig. 9. 7720 Memory Map used for Digital Filter.
7720 is read from or written to external devices in parallel form via the Data Register, D R (see Fig. 1). A control bit in the Status Register is used to define either 16-bit or 8-bit mode of operation of the D R (see Fig. 4). In the 16-bit mode of operation the most significant byte of the internal 16-bit data word of the 7720 is inputted/outputted as a byte of data in the DR and is followed by a second data byte consisting of the least significant byte. In the 8bit mode of operation the least significant byte of the internal 16-bit data word of the 7720 is inputted/outputted as a byte of data. Consequently care must be taken to ensure that the input output format is correct. For example, the A/D converter used by the authors was 8-bit and unsigned. Therefore in order to provide this data as a signed 16-bit word in the 7720, it was inputted in 8-bit mode into Accu-
ie 1A70H The memory map shown in Fig. 9 contains the Data ROM and Data RAM designations for a second-order recursive digital filter. The coefficients in Table 5 characterise a lowpass second-order filter having a cut-off frequency of I K H z operating at a sample frequency of 5 KHz, and derived using the bilinear z-transform method. That is, the linear difference equation for the filter is y,, = 0.2066x, + 0.4131x,,_~ + 0.2066xn 2 + 0.3695yn L 0.1958),,, 2 (3) This design was based on a normalised second order lowpass Butterworth prototype filter [7]. The low-pass performance of the filter was tested using a swept sinusoidal signal over the range 250 Hz to 2500 Hz, which yielded the response shown in Fig. 11. Other responses for second order filters may be readily achieved by substituting the appropriate coefficients in the Data ROM. Furthermore the complexity of the filter may be changed by modification of the 7720 program.
5. Concluding Remarks This paper has attempted to illustrate the main features and characteristics of the 7720 single-chip sig-
76
R.J. Simpson, T.J. Terrell / Digital Filtering Data Bus
XX ............ X I b7 b6 ....... b° I (DR)
I
I XX ............ X b b 6 .........
exchange HI and LO bytes
bol
(ACCB)
I
I b 7 b 6 ........ boJ xx ........... x
(ACCB)
(a)
one bit shift right I b7 b7 b6 ..... bll boXX ......... x
(ACCB)
AND
O 1 1 1
1 1 1 1 I 10 0 0
I
0 b 7 b6 ....... bl I b o 0 0 O
0 0 0 0
[Data Rom 007)
0 O 0 0 I (ACCB)
sign-bit I
Yn
s b 6 b 5 ........ bol
n 7 n6 ........ no
I
(ACCA)
carry-bit
one bit I shift left ~6 b5 ....... bon7 I n 6 n 5 ....... no c I (ACCA)
(b) exchange I HI and LO bytes n 6 n 5 ........ n o cl b6 b5 ....... b°n7 I (ACCA)
I n6 n 5 ..... ..-no c[ b 6 b 5 ....... b o n71 (DR) J
Data Bus
Fig. 10. Eight/Sixteen bit Data Manipulation, (a) input transf'er, (b) output transfer.
R.J. Simpson, T.J. Terrell / Digita/ Filtering Table 5
Coefficient Values for Low-pass Second Order Filter
COEFFICIENT
DECIMAL VALUE
SIGNED HEX VALUE
ao
0.2066
IA70
aI
O.4131
34E0
77
used to assist the reader in quickly and effectively gaining an introduction to the practical aspects of using the 7720 in digital signal processing applications. Readers requiring further information (e.g. program listings) are encouraged to contact the authors.
Acknowledgements
a2
0.2066
IA70
bI
0.3695
2F48
b2
-0.1958
E6FO
The authors wish to express their thanks to NEC Electronics (UK) Limited for supporting the work described in this paper. In particular the authors are indebted to Mr. R. Laird (Applications Manager, NEC) for his invaluable support and co-operation.
References
nal processor connected as a peripheral to an 8085 host microprocessor. It is intended to make the reader more aware of the potential of this singlechip signal processor for digital filtering implementation. A turorial form of presentation has been
[1] T. Nishitani et al., 'A Single-Chip Signal Processor for Telecommunication Applications', IEEE Jour. SolidState Circuits, Vol. SC-16, No. 4, pp 372-376, Aug. 1981. [2] L. Gazsi, 'Single-Chip Filter Bank with Wave Digital
Filters', IEEE Trans. Acoustics, Speech and Signal Pro cessing, Vol. ASSP-30, No. 5, pp 709 71 8, Oct. 1 982.
(b)
(a)
Fig. 11. Practical results (a) low-pass filter output, (b) swept input test signal.
78
R.J. Simpson, T.J. Terrell / Digital Filtering
I'3] G.P. Edwards, 'Programmable Signal Processor LSI rivals Analog Circuit Filters', Electronic Design, pp 1 3 7 140, Feb. 1980. 1'4] B. Secrest et al., 'Speech Analysis and Synthesis becomes practical o n p C Chip', Electronic Design, pp 1 29136, May 1 982. [5] C.M. Rader and B. Gold, 'Digital Filter Design in the Frequency Domain', IEEE Proc., Vol. 55, pp 149-171, 1967. 1-6] A.V. Oppenheim and R.W. Schafer, 'Digital Signal Processing', (Prentice-Hall, Englewood Cliffs, N.J., 1975). [7] T.J. Terrell, 'Introduction to Digital Filters', (Macmillan, London, 1980) 1-8] A. Tustin, "A Method of analysing the behaviour of linear system in terms of time series', J. Instn. Elec. Engrs, 94, Part IIA, pp 130-42, 1 947. i9] NEC pPD7720 Data Document, NEC Microcomputers Inc., 1 981. 1'10] NEC Evakit - 7720PP Users Manual, NEC Microcomputers Inc., 1982 Dr. R o b e r t J. S i m p s o n graduated with a B. Tech honours degree in electrical engineering from Loughborough University of Technology in 1963. He was sponsored by the British Aircraft Corporation (now British Aerospace). Since 1965 he
has been on the staff of Preston Polytechnic, where he is the Reader in Electronic Engineering. In 1969 he received an M.Sc. from Loughborough University for his research thesis, on a.c. control systems, and in 1972 was awarded a Ph.D. by the University of Salford for his research into the identification and control of non-linear systems. In 1979 he was a Visiting Professor at the University of Cape Town, and in 1979-80 and 1984 he was Visiting Professor at Oregon State University, Corvallis, USA. His current research interests include digital signal processing applications. He is a chartered engineer and a Fellow of the Institute of Electrical Engineers. Dr. T r e v o r J. T e r r e l l studied at Preston Polytechnic and in 1965 obtained a Higher National Diploma in electrical engineering. From 1964 to 1967 he was employed as an engineer by the Post Office Engineering Department, London, where he designed telecommuncation networks. In 1967 he joined Mullard Magnetic Components as an electronics development engineer, working on the design of measuring instruments and digital systems. From 1969 to 1 972 he attended the University of Manchester Institute of Science and Technology, obtaining and MSc. degree in 1970 and a PhD degree in 1972. In September 1972 he was appointed as a lecturer in the Electrical Engineering Department of Preston Polytechnic. In September 1974 he was promoted to Senior Lecturer and in May 1978 he was again promoted, this time to Principal Lecturer. Some of his research interests are in the application of microprocessors in digital control systems. Since 1974 he has been a chartered engineer and he is a Fellow of the Institution of Electrical Engineers.
67
Digital Filtering using the NEC/ PD7720 Signal Processor Robert J. Simpson and Trevor J. Terrell Systems and Instrumentation Division, Preston Polytechnic, Preston, PRI 2TQ, England. The concepts of digital filtering using the NEC pPD7720 single-chip digital signal processor are presented. The architecture and instruction formats of the device are summarised. The design philosophy and practical hardware and software considerations of using the 7720 as a peripheral to a host 8085 microprocessor system are discussed.
Keywords: Digital filter, Signal Processor, Chip Architecture, NEC pPD7720, host mpu, system evaluation, mpu, system evaluation, microprocessors.
I. Introduction
In recent years digital signal processing has played a more important role in telecommunication applications. This has occurred due to the increased availability and relatively low cost of LSI chips for system implementation. In many cases the single-chip stored program approach provides a versatile and cost-effective method of implementing real-time digital signal processing operations [1-4]. In particular the NEC/tPD7720 signal processor chip has an architecture design philosophy which makes the device suitable for voiceband digital filter applications. Realization of a digital filter requires a linear difference equation for calculating the discrete-time values used for the filtering process, There are a number of established design methods for deriving the required equation via the corresponding Zplane representation of the digital filter transfer function [5-7]. The approach may involve the selection or derivation of a suitable transfer function, G(s), corresponding to an analogue filter which meets the appropriate specification. The digital filter transfer function G(z) is then derived from knowledge of G(s), using s-plane to z-plane mapping.
In some digital filter designs an objective may be to achieve a time-domain specification, in which case the time response of the analogue filter is used as the basis for deriving G(z). This method is suitable if the digital filter is required to have the same impulse-response or step-response as the prototype analogue filter G(s). That is, the s-plane to z-plane mapping is achieved via the corresponding impulseinvariant or step-invariant design methods. A point to note is that for the step-invariant design method, if the analogue prototype filter has fast rise-time and short settling time, these characteristics will be preserved in the digital filter. It should also be noted that for both methods, the frequency response characteristic of G(z) may not match that of G(s), the closeness of the match depends upon the frequency response of G(s) being adequately bandlimited. However, filters are often specified in terms of frequency response characteristics and in many digital filter designs these are the main considerations. In such cases time-invariant design methods are generally not satisfactory. An s-plane to z-plane mapping, which is characteristically bandlimiting in its action, is the bilinear z-transform [8]. This method is easy to apply because it is simply a matter of substituting a function of : for each Laplace operator s appearing in G(s). This is a common approach to digital filter design, and G(s) may be based on prototype Butterworth, Chebyschev, Elliptic or Bessel analogue filters which have the desired frequency-domain characteristics. The transfer function, G(z) of a digital filter may be expressed in the directjbrm as a rational polynominal in z -J, yielding
G(z)
=
Y(z) X(z)
~M
L~=o -
a
iz
i
N ~i=obi z i '
where b0 = 1 and for realisability N >~ M.
(1)
68
R.J. Simpson, T.J. Terrell / Digital Filtering
If the assumption is made that the order of the numerator and the denominator are identical then the corresponding difference equation may be written in the form
N
N
y(n) = ~ aix(n- i ) - ~ biy(n- i). i=O
(2)
i- I
This paper describes how the implementation of this form of linear difference equation may be achieved using the NEC/~PD7720 signal processor controlled by an Intel 8085 host microprocessor system.
2. Chip Architecture The functional block diagram of the ~PD7720 is shown in Fig. 1. The device is fabricated in highspeed NMOS and is a complete 16-bit microcomputer on a single-chip. The device has a 16-bit 2's complement ALU and a separate 16 x 16 bit parallel multiplier, and this combination permits the implementation of a sum of products operation (see equation 2) in a single in-
struction cycle. Data transfer to and from the device may be achieved using the serial or parallel ports. Handshaking signals, including DMA controls, allow the device to act as a sophisticated programmable peripheral as well as a stand alone microcomputer. Memory is divided into three types: Program ROM, Data ROM, and Data RAM. The 512 x 23bit words of Program ROM are adressed by a 9-bit Program Counter, PC, and this can be modified by an external reset, interrupt, call, jump, or return instruction. The Data ROM is organized in 512 x 13bit words and is addressed through a 9-bit ROM pointer, RP, which may be modified as part of an arithmetic instruction so that the next value is available for the next instruction. The Data ROM is used for storing the necessary coefficients, conversion tables and other constants. The Data RAM is 128 x 16-bit words and is addressed through a 7bit Data Pointer, DP, which has addressing features that operate simultaneously with arithmetic instructions. It may be seen from the functional block diagram that the device contains a number of registers, and these hold 16-bit 2's complement data words. Two independent sets of accumulator and flag registers facilitate the arithmetic and logic operations in the
¢K
~AY
.... ~;,.;.-o..oo,.
Fig. 1. Block Diagram of NEC/,tpD7720.
R.J. Simpson, T.J. Terrell / Digital Filtering
instructions set. Multiplication is performed between the K and L registers in every instruction cycle, thereby producing a 31-bit 2's complement result. For this 31-bit result, the sign-bit and the fifteen higher weighted bits are output to the N register (the least significant bit is always set to 0). Under program control, data in a register may be moved (copied) into another specified register or a specified R A M location. Data can also be moved from a specified memory location into a specified register.
Table 1 D e s t i n a t i o n ( D S T ) Field S u m m a r y
DST Field Mnemonic
3. Instructions
There are three types of one word 23-bit instructions which are executed in 250ns when the chip is clocked at 8MHz. Each type is summarised below. 3. l. Load Data Instruction This type of instruction has the format shown in Fig. 2, and it takes the 16-bit value held in the ID field (bits 5 to 20 inclusive) and loads it into the location specified by the DST field (bits 0 to 3 inclusive), see Table 1. It is seen therefore that any specified destination register may be preset with any 16-bit data word. For example the instruction LDI (a RP, 0007H; loads the Data R O M Pointer, RP, immediately with the data word 0007 (hexadecimal), which in this case enables access to R O M Location 007H using subsequent instructions.
This type of instruction has the format shown in Fig. 3. The field specification (bits 13 to 20 inclusive) determines the instruction to be executed, see Table 2. If the instruction is unconditional or the
22
21
I-1
20
19
18
17
16
15
14
(~) (~) (~) (~)
13
12
11
10
9
8
7
6
5
4
,o Fig. 2. Load Data ( L D ) I n s t r u c t i o n F o r m a t
3
2
10
o,,t
Specified Register
D3 D 2 O 1 D O
@NON
0
0
0
0
NO Register
@A
0
0
0
1
ACC A (Accumulator A)
@B
0
0
1
0
ACC B (Accumulator 8)
@TR
0
0
1
1
TR
@DP
0
1
0
0
DP Data Pointer
@RP
0
1
0
1
RP ROM Pointer
@DR
0
1
1
0
DR
@SR
0
1
1
1
SR Status Register
Temporary Register
Data Register
@SOL
1
0
0
0
SO Serial Out LSB
C)
@SOM
1
0
0
1
SO Serial Out MSB
(~)
@K
1
0
1
0
K
(Mult)
@KLR
1
0
1
1
IDB ~ K ROM ~ L
@KLM
1
1
0
0
Hi RAM ~ K IDB ~ L
(~
@L
1
1
0
1
L
(~)
(Muir)
@NON
1
1
1
0
NO
@MEM
1
1
1
1
RAM
Register
LSB is first bit out. MSB is first bit out. Internal data bus to K and ROM to L. register. Contents of RAM address specified by DP 6 = 1 (i.e., 1, DP5, DP4,-DP0) is placed in K register. IDB is placed in L.
specified condition is true, the Program Counter content, (PC), is the address specified by the NA field (bits 4 to 12 inclusive), otherwise (PC) = (PC) + 1. Examples of this type of instruction are (a)
JMP
WAI;
which causes the program to unconditionally jump to the line of program having the lable WAI. (b)
3.2. Jump~Call~Branch
69
JNZBLoop;
which causes the program to conditionally j u m p to the line of program having the lable Loop if the content of accumulator B is non-zero, otherwise the next line of program is executed. The conditional operations depend on the state
22
21
20
19
18
17
16
15
14
13
[,otB.c.I Fig. 3. J u m p / C a l l / B r a n c h
~2
11
10
9
8
7
6
5
4
3
2
] ( J P ) I n s t r u c t i o n Format.
!
0
R.J. Simpson, T.J. Terrell / Digital Filtering
70
Table 2 Condition Field Specification
MSB
LSB
I.o+,.lo, ol .efo A[o.cl.ool.,c BRCH/CND Fields
Mnemonic
D20
O19
D18
D17
D16
D15
D14
D13
Conditions
JMP
1
0
0
0
0
0
0
0
Unconditional
CALL
1
0
1
0
0
0
0
0
Unconditional
JNCA
0
1
0
0
0
0
0
0
CA= 0
JCA
0
1
0
0
0
0
0
1
CA = 1
JNCB
0
1
0
0
0
0
1
0
C8 = 0
JCB
0
1
0
0
0
0
1
1
CB=I
JNZA
0
1
0
0
0
1
0
0
ZA = 0
JZA
0
1
0
0
0
1
0
I
ZA= 1
JNZB
0
1
0
0
0
1
1
0
ZB- 0
JZB
0
1
0
0
0
1
1
1
Z8= 1
JNOVA0
0
1
0
0
1
0
0
0
OVA0 = 0
JOVA0
0
1
0
0
1
0
0
1
OVA0 = 1
JNOVB0
0
1
0
0
1
0
1
0
OVB0 = 0
JOVB0
0
1
0
0
1
0
1
1
OVB0 = 1
JNOVA1
0
1
0
0
1
1
0
0
OVA1 = 0
JOVA1
0
1
0
0
1
1
0
1
OVA1 = 1 OVB1 = 0
JNOVB1
0
1
0 [
0
1
1
1
0
JOVB1
0
1
0
0
1
1
1
1
OVB1 = 1
JNSA0
0
1
0
1
0
0
0
0
SA0 = 0
JSA0
0
1
0
1
0
0
0
1
SA0 = 1
JNSB0
0
1
0
1
0
0
1
0
SB0 = 0
JS80
0
1
0
1
0
0
1
1
SB0 = 1
JNSA1
0
1
0
1
0
1
0
0
SA1 = 0
JSA1
0
1
0
1
0
1
0
1
SA1 = 1
JNSBI
0
I
0
1
0
1
1
0
SB1 = 0
JSB1
0
1
0
1
0
1
1
1
SB1 = 1
JDPLO
0
1
0
1
1
0
0
0
DP L = 0
JDPLF
0
1
0
1
1
0
0
1
DP L = F (HEX}
JNSIAK
0
1
0
1
1
0
1
0
SI ACK = 0
JSIAK
0
1
0
1
1
0
1
1
SI A C K = 1
JNSOAK
0
1
0
1
1
1
0
0'
SO A C K = 0
JSOAK
0
1
0
1
1
1
0
1
SO A C K = 1
JNRQM
0
1
0
1
1
1
1
0
RQM = 0
JRQM
0
1
0
1
1
1
1
1
RQM = 1
of the accumulators' flags, the state of the DP leastsignificant byte, the Status Register RQM-bit (see Fig. 4) or the serial I/O timing signals SI ACK and SO ACK [9]. Each set of accumulator flags (see Fig. 5) are updated at the end of each arithmetic instruction (except NOP). In addition to the Zero Result (ZA/ZB), Sign Carry (SAO/SBO) and Overflow (OVAO/OVBO) flags the 7720 has Auxilary Sign (SAI/SBI) and Auxilary Overflow (OVAI/OVBI) flags. These flags enable detection of an overflow condition and the correct sign is maintained for up to three successive subtractions or additions. When the OVAI (or OVBI) flag is set, the SA1 (SBI) flag
I E, re J o i o f o Io I" I'°J
The status register is a 16-bit register in which the 8 most significant bits may be read by the system's MPU for the latest I/O end processing status. RQM - (Request for Master): A read or write from DR to IDB sets RQM = 1. An Ext read (write) resets ROM = 0. USF1 - (User Flag 1):~ USF0 - (User Flag 0):~
General purpose flags which may be read by an external processor for user defined signalling
DRS - (DR Status):
For 16 bit DR transfers (DRC = 0) DRS = 1 after first 8 bits have been transferred, ORS = 0 after all 16 bits
D M A - (DMA Enable):
DMA = 0 (Non DMA transfer mode) DMA = 1 (DMA transfer mode)
DRC - (DR Control):
DRC = 0 (16 bit mode), ORC = 1 (8 bit mode)
SOC - (SO Control):
SOC = 0 {16 bit mode), SOC = 1 (8 bit mode)
SIC - (5;I Control):
SIC = 0 (16 bit mode), SIC = 1 (8 bit mode)
El - (Enable Interrupt):
El = 0 (interrupts disabled), EI = 1 (interrupts enabled)
P0/P1 (Ports 0 and 1):
P0 and Pl directly control the state of output pins P0 and P1
Fig. 4. Status Register Format and Bit Assignments.
F.AGAISA I SA0ICA I ZA J OVA OVA0 FLAG B
SB1
SB0
CB
ZB
OVB1
OVB0
Fig. 5. Flags for Accumulators A and B.
holds the corrected sign of the overflow. The SGN Register then automatically uses SAI (SBI) to saturate the corresponding accumulator with constants 7 F F F H ( + ) or 8000H(-), which effectively limits a calculated value. It is seen that conditional control of the program may be achieved by testing the state of the appropriate flag(s) in the 7720. 3.3. Arithmetic/Move or Return
This type of instruction has the format shown in Fig. 6. There are two instructions of this type, and both can execute the A L U functions given in Table 3 on the selected ALU input defined by the P-select field (bits 19 and 20), see Table 4(c). The form of the instruction to be executed is defined by the fields sammarised in Table 4(a) to (f). In addition to the ALU operations defined in Table 3 these instructions can also modify: (a) the RAM Data Pointer, DP, (b) the ROM Pointer, RP, and
R.J. Simpson, T.J. Terre# / Digital Filtering
22 21 ]' 20 OP
0 0
RT
01
19
P[ SELECT
18 17 16 15 14 13 12 11 10 9 8 ALU
!
DPL
DPH'M
c°
71
7 6 5 4 3 2 1 0 SRC
DST
Same as OP instruction
Fig. 6. A r i t h m e t i c / M o v e
or Return Instruction
Format•
Table 3 ALU
Field Specification FlagsAffect~
A L U Field Mnemonic
D18 D17 D16 D15
A L U Function
Flag A
SA1 ! SA0
CA
ZA
OVA1 O V A 0
Flag B
SB1
SB0
CB
ZB
OVB10VB0
NOP
0
0
0
0
No Operation
OR
0
0
0
1
OR
X
t
~
t
@
AND
0
0
1
0
AND
X
t
~
t
@
XOR
0
0
1
1
Exclusive OR
X
t
¢
t
0
SUB
0
1
0
0
Subtract
t
t
t
$
$
t
ADD
0
1
0
1
ADD
t
t
t
SBB
0
1
1
0
Subtract with Borrow
t
t
t
t
t
t
ADC
0
1
1
1
Add with Carry
t
DEC
1
O
0
0
Decrement ACC
INC
l
t
t
t
t
$
t
t
t
t
1
0
0
1
Increment ACC
t
t
t
$
CMP
1
0
1
0
Complement ACC (1 's Complement)
X
t
@
t
SHR1
1
0
1
1
1-bit R-Shift
X
t
t
t
SHL1
1
1
0
0
1-bit L-Shift
X
SHL2
I
1
0
1
2-bit L-Shift
X
t t
t @
t t
SHL4 XCHG
1 1
1 1
1 1
0 1
4-bit L-Shift 8-bit Exchange
X
t t
@
t t
X
@
0 0 @ ¢
@
Q ¢
May be affected, depending on the relultl -- Previoui ItltUll can be helj g Rm!
X indefinite
(c) move data (copy) from a source register to a destination register. The difference in the two forms of instructions is that the RT type executes a subroutine or interrupt return at the end of the instruction cycle, but the OP type does not. Examples of typical instructions of this type are given below: (a) OP A D D A C C A , M ; which adds the content of the M-register to the current content of accumulator A and leaves the result in this accumulator (the value in M is preserved). (b) RT D P I N C MOV (~ L , M E M ; which moves (copies) the data R A M location, addressed by the current content of the DP register,
into the L-register, then increments the Data Pointer, DPL, least-significant byte, and then causes a r e t u r n to the main program. (c) OP SHL1 ACCB ; shifts the current content of accumulator B one place left, see Fig. 10(b). It is seen therefore that a useful selection of A L U functions, data moves and memory pointer modifications may be achieved using the multi-operation instructions [9]. F r o m the above it will be appreciated that the 7720 signal processing interface is an advanced-architecture microcomputer having an instruction and register set which provides flexible and relatively fast processing functions, which are suitable for
R.J. Simpson, T.J. Terre#/ Digital Filtering
72
Table 4 OP/RT
Instruction Fields
ASL Field
Mnemonic
DPH-M Field ACC Selection
D14
ACCA
0 1
ACC6
Mnemonic
ACC A ACC B
(a)
I
DPL Field Mnemonic
D13
D12
DPNOP DPINC DPDEC DPCLR
0 0 1 1
0 1 0 1
DP3-DP 0 NO Operation Increment DPL Decrement DPL Clear DPL
Dll
Exclusive OR
D10 D9
M0
0
0
0
(DP6
DP5 DP4) V (0
0 0)
M1
0
0
I
DP6
DP5 DP4 V (0
0
M2
0
I
0
DP6
DP5 DP4 ¥ (0
1 0)
M3
0
I
I
DP6 DP5 DP4 V (0
I
1)
M4
I
0
0
DP6
DP5 DP4 V (1
0
0)
M5
I
0
I
Dp 6 D% DP4 V (1
0
1)
M6
I
I
0
DP6
DP5 0P4 V (1
I
0)
M7
I
I
I
DP6 DP5 DP4 V (1
1
1)
1)
(d)
(b) P Select Field
Mnemonic
020
D19
RAM
0
0
IDB
0
1
ALU Input RPDCR
RAM Internal Data Bus
M
1
0
M Register
N
1
I
N Register
i
Mnemonic
D8
RPNOP
0
RPDEC
1
Operation No Operation Decrement RP
(e)
(c) SRC Field Mnemonic
J
D7 D6 D5 D4
NON
0
0
0
A
0
0
B
0
0
TR
0
DP
Specified Register
0
NO Register
0
1
ACC A (Accumulator A)
1
0
AC C B (Accumulato~ B)
0
1
1
TR Temporary Register
0
1
0
0
DP Data Pointer
RP
0
1
0
1
RP ROM Pointer
RO
0
1
1
0
RO ROM Output Data
SGN
0
1
1
1
SGN Sign Register
DR
1
0
0
0
DR Data Register
DRNF
1
0
0
1
DR' Data No Flag (~
SR
1. 0
1
0
SR Status
SIM
1
0
1
1
SI Serial in MSR (~)
SIL
1
1
0
0
SI Serial in LS8 (~)
k
1
1
0
1
K Register
L
1
1
1
0
L Register
MEM
1
1
1
I
RAM
(~ DR to l o g ROM not set. IN DMA DRO not set. (~) First bit in goes to MSB, last bit to LSB. (~) First bit in goes to LSB, last bit to MSB (bit reversed).
(f)
many digital processing applications. A typical application is destribed below to illustrate the practical considerations necessary for the effective implementation of a digital signal processor using the 7720.
4. System Configuration The 7720 Signal Processor has three communication ports: two serial and one 8-bit parallel, each having their own control signals for interface handshaking modes of operation. For many applications
R.J. Simpson, T.J. Terrell / Digital Filtering
the parallel mode of data transfer is most appropriate because a comparatively higher rate of data transfer is required, and because the acquisition and storage of the sampled-data input samples is often achieved in parallel-byte form. Furthermore, in many cases for flexibility of application it is more appropriate to use the 7720 as a memory-mapped peripheral to a host MPU system. To assit in this respect the 7720 can operate in a parallel communication mode using its compatible Z80, 8085 or 8086 microprocessor bus signals. Also in the parallel mode of operation the processing power can easily be enhanced because the connection of additional 7720s is a straightforward operation, and the associated software modifications generally present no major difficulties. In contrast, enhancements and modifications of serial-based configurations are generally difficult processes. The parallel-based system shown in Fig. 7 was developed by the authors to implement digital filters of the type defined by equation 2. This form of implementation was used because it gives the advantage of comparatively higher data transfer rates and because of the configuration flexibility offered (it is planned to enhance the system to form a bank of 7720 filters controlled by the single host MPU). Referring to Fig. 7 it is seen that the host controller is an SDK85 evaluation system, and it is con-
73
nected to the 7720 so that it may be operated in a handshaking mode. The flowchart pertaining to the 8085 system operation is shown in Fig. 8(a), and that for the 7720 is shown in Fig. 8(b). It may be noted that the 8085 and the 7720 programs may be started independently, but they are linked via the INT interrupt signal and the software set/reset SR flag, which collectively form the handshaking link. Let us consider the basic operation depicted in these flowcharts. This is summarised as follows: (a) assuming that the 7720 has been started, then it will loop around waiting for the INT signal from the 8085. (b) after the three initialisation steps the 8085 sends the INT signal to the 7720, and then generates an A/D convert signal on the PC3 output. The 7720 will then have progressed beyond the operation of resetting the SR flag, and consequently the 8085 will loop around waiting for the SR flag to be set in the 7720. (c) after calculating the y, output value and updating the sampled-data values for the linear difference equation the 7720 sets the SR flag and enters the wait for the 8085 interrupt loop. (d) the above step releases the 8085 from its wait operation, and the computed y, value is transferred from the 7720 to the D/A converter, via the 8085.
Address
FFFO for DR
~!
V2Z--I
[~
I
I
for SR
chip°nd I
Mode
Select
+ 5v Analogue
inpun
l
I
|
7~0 DACK
Analogue
Output
Exr~
|
~----~__
|
(sDx85)
(7720) -D7 RST
/
I
,,
INT lk
Fig. 7. Host MPU Configuration.
R.J. Simpson, T.J. Terrell / Digital Filtering
74
( Start
Ise=
)
Enable 6.5 Interrupt
I Initialise Stack Pointer
I I Wait for A/D Status
Initialise ~/O Ports (Fig.7)
Disable 6.5 Interrupt
Send Interrupt to 7720
Generate A/D Convert
Start
Signal
~6.5Interrupt
t
7720 SR Flag
No
+
xn
Read
1
Write xn to 7720
I
Calculate and Output Yn
t
Update Stored Samples
DR
Read Yn
I Output Yn to D/A
(a)
(b)
Fig. 8. Digital Filter System Flowcharts (a) 8085 and (b) 7720.
(e) Recall that during the execution of steps (c) and (d) above the A / D converter has been obtaining a sample, and the 8085 is now waiting for the status signal on PC2 to signal a 6.5 interrupt. When this is recognised the A / D sends the new input sample, xn, to the 7720 via the 8085. However, to synchronise the data transfer to the correct point in the operation cycle, it was necessary to delay the status signal using the CR differentiating circuit and the monostable circuit.
4.1. System Evaluation Programs may be edited and assembled using an Intel MDS system and subsequently run on an NEC emulator system [10], connected to the SDK85 host system. However, the development of a program depends upon the definition of an appropriate memory map (see Fig. 9) and correct data and coefficient formats. Data from the internal 16-bit data bus of the
R.J, Simpson, T.J. Terrell / Digital Filtering
RP
ao
002
aI
003
a2
004
b1
005
b2
)06
7F80
307
Data R O M
DP xn
OO
Xn_ 1
Ol
Xn_ 2
02
75
mulator B via DR, the high and low bytes of Accumulator B were exchanged, it was shifted one bit right and ANDed with 7F80. These operations are shown diagrammatically in Fig. 10(a). A similar set of operations is required for outputting a 16-bit d a t a word in an unsigned 8-bit format, see Fig. 10(b). The coefficients of the difference equation (2) are stored in Data ROM. Each coefficient is represented by a 13-bit 2's complement binary fraction, but is is stored as a 16-bit word with the least significant 3-bits always zero. The most significant bit of the word is the sign bit. For example, a coefficient of value 0.2066 is represented in binary as 0.001101001110 but is stored as 000110100Ill0000
Data RAM Yn.
03
Yn-i
04
Yn-2
05
(scratchpad)
06
Fig. 9. 7720 Memory Map used for Digital Filter.
7720 is read from or written to external devices in parallel form via the Data Register, D R (see Fig. 1). A control bit in the Status Register is used to define either 16-bit or 8-bit mode of operation of the D R (see Fig. 4). In the 16-bit mode of operation the most significant byte of the internal 16-bit data word of the 7720 is inputted/outputted as a byte of data in the DR and is followed by a second data byte consisting of the least significant byte. In the 8bit mode of operation the least significant byte of the internal 16-bit data word of the 7720 is inputted/outputted as a byte of data. Consequently care must be taken to ensure that the input output format is correct. For example, the A/D converter used by the authors was 8-bit and unsigned. Therefore in order to provide this data as a signed 16-bit word in the 7720, it was inputted in 8-bit mode into Accu-
ie 1A70H The memory map shown in Fig. 9 contains the Data ROM and Data RAM designations for a second-order recursive digital filter. The coefficients in Table 5 characterise a lowpass second-order filter having a cut-off frequency of I K H z operating at a sample frequency of 5 KHz, and derived using the bilinear z-transform method. That is, the linear difference equation for the filter is y,, = 0.2066x, + 0.4131x,,_~ + 0.2066xn 2 + 0.3695yn L 0.1958),,, 2 (3) This design was based on a normalised second order lowpass Butterworth prototype filter [7]. The low-pass performance of the filter was tested using a swept sinusoidal signal over the range 250 Hz to 2500 Hz, which yielded the response shown in Fig. 11. Other responses for second order filters may be readily achieved by substituting the appropriate coefficients in the Data ROM. Furthermore the complexity of the filter may be changed by modification of the 7720 program.
5. Concluding Remarks This paper has attempted to illustrate the main features and characteristics of the 7720 single-chip sig-
76
R.J. Simpson, T.J. Terrell / Digital Filtering Data Bus
XX ............ X I b7 b6 ....... b° I (DR)
I
I XX ............ X b b 6 .........
exchange HI and LO bytes
bol
(ACCB)
I
I b 7 b 6 ........ boJ xx ........... x
(ACCB)
(a)
one bit shift right I b7 b7 b6 ..... bll boXX ......... x
(ACCB)
AND
O 1 1 1
1 1 1 1 I 10 0 0
I
0 b 7 b6 ....... bl I b o 0 0 O
0 0 0 0
[Data Rom 007)
0 O 0 0 I (ACCB)
sign-bit I
Yn
s b 6 b 5 ........ bol
n 7 n6 ........ no
I
(ACCA)
carry-bit
one bit I shift left ~6 b5 ....... bon7 I n 6 n 5 ....... no c I (ACCA)
(b) exchange I HI and LO bytes n 6 n 5 ........ n o cl b6 b5 ....... b°n7 I (ACCA)
I n6 n 5 ..... ..-no c[ b 6 b 5 ....... b o n71 (DR) J
Data Bus
Fig. 10. Eight/Sixteen bit Data Manipulation, (a) input transf'er, (b) output transfer.
R.J. Simpson, T.J. Terrell / Digita/ Filtering Table 5
Coefficient Values for Low-pass Second Order Filter
COEFFICIENT
DECIMAL VALUE
SIGNED HEX VALUE
ao
0.2066
IA70
aI
O.4131
34E0
77
used to assist the reader in quickly and effectively gaining an introduction to the practical aspects of using the 7720 in digital signal processing applications. Readers requiring further information (e.g. program listings) are encouraged to contact the authors.
Acknowledgements
a2
0.2066
IA70
bI
0.3695
2F48
b2
-0.1958
E6FO
The authors wish to express their thanks to NEC Electronics (UK) Limited for supporting the work described in this paper. In particular the authors are indebted to Mr. R. Laird (Applications Manager, NEC) for his invaluable support and co-operation.
References
nal processor connected as a peripheral to an 8085 host microprocessor. It is intended to make the reader more aware of the potential of this singlechip signal processor for digital filtering implementation. A turorial form of presentation has been
[1] T. Nishitani et al., 'A Single-Chip Signal Processor for Telecommunication Applications', IEEE Jour. SolidState Circuits, Vol. SC-16, No. 4, pp 372-376, Aug. 1981. [2] L. Gazsi, 'Single-Chip Filter Bank with Wave Digital
Filters', IEEE Trans. Acoustics, Speech and Signal Pro cessing, Vol. ASSP-30, No. 5, pp 709 71 8, Oct. 1 982.
(b)
(a)
Fig. 11. Practical results (a) low-pass filter output, (b) swept input test signal.
78
R.J. Simpson, T.J. Terrell / Digital Filtering
I'3] G.P. Edwards, 'Programmable Signal Processor LSI rivals Analog Circuit Filters', Electronic Design, pp 1 3 7 140, Feb. 1980. 1'4] B. Secrest et al., 'Speech Analysis and Synthesis becomes practical o n p C Chip', Electronic Design, pp 1 29136, May 1 982. [5] C.M. Rader and B. Gold, 'Digital Filter Design in the Frequency Domain', IEEE Proc., Vol. 55, pp 149-171, 1967. 1-6] A.V. Oppenheim and R.W. Schafer, 'Digital Signal Processing', (Prentice-Hall, Englewood Cliffs, N.J., 1975). [7] T.J. Terrell, 'Introduction to Digital Filters', (Macmillan, London, 1980) 1-8] A. Tustin, "A Method of analysing the behaviour of linear system in terms of time series', J. Instn. Elec. Engrs, 94, Part IIA, pp 130-42, 1 947. i9] NEC pPD7720 Data Document, NEC Microcomputers Inc., 1 981. 1'10] NEC Evakit - 7720PP Users Manual, NEC Microcomputers Inc., 1982 Dr. R o b e r t J. S i m p s o n graduated with a B. Tech honours degree in electrical engineering from Loughborough University of Technology in 1963. He was sponsored by the British Aircraft Corporation (now British Aerospace). Since 1965 he
has been on the staff of Preston Polytechnic, where he is the Reader in Electronic Engineering. In 1969 he received an M.Sc. from Loughborough University for his research thesis, on a.c. control systems, and in 1972 was awarded a Ph.D. by the University of Salford for his research into the identification and control of non-linear systems. In 1979 he was a Visiting Professor at the University of Cape Town, and in 1979-80 and 1984 he was Visiting Professor at Oregon State University, Corvallis, USA. His current research interests include digital signal processing applications. He is a chartered engineer and a Fellow of the Institute of Electrical Engineers. Dr. T r e v o r J. T e r r e l l studied at Preston Polytechnic and in 1965 obtained a Higher National Diploma in electrical engineering. From 1964 to 1967 he was employed as an engineer by the Post Office Engineering Department, London, where he designed telecommuncation networks. In 1967 he joined Mullard Magnetic Components as an electronics development engineer, working on the design of measuring instruments and digital systems. From 1969 to 1 972 he attended the University of Manchester Institute of Science and Technology, obtaining and MSc. degree in 1970 and a PhD degree in 1972. In September 1972 he was appointed as a lecturer in the Electrical Engineering Department of Preston Polytechnic. In September 1974 he was promoted to Senior Lecturer and in May 1978 he was again promoted, this time to Principal Lecturer. Some of his research interests are in the application of microprocessors in digital control systems. Since 1974 he has been a chartered engineer and he is a Fellow of the Institution of Electrical Engineers.