Digital measurement of the mass-flow rate

ELSEVIER

Sensors and Actuators A 45 (1994) 139-143

Digital measurement of the mass-flow rate Saleem M.R. Taha Depamnent

of Electrical

Engine+

CoUegeof Engineering, Urnher& of Baghda4 Baghdad Iraq

Received 21 September 1993;in revised form 27 May 19% accepted 21 June, 1994

Abstract

This paper introduces the design and implementation of a gas mass-flow rate digital meter. It employs hybrid processor circuitry in such a way that the output is displayed digitally through a novel dual-slope-type non-linear analogue te digital conversion (ADC). An analogue output mass-flow rate measurement is also obtainable. Linear and digital ICs have been used in this circuit. The accuracy of measurement is better than 0.5%. zCeyxw& Digital measurements; Mass-flow rate meter

1. Introduction

The measurement of gas mass-flow rate has become of great importance in a large number of industrial processes, particularly in chemical engineering, where the flow has to be monitored at various places during a certain controllable process. The relationship between the mass-flow rate (m”) and the volumetric flow rate (Q) is [l] m”=pe where p is the gas density. The differential pressure AP produced across an orifice plate (see Fig. 1) is given as APapQ2 However, p is determined by measuring the gas static pressure P, and static temperature T,, where

Therefore,

b2 mea

$P ( *

1

This method of measurement assumes a constant coefficient of discharge and expansion ratio for the orifice plate. It is based on Bernoulli’s equation for subsonic flow. This paper describes a digital gas mass-flow rate meter where: (1) a gas static-pressure transducer is

0924-4247/94/307.00 8 1994 Elsevier Science S.A. All rights reserved SSDI 0924-4247(94)00825-3

used to develop a voltage V, proportional to P,; (2) a static-temperature transducer is used to develop a voltage V, proportional to T,; and (3) a voltage V, is developed by the orifice plate to represent the pressure drop hp. These voltages are processed through a hybrid processor that gives a digital output reading proportional to the mass-flow rate (MFR) of the applied voltages. Hence, the system could be calibrated to give the MFR value directly in kg s-l. An analogue output is also obtainable. Other alternatives for realizing the MFR of the input voltages could be analogue methods to be implemented before analogue to digital conversion @DC!), or digital methods to be implemented after linear ADC (i.e., first converting the input voltages to their digital equivalent, and then using PROM look-up tables to calculate their MFR value). A technique that is based on a squareroot non-linear triple-slope ADC to calculate the MFR value is described elsewhere [2], but its accuracy and speed of measurement are slightly less than that of the system described here. In this paper a new hybrid processor is described in which the MFR value of the input voltages is obtained implicitly during the ADC process. 2. Operation of the circuit Fig. 1 shows the block diagram of the digital MFR meter. Initially three voltages V1, V2 and V, are developed from the three transducers used to measure

S.hf.R

140

Taho I Sensors and Actuators A 45 (1994) 139-143

Fig. 1. Block diagram of the dikitai gas mass-flow rate meter.

I

0

,

1

M I

I

Now, the operation is repeated, but the output of the DAC after being integrated by the integrator 12 is taken as the input to the integrator Il. The integrator 12 output ramps down due to the positive input. This is compared with the zero level by means of the comparator C2. Hence the output of C2 changes state from low to high, causing the counter to be reset at the beginning of the second cycle of operation. The output of 11 is compared with Vrcpby means of the comparator Cl; which enables the AND gate, allowing clock pulses of constant frequency to be applied to the counter. The comparator Cl inhibits the AND gate when the 11 output reaches V,, and the counter is stopped at the last count. This count, which represents the MFR value of inputs VI, V, and V,, is displayed by a display unit and converted to the analogue equivalent by the DAC. Hence, the output is obtainable in digital or analogue form. What follows is the mathematical derivation of the system that gives the relation between the final count N of the counter and the analogue inputs VI, V, and V3. Fig. 3 shows the complete circuit of the system. During the period I,, to tl, V,, (after being inverted) is applied to the integrator 11, while V, is applied to the VFC circuit. Hence,

Fig. 2. Block diagram of the hybrid processor.

AP, P. and T,, respectively. These analogue voltages are processed through a hybrid arrangement that makes use of digital circuits. Fig. 2 shows the hybrid processor in block-diagram form. Its digital output represents the MFR value of the applied voltages. The hybrid processor works as follows: a reference voltage v-f, after being reversed to ( - J&r), is applied to the integrator 11,while the input voltage V, is applied to the voltage-to-frequency converter (VFC). V,, and V2vary slowly with time. The integrator I1 output ramps up due to the negative input (-I’&. This is compared with the zero level by means of the comparator Cl, which enables the AND gate preceding the counter to operate; the VFC output frequency, which is proportional to V2, is applied to the counter. This situation continues until the counter reaches full scale (i.e., after 2”-- 1 counts, where n is the number of stages of the counter). Now, the input voltage V, is applied to the integrator and V3 to the VFC. The integrator output ramps down due to the positive input V,, and the VFC produces an output frequency proportional to V,. The comparator Cl inhibits the AND gate when the integrator output reaches zero, and the counter is stopped at the last count. This count is then stored by a latch circuitry whose output is applied to a digital-to-analogue converter (DAC).

=

$(rl-ro)

But t,-r,=N,f where NO=2” - 1, n = number of bits of the counter and f= the counter clock frequency. Therefore

But during the period (rl -to) f is proportional Hence, A@,)=

to VP

NoV,,r K,RC V,

where Kf is the proportionality constant of the WC. During the period t1 to rz (see Fig. 4), V, is apljlied to the VFC circuit while V, is applied to the integrator Il. Hence,

A@,)-A(t,)+

2

J, II

Therefore

dr=o

S.M.R Taha / Senwrs and Actuators A 45 (1994) 139-143

141

Fig. 3. Complete schematic diagram of the system.

(2) But NOand Vrcrare constants. Therefore Eq. (2) becomes (3) ’ i

I

;

where 4 = N&L) Now, N1 is converted to its analogue equivalent by a DAC circuit as shown in Fig. 3. The analogue output of the DAC (0) is applied to the integrator 12 during the period t2 to &. Hence

Fig. 4. The timing diagram.

4,) = g oz-td

(1)

But tz-tl=NJf where N1 is the digital count of the ‘counter at time rz, and f is proportional to I’, during the period (tz i tl). Substituting the values of (tz-tl) and A(t,) into Eq. (1) yields

N,Vrc, -=_

NI h

K,RC V,

&RC V,

Hence,

= g

(t,-t,)

The integrator I2 output (E) is fed back to the input and a new cycle starts with E applied to the integrator II at this time. If the same mathematical analysis is applied to ‘the second cycle, the following relationships are obtained: (4)

&s

(f3-t2)2=Kef

142

S.M.R Taha I Sensors and Achuztom A 45 (1994) 139-143

Eq. (9) showsthe relationship between the digital output (N) and the inputs V,, V2and V,, from which a digital number proportional to the MFR value of the inputs could be obtained by the circuit. But V,, V, and V3 are proportional to A?‘,P. and T,, respectively. Therefore, the system could be calibrated to give the MFR value directly.

Also, it is applied to close switches S5 and S6 to reset the integrators 11and 12.The types of analogue switches used are such that logic ‘one’ closes the switch, while logic ‘zero’ opens it. Hence the application of the start pulse will cause waveforms X and L to be high (see Fig. 4). Hence switches Sl, S2, S3 and S4 are turned to positions 1. Consequently V,,, is integrated after being inverted and V2is applied to the VFC, which gives a frequency proportional to V,. The output of the integrator 11 is an increasing ramp. Hence the output of the comparator Cl (zero detector) is high, enabling the AND gate preceding the counter to operate and the counter to start counting. This condition is maintained during the period to to t,. At t=tl, the counter reaches the full-scale count, and on the next clock pulse the counter is cleared. Hence, the most significant bit (MSB) changes state from high to low at t= tl causing the waveform X to change state from high to low; therefore switches Sl and S2 are turned to position 2. Now, V, is applied to the VFC, while VI is applied to the integrator 11 and its output is a decreasing ramp. The counter continues counting until the output of the integrator 11 at t = tz becomes zero. The output of the comparator changes state from high to low, causing switches S3 and S4 to be turned to position 2, and S6 to be opened. Also, the monostable is triggered, giving a pulse S at its output, and waveform M is changed from high to low, triggering the latch circuitry and allowingthe count of the counter at t=t2 to be changed to its analogue equivalent by the DAC. Then the second cycle of operation is started, but this time the output of the integrator 12 is used as the input to the integrator Il. The output of the integrator I2 is a decreasing ramp. The output of the comparator C2 changes state from low to high at t = tz, causing the counter to be reset at the beginning of the second cycle of operation. Now, the output of integrator I1 (A) is compared with VEp At t = t,, A reaches the voltage level V,, and the second cycle is finished. Hence, waveform M changes state from high to low, giving a trigger to the latch circuit, and therefore the counter contents at the end of the second cycle are displayed. This count is an indication of the MFR value, as is shown in the previous section. Its analogue equivalent is also available at the output of the DAC. Fig. 4 shows the timing diagram of all the circuit’s waveforms discussed above.

3. Complete circuit design

4. Results and discussion

Fig. 3 shows the complete circuit of the system, which operates as folIows.The start pulse is applied to clear the counter, the latch circuit and the two D flip-flops.

A measuring technique for obtaining the MFR value has been described. In this technique three voltages proportional to differential pressure, static pressure and

But t,-fz=Nlfc where N is the digital count of the counter at the end of the second cycle (i.e., at time t3) and fe is the clock frequency. Substituting the values of (t3- tJ into Eq. (4) yields

--D N2=v 2W)z

0 fc

r.9

Hence, N=RC(fc)(2Vxf/D)‘”

(5)

But R, C, fc and V,, are constants. Therefore Eq. (5) becomes l/Z

(6) where &=RC(f,)(2V,S’” But D =&(N,)

(7)

where K3 is the DAC proportionality constant. Substituting Eq. (3) into Eq. (7) yields (8) Substituting Eq. (8) into Eq. (6) yields

or (9) where K = KJ(K,K,)‘”

S.M.R Taha I Sensors and Actuators A 45 (1994) 139-143

static temperature of a gas-flow arrangement are applied to a hybrid processor, which produces a digital number proportional to the MFR value of the applied voltages. An analogue output is also obtainable. Fig. 5 shows the practical relationship between the input voltages and the digital output. The accuracy of measurement is around 0.3% for the digital output and 0.5% for the analogue output. In fact, the technique used is an adaptive form of the dual-slope ADC. Examples of the advantages of this type of conversion are the excellent noise rejection, high accuracy and linearity. Linear and digital ICs have been used in this circuit. The most important advantage of this circuit is that an accurate gas MFR measurement could be obtained in two forms, analogue and digital. The speed of the system is slow, since the method of analogue-to-digital conversion uses integration. The accuracy of measurement depends mainly on the inherent f1/2 least significant bit (LSB) of the DAC, Oigito1 Output N

Fig. 5. Experimental

resultsof the MFR meter.

together with the offsets of the operational comparators and switches.

143

amplifiers,

Acknowledgement The author wishes to thank Mr Amer Estephan for his kind help in preparing the original Figures for this paper.

References [l]

B.E. Jones, Inshwnentations, Meas-enr and Feedback McGraw-Hill, 1977. [2] B.A. Hafeth and M.A.H. Abdul-Karim, Digital mass flow rate meter using square-root analogue to digital converter, ht. X Electron., 57 (1984) 745-753.

Saleem MR. Tab was born in Baghdad, Iraq, on May 21, 1956. He received the B.Sc degree in electrical engineering with elective courses in computer science, the Higher Diploma degree in electronics and communications and the M.Sc. degree in digital electronic systems from the University of Baghdad, Baghdad, Iraq, in 1978, 1980 and 1982, respectively. From October 1978 to May 1982, he worked with the State Organization for Technical Industries (SOTI), Baghdad, Iraq. From June 1982 to April 1983, he was with the (SOTI) computer centre. In May 1983 he joined the Department of Electrical Engineering, College of Engineering, University of Baghdad, as assistant lecturer and then in May 1986 he became a lecturer. Since September 1989 he has been an assistant professor at that university. He has contributed to and written many papers in the areas of hybrid circuit design, digital signal processing, digital measurements instrumentation, microcomputer applications, computer-aided design, computer simulation and biomedical engineering.

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