Digital system simulation with VHDL in a high-level synthesis system

Microprocessinoand M[croprograrnming35 (1992) 263-270 North-Holland

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Digital System Simulation with VHDL in a High-level Synthesis Sys~n Zebo Peng Dept. of Computer and Information Science Link~ping University S-581 83 Linktping, Sweden E-mail: [email protected] This paper presents the use of VHDL to simulate the intennediato design repmsentafinn in a high-level synthesis system. The design representation is captured by an extended time Peui net notation and is used throughout the synthesis process. We have developed an algorithm to convert the design representation into a VHDL description. As a result, digital system designs can be simulated together with the behavioral models of the primitive register-ffansfer level components which are also described in VHDL. The main feature of our appmanh is that the intermediate results (as well as the final results) of the high-level synthesis process can be simulated at any time and the simulation results can be used to guide the synthesis process.

l . Introduction A high-level synthesis system takes an abstract behavioral specification as input and generates an implementation structure at register-wansfer level as output. The VHDL language [VHDL 87], with its rich functionality and multi-level description capability, has been used for many different purposes in high-level synthesis. It has been used, for example, to capture the input specification [Cam 91] and [Pus 91], to model the designs at varying levels ILls 89], and to perform design simulation [Ber 91]. In this work, we have addressed the problem of how to use VHDL to simulate the intermediate design representations of the high-level synthesis process. This work has been carded out with the continuous development of the CAMAD synthesis system [Pen 89]. The current ve~'sico of the CAMAD system takes a high-level algorithmic specification and gune, stes a net-list description of the data path as well as a microprogrem for the controller. The net-list description specifies the primitive components of a design as well as their connections. The components arc defined by a component (module) library which consists of all available components (modules) and This research has been supported by the Swedish National Board for Industrial and Technical Development (NUTEK).

their parameters, such as estimated layout area and typical timing information. Most of other high-level synthesis systems use a flat list of infonnal descriptions of components. In our approach, VHDL is used to specify both the functionality and the implementation attributes of the components. As a result, a hiera~hical organization of the components is obtained, components with many different levels of granularity can exist simultaneously in the lilraryo and automatic selection of components during the synthesis process is made possible. One of the main objectives of the cunent work is to make it possible to simulate intermediate as well as final designs of the high-level synthesis process so that the behavior of a design can be verified at an ear_ ly design phase and at the same llme the simulation results can be used to guide the synthesis process. To achieve this, the intermediate design mpresentati~ of CA_MAD is automatic~ly converted into an eqnivalent VHDL description, which is then simulated with behavioral models of the prinfitive components and the user-specified input stimuli using existing VHDL simulation tools. Since the design relm~entafion of CAMAD is used throughout the whole synthesis process, both intermediate and final results of CAMAD can be simulated using the same mechanism/tool and mniti-level simulation is achieved. Related work in this area, on the other hand, usually uses different models/methods to simulate the different levels/domains of designs and therefore the siren-

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ladon results aa¢ sometimes difficult to be interpreted and comperecL With our approach, it is very stJaightforward to interpret and use the simulation results since they are all referred to the same design representalion model. The rest of this paper is organized as follows. Section 2 presents an overvi¢=~ of the CAMAD high level synthesis system tugethur with a d~;scussion of how the VHDL simulator interacts with the other tools. We describe then the use of VHDL to capture the somandct of the basic register-transfur level compononts in ~ecfion 3. The algorithm used to convert the design representalion of CAMAD into a VHDL description is presented in section 4, where the use of a VHDL simulator to simulate the design representation is also described. We finish the paper with a final discussion and a short summary of the results in section 5. 2. The CAMAD High-Level Synthesis System The CAMAD system is built on top of a unified design representation model used to capture the design (or partial design) during the high-level synthesis process. This design representation is based on an extended timed Petei net description (the ETPN model) which consists of separate but related models of conIrol and data path [Pen 88]. The data path of ETPN is ~prcscntod as a directed graph with nodes and arcs. The nodes am used to capture data storage and ntadipuladon units and the arcs represent the conneclions of the nodes. The control part of ETPN, on the other hand, is captured as a timed Petri net with restricted transilion firing rides. A very simple example of ETPN is illustrated in Fig, 1. Fig. l(b) shows the data path where each data path node is depicted as a rectangle with a label iedicadng the basic operation of the node. The arcs of the dam path represent the data flow between the nodes. Flow of data from one node to another is controlled by the control signals coming from the control part. The control relation is indicated by using control place names to guard the arcs. Fig. l(a) dcpicb; the Pelri net which represents the control flow ~,f ~he example. A control state is represented as a marking of the Petri net. i.e., the possession of token~ i- a subset of the places of the Pctri net which am depicted as circles. The wansilions of control states are represented as firings of one or several transitions of the Petri net

(to)Dauapath BEGIn COHEGIN X : = i; Y := 0; :OEND: WHILE X • 0 DO (a) Control Petal net BEGIN R e a d (X} ; Y : - Y + X; END~ (C) A D D L description ~¢rlt.e(Y) BleD.

/PO/ Ip?/ /P2/ /P3/ /P4/

/PS/ /P6/

/el/

Fig. 1 An example of the ETPN representations and its corresponding ADDL description

which are depicted as bars. This ETPN example is generated by CAMAP as the compilation output of the input ADDL specification given in Fig I(c). The main feature of the ETPN design representation is its ability to capture the intennediata result of a design explicitly so as to allow the design algorithm to make accurate design decisions. For example, if sow oral operations am not data-dependent and can thus be executed concurrently, the situation can be captured precisely by giving their associated contrul places in the Petri net a potential to hold tokens sintultaneoasly. That is, the set of Pctri net places corresponding to the operations will not have any partial ordering relation between them. Fur example, in Fig. 1, P2 and P7 control the loading of initial data to register X and Y respectively, which am independent operations. Therefore. P2 and P7 can hold token simultaneonsly. When it is, however, discovered later that the potential parallelism will not be able to be implemented, some partial ordering relations can be introdaced into the set of Petri net places by performing a place-stretch transformation [Pen 89]. As in the above example, if both register X and Y are loaded via !/O pins and it is too expensive to implement two set of I/O pins. P2 and P7 can be stjre~ched so that e.;tiler P2 will follow P./or vice versa and thus only one set of 1/0 pins will be needed.

Digital system simulation with VHDL

In general, given an intermediate synthesis result represented in the ETPN form, an algorithm can be used to calculate, for example, its implementation cost. check whethei" the cost satisfies the design constraints, end automatically choose a transformation to apply to "he design to produce another intermediate result witll imla~oved outcome. CAMAD utilizes such an iterafive transformation alp preach to carry out the synthesis tasks. That is, it first generates a preliminary (default) design from the input specification which is v,qritten in the ADDL language (Algorithmic Design Description Language, a subset of PASCAL with several extensions to capture parallelism and hardware specific operations), h then applies design transformations one by one to the preliminary design so as to obtain better results. These t~ansformations deal with design decisions concerning operation scheduling, data path/enntrol allocation, or optimization of tim currant design. This iterative process is finished when a satisfactory resuR has been reached. The data path is then transformed into a net-list and the control part into a microprogram. The netlist and the microprogram together form the RT-level implementation of the input specification. This process is iliostx-ated in Fig. 2. With the development of the VHDL simulator de. sefibed in this paper, k is possible to simulate the iatermediate as well as the final results of CAMAD, as indicated in Fig. 2. The simulation of a design is

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ochieved by converting the ETPN description into a VHDL program and li.n~ltingit with the basic cmnlmaent descriptions which are also specified by After the design is simulated with some usor-spcctfled input stimuli (which usually concspoods to the . ~ c ~ input dam of the designed system), the sinmlation results can then be i n t e r p m ~ by the designers and used to interacfively ~ the design lrmsf~mations using the interactive mode of the CAMAD system [Pen 89]. For example, if the lx~rformmme of a given critical path of the current ET1'N design cannot satisfied the given design cousWamt, the designers can iusuuct CAMAD to select performance improvement transformations to apply to the related data part of the design. This can he easily done by indicating to CAMAD the re/ated critical path and/e~ring CAMAD to use performance as the first critesion for selecting wansformatioos [pen 89]. 3. Component Descriptions with VHDL in order for CAMAD m make accurate simulation of an ETPN design so as to estimate, for example, its performance in respect to two given states, ~ c.omportent library which consists of all ~ available lmsic componenls must provide information about different parameters (attributes) of the componem~. More importantly, the component library must con= taln semantics information of the components so that

L

Fig, 2 The hi&h4~¢~lSyathesis Process of CAMAD

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the syn~esis algorithms know precisely what the functions of the different components are and how to simulate them. Previous work has used either a procedural representation of the component library where the componel:t specification is embedded in the algorithms, or a very simple declarative structure of components of a single technology. The current work enhences declarafive representation of multiple-technology component library and its integration into the synthesis procuss. It improves also the flexibility of the CAMAD system as the VHDL component specifications are of any specific technology or vendor.

components. That is, instead of using a behavioral specification for its semantics, each high-level component is specified by an architecture body which describes the basic components used to implement the high-level component. As a result, the semantics of a high-level component is deduced directly from its implementation. Therefore, modification of a basic component will be immediately reflected on all of the high-level components which use it as building blocks and the hierarchical organization of the components is clearly identified. However, this approach entails extra time on simulation. 4. VHDL Generation and Simulation

Each component of the CAMAD component library is described by a VHDL entity. The entity declaration specifies the name and the input/output port structure of the component together with possible parameterLred information. An architecture body is used to specify file semantics of the component. The following example illustrates the specification of the basic semantics of a combinational component. entity Addl6 is port(Ipl, Ip2 : in Unslgnedl6; --inputs Opl : Out Unsignedl6); -output end Addl 6; architecture behavior of Addl6 is

begin opl
In the above example, since the ADDI6 component is t,he basic component, its semantics is given directly by a behavioral specification. For combinational components such as ADDI6. the simple data flow style of V H D specification is used. In the case of seqnnntial components, block statements are used to specify Ilheir behavior, such as in the next example. entity ReglS is porttIpl : i.~ Unsigned16; --input It1 : in Bit : - ,0,; --load control Opl : Out Unslgnedl6); --output end Begl6;

- - falling-edge triggered register architecnure behavior of neglS is begin FE : blo=k (IcI"EVENT and It1-'0') begin Opl
The main use of the VHDL language in this work is m provide a simulation platform for verification of the design and extraction of design attributes at different design stages. CAMAD generates a stmctura', description in VHDL format of the ETPN data pPal at any moment daring the synthesis process upon request. The control Petri net, on the other hand, will be first converted into a mic~program and then coded into the VHDL form as a finite state machine (FSM) description. The generated VHDL description can then be simulated together with the component descriptions and the user-specified input stimuli. The generation of the ETPN data path description is very sn'aightforwerd. Each type of the components used in the data path will have a corresponding VHDL component declaration in the generated VHDL description. The arcs connecting data path nodes in the ETPN description will be declared as signals and the connection information is captured by the component instanfiation statements. Fig. 3 shows the VHDL code generated by CAMAD for the ETPN example given in Fig. 1. Note that two multiplexors have been introduced by CAMAD due to that beth register X and Y have two sources of inputs. The generation of the control Petri net description in VHDL, on the other hand, is done in two steps. In the first step, the timed Petri net is converted into a finite state machine description by assuming an as-soon-aspossible firing rule [Kuc 87]. The FSM description is captured as a directed graph w~'h nodes representing FSM states end ares state transitions. A state denotes a reachable marking of the control Petri net, Le., a set of Petri net places which hold tokens at the same time and consequently their associated operations will be performed szmultaneously. When these operations

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Digital systam simulation with VHDL use W o r k . E T P N ~ d e l l l n g . a l l ; entity AccumTs poxt ( P N1 : in ffnsignedl6: -- input P--N2 : out Unsignedl6; -- output C l o c k : in Bit :- "0'): -- c l o c k end; architecture structure of A c c u m is -- signals for cunnection points signal N A1 : Unsigned16; signal N A2 : Unslgnedl6; signal N--A3 : Unslgnedl6; signal N--A4 : Unsigned16; signal N--A5 : unsignedl6; signal N--A7 : Unslgnedl6; signal N--All : Unsignedl6; signal N--At2 : Unsignedl6; signal N--At3 : Unsigned16; -- control slgnals f r o m the Petri net slgnal P0, P1, P2, P3, P4, P5, P6, PT, P2_P5, P4_P7 : B i t :- "0'; -- c o n d i t i o n signals f r o m the d a t a p a t h signal CI : Bit := 0; -- d a t a p a t h c o m p o n e n t types component Pad16 -- I / O p i n port ( Ipl : in Unslgned16; -- input Opl : out unsigned16); -- output e n d component; component Regl6 -- register port ( Ipl : in Unslgnedl6; -- input It1 : in Bit; -- l o a d control Spa : out unslgned16); -- output e n d component; component C o n 1 6 -- constant g e n e r i c (D_value : U n s i g n e d l 6 := 0); port ( 0pl : out unsignedl6); -- output e n d component; c o m p o n e n t qtn16 -- greater t h a n comp. port ( Ipl, Ip2 : in Unsignedl6; - - input Opl : OUt Bit}; -- output e n d component; c o m p o n e n t Add16 -- additioB port ( Ipl, Ip2 : in Unsigned16; -- input 0pl : out unsignedl6); -- output e n d component; component M U 1 1 6 _ 2 -- 2-input m u l t i p l e x o r port ( Zpl, Ip2 : in gnsigned16~ -- input Icl, It2 : in Bit; -- selection Opl ; out Unsigned16|; -- output e n d component; data p a t h component configuration for NI, N2 : Padl6 u s e e n t i t y Work.Pad16(behavior); for N3, N4 : Regl6 u s e e n t i t y Work.Reg16(behavior) 1

for N5, NT, Nll ; Con16 use e n t i t y W o r k . C o n 1 6 (behavior) ; for N 6 : G t n 1 6 use e n t i t y W o r k . G t n l 6 (behavior) ; for N8 : A d d l 6 u s e e n t i t y W o r k . A d d l 6 (behavior) ; for NI2, N 1 3 : M u l l 6 2 u s e e n t i t y W o r k . M u 1 1 6 2 {behavior) ; -- F S M state d e c l a r a t i o n t y p e State type is (SI, $2, S3, 54, 55, $6, 57) ;

begin -- c o m p o n e n t i n s t a n t i a t i o n N1 : P a d l 6 port m a p (P_NI, N_A4) ; N2 Pad16 p o r t m a p (N A5, P_N2); N3 :: R e g 1 6 p O E t m a p (N_--AI2, P4_PT, NA2);

N4 .~Reg16 p o r t m a p (N AI3, P2_P5, N_a5) ; N 5 : Con16 generic m a p (0) p o r t m a p (N A1); N6 : G t n 1 6 p o r ~ m a p (N_A2, N A3, el); N7 : C o n 1 6 generic m a p (0) port map (NA3) ; N8 : A d d 1 6 p o r t m a p (N_A5, N A2, N A7); NIl-- C o n 1 6 g e n e r i c m a p (1) p o r t m a p ( N All); NI2 : M u l 1 6 _ 2 p o r t m a p (N_A4, N All, P4, PT, N A12); N I 3 ; M U I 1 6 - ~ p o r t m ~ p ( N A I , N_A?, P2, P5, ~._A13); -- The F S M controller controller : process variable S t a t e : State type :-- $1; begin c a s e S t a t e is w h e n $I => PO <- "I', *0' after 296.00ns; State :- 52; w h e n 52 = >

P2 <= ,z,,

~

after

296.o0ns~

P7 <-- 'i', after 296.00ns; State :-- $3; w h e n $3 = > P3 <- 'l'p 'S' after 296.00ns; w a i t for 291.00ns; if C1 = 'i' t h e n 5tate := 54; e l s e State : = 55; e n d if; w h e n $4 => P4 <= "l*, ~0' after 296.00ns; State := $6; w h e n 55 -> P6 <= 'l', '0' after 296.00ns; State :- $7; w h e n 56 = > P5 <- 'i', 10' after 296.00ns; State := 53; w h e n $7 -> P1 <- "I', '0' after 296.00ns; end case; w a i t on Clock; e n d process;

--

-- O t h e r control mignals P2 P5 < = P2 or P5; P4--P7 < = P4 or P7; end;

Fig. 3 An VHDL example generated by CAMAD. It corresponds to the ETPN example given in Fig. 1

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z Pe~

have been completed, a next state will be entered depending on the co,+.Jitions guarding the arcs coming from the currem ~t,,~e. The FSM generation problem is similar to the problem of generating the teachability tree or coverability graph for a Pe~'i net [Pet gl]. The main difference between the CAMAD algorithm and a reachability graph generation procedure is that when generating the reachable states from the current state, a set of transitions is fired in the ETPN case instead of one single transition. Further, only states which are reache~ by firing maximally firable sets of transitions are iuciudod in the FSM graph. A firable transition set is a set of transitions which are enabled by the current state and the intersection of their guarding conditions are not always false. A maximally firable transition set is defined as a firable transition set that is not proper subset of any of the firabhi transition sets of the current state. The maximally firable transition set concept is introduced to get rid of redundant states in the generated FSM graph so as to reduce its complexity and implementation cost. The generated FSM description of the ETPN controller is then coded in the VHDL format in the second step. Fig. 3 includes an example of the coded FSM descriptions which cerresponds to the Pelri net given in Fig. l(a). In this example, the clock cycle time is 290 ns, which is produced as the result of analyzing the critical path of the current design by CAMAD. Note that in the case when there exists more than one possible next state, the branch checking will be done at the end of the clock cycle time when the condition signals are stabilized. CAMAD generates also a test-bench skeleton for the ETPN design when convening it into a VHDL desefiption. The tost-beneh skeleton consists of a declaration of t_~.~ test-bench entity and an architecture which consists of a signal component corresponding to the designed system. The I/O pins of the designed system will be connected to some signals which will be used to capture the simulation results. The users can also fill in some waveform specification for the input pins of the designed system so that specific test patterns can be used to check the desired properties. The test-beuch skeleton also includes a clock signal generator and a stop-simulation signal to control the simulation process. The final VHDL description is simulated by the MINT VHDL simulation system developed by the

Swedish Institute of Micrnelectronics [Ah 90]. The MINT syste m provides a very nice user-interface which allow the designers to view waveforms graphically, thus facilitating visual comparison of simulation results as well as allocation of errors. The users can use the simulation results to chock functional correctness or performance of the designed system. Assertions will also be used to report specific problems to the designers, such as violation of register set-up or hold time. At the moment, we have not implemented any automated feedback path of the simulation results to directly influence the high-level synthesis process. The designers must interpret the simulation results themselves and guide the synthesis process by interacting with the design algorithms. This is a main weak point of the current work. Nevertheless, since CAMAD provides a very efficient interactive mode for designers to interact with the high-level synthesis process and the current design in ETPN form can be viewed graphieaily, this manual feodback path works well with design eases which are not extremely large. 5. Final Discussions We have developed a method to use VHDL as a highlevel simulation language. VHDL is used both to capture the semantics and the implementation attributes of basic components at register-transfer level and to model the intermediate design representation of a high-level synthesis process. As a result, the intermediate and final designs can be simulated and the simulation results can be used to guide the synthesis process. A VHDL genelator has been implemented as part of the CAMAD hlgh-level synthesis system. It converts the ETPN design representation of CAMAD into a VHDL entity specification and generates a test-bench for testing the entity. A set of the basic and high-level components used by CAMAD has also been described in VI-~L. The development of the VHDL simulation facility is motivated by the tact that there exist many, good quality VHDL models for a wide range of standard components. With our approach, these standard componems can directly be used as building block of digiud systems, because a system consisting of these components and other dedicated modules can readily be evaiantod and verified using the VHDL simulation

Digital syslem simulation with VHDL

facility. Another advantage of our approach is that the generated VHDL output of the register-transfer level design can be used directly as input to a lowlevel layout generation tool as more and more CAD tools are supporting VHDL as an input speci.r.c~tlon language. 6. References [AIt 90]

M. Altmae, MlikT a VHDL Simulation System, Prec. Europea~ Design Automation Conference, Glasgow, Scotland, 1215 March 1990, pp.102-106 [Ber 91] L. Berrojo, P. Sanchez and E. Villar, HighLevel Synthesis and Simulation with VHDL, Prec. EURO-VHDL'91, Stockholm, Sept. 8-11, 1991, pp.62-69 [Cam 91] R. Camposano, L. E Saunders and R. M. Tabel, VHDL as Input for High-Level Synthesis, IEEE Design and Test Conf. 1991 [guc 87] IC Kanhcinski and Z. Peng, Microprogramming Implementation of Timed PetH Nets, Integration, the VLSI Journal, vol.5, 1987, pp.133-144 -

[Lis 89]

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J. Lis and D. Gajski. VHDL Synthesis [,'sing Structured Modelling, Prec. 26th Design Autormtlon Conf. 1989, pp.606-609

[Pen 88] 7-,. Peng, Semantics of a Parallel Compw ration Model and ~txApplications in Digital Hardware Design, Prec. of the 1988 International Conference on Parallel Processing, Pennsylvania State Univeralty, August 15-19,1988, pp.69-73 [Pen 89] Z. Peng, K. Kuchcinski and B. Lyles, CAMAD: A Unified Data PathlControl Synthesis Environment, in D.A. Edwards (Editor), Design Methodologies for VI..SI and Computer Architecture, North-HolPand, 1989, pp.53-67 [Pet 81] J . L . Peterson, Pctri Net Theory and the Modeling of Systems, Prentice-ball, Englewood Cliffs. New Jersey. 1981 [Pos 9r] A. Postola, VHDL Speclfzc Issues in High Level Synthesis, Prec. EURO-VItDL'91, Stockholm, Sept. 8-11,1991, pp.70-T'/ ~/HDL 87] IEEE Standard VHDL Language Reference Manual, IEEE Standard 1076-1987