- Email: [email protected]
Discovering and reducing defects in MIM capacitors
Microelectronics Reliability xxx (xxxx) xxx–xxx
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Discovering and reducing defects in MIM capacitors William J. Roesch⁎, Dorothy June M. Hamada Qorvo, 2300 N.E. Brookwood Parkway, Hillsboro, OR 97124-5300, United States
A R T I C L E I N F O
A B S T R A C T
Keywords: Capacitor Defect Detection Classification Reduction Mitigation
Integrated circuit defectivity is becoming a top concern for Reliability Engineers and their customers. Device lifetimes and times to wearout are less important compared to the experience of an early or infant failure in the warranty period. Defects in circuit elements, such as capacitors, are as important as any other cause of device fallout. Historically, integrated capacitors have been a leading reason for early failure, so this work describes the detection, root cause analysis, and the mitigation of three types of capacitor defects.
1. Introduction
1.2. History – materials and capacitor physical defects
Analog and radio frequency integrated circuits typically use passive elements. Capacitors are commonly formed by silicon oxide or silicon nitride dielectrics formed between metal plates and they can range in sizes from square microns to square millimeters. These elements are called Metal-Insulator-Metal (MIM) capacitors, and they can be used as discrete die components or integrated into semiconductor circuits. The long history of Metal-Oxide-Semiconductor (MOS) gate capacitor developments have driven various improvements in measurement, characterization, defect detection methods for MIM capacitors.
With crude capacitor construction between evaporated and plated metals, the source of early MIM capacitor detects was those obvious physical materials which could affect the dielectric uniformity by causing localized thin regions. Stray materials, particles, stains, residues, and non-planar surfaces are typical defects that cause thinner dielectrics and higher electric fields which lead to instantaneous failure or early life fallout. See images in Fig. 3. Particle, or physical defects are the one of the most common types of defects reported to cause capacitor failures. Large physical defects can be detected by various particle detection (such as laser scanning) and/ or visual inspection (such as automated optical inspection) equipment. Examples of physical particle detection results are shown as a count of defects over more than a 1 year period in Fig. 4 [3]. Measurement of the physical defects per unit area and the reduction of defects over time are depicted in Fig. 4. Early learnings led to significant reductions in physical defects. Changes to the overall structure included planarizing dielectrics to remove plated airbridge variation, and shifts from evaporated to sputtered metal formation for the top and bottom capacitor electrodes. As a result, a modern MIM capacitor construction is depicted in Fig. 5.
1.1. History – why worry about capacitors? Examination of > 14,000 customer returns over a 9 year period indicates that capacitors are a leading cause of fallout [1]. Fig. 1 shows the total count of analyzed customer returns categorized by failure mechanism. For each year, the top 10 causes of returns are counted. Highest causes of returns are electrostatic discharge, electrical overstress, and transistor defects. Lower level causes of returns are cracked die, delamination, and package connectivity. While capacitors are not an inherent part of compound semiconductor active devices, they are often integrated in analog and mixed signal circuits as MIM components. In their earliest form, they were simply constructed between available interconnect materials as shown in Fig. 2 [2].
1.3. History – measurement and defect detection After the most obvious physical defects are discovered and mitigated, detection of capacitor defects becomes more difficult by surface
Abbreviations: Ave, average; AVG, average; Cap, Capacitor; cm2, square centimeter; CS, Compound Semiconductor; DPM, Defects Per Million; FIB, Focused Ion Beam; GaAs, Gallium Arsenide; ManTech, Compound Semiconductor MANufacturing TECHnology Conference; MIM, Metal Insulator Metal; MOS, Metal Oxide Semiconductor; pF, pico Farad; ppm, parts per million; RF, Radio Frequency; StDev, Standard Deviation; μm, micron; Vs, versus; #, number ⁎ Corresponding author. E-mail address: [email protected] (W.J. Roesch). http://dx.doi.org/10.1016/j.microrel.2017.10.021 Received 16 July 2017; Received in revised form 14 October 2017; Accepted 19 October 2017 0026-2714/ © 2017 Elsevier Ltd. All rights reserved.
Please cite this article as: Roesch, W.J., Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.10.021
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Fig. 1. Pareto Chart of customer fallout causes by year from 2008 through 2016. Capacitors were a top cause of failure prior to 2008, and were the third leading cause over the nine years reported in this chart. By 2016, returned capacitors had dwindled to #7.
Fig. 2. Pre-1990 MIM capacitor construction. Dielectric layer between “landed” airbridge (thick top metal) and local transistor interconnect layer (thinner bottom metal). Dielectric is silicon nitride, metals are gold, and substrate is GaAs.
delineation of intrinsic and extrinsic failure types. Detection of defectivity down to 100 ppm levels is indicated by sample sizes > 10,000 capacitors. Of course, the size (in area) of the capacitor has a direct impact on the detectability of defects which are affected by area – as most are physical defect types. Typical physical scans and visual inspections rarely exceed about a 20% defect detection capability in the correlation studies conducted by these researchers. Additionally, nonelectrical detection methods, such as Automated Optical Inspection, usually have a false positive detection rate of > 100% of the actual defects it catches. That means that scans and visual inspections classify more good capacitors as bad than bad capacitors as bad.
scanning and/or visual inspection methods. Electrical methods, such as ramping or step-stressing capacitors until failure, provide a much more complete assessment of each individual sample capacitor's lifetime. For example, the extrinsic and intrinsic failure populations are easily discernable in a voltage ramp to failure stress. A probability plot, such as shown in Fig. 6, can provide population information and also provide electrical indicators of the mechanisms that might be causing the defective fallout [4]. Examination of Fig. 6 clearly delineates the intrinsic (> 44 V) and extrinsic (< 44 V) failure types. The defective population in this plot is about 5% and the intrinsic population is about 95%. Although the ramp-to-failure method is destructive, it is 100% effective in detecting extrinsic capacitors, regardless of their underlying cause. While faster ramp rates lead to more optimistic (i.e. higher) predictions of the lifeending failure voltage, the speed of ramp doesn't seem to change the
1.4. Voltage stress to failure - magical Ramping or step-stressing capacitors until failure provides a 2
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Particle, As Deposited
FIB of Shorted Capacitor
of identical capacitors produced with sputtered and evaporated bottom electrode metals. Besides the inherent concentration of defects, the size of the defects, material properties, (such as roughness) can impact capacitor dielectrics as shown in Fig. 7. Three or more volts in breakdown could indicate systemic changes in the effective dielectric thickness.
2.1. Mitigating defects – layout of devices The effect of changing capacitor design by examining results on ramp-to-failure probability plots is a good way to show designers the effect of their choices on defectivity. For example, the results of adjusting a layout parameter can have remarkable effect. The layout parameter shown in Fig. 8 was thought to be innocuous for capacitor defectivity. This parameter is not related to either of the metal electrodes above or below the dielectric, or the dielectric itself. This layout parameter was varied from the specified minimum and maximum across a population of devices. At the maximum allowed size, defectivity was at least 4 × higher than defectivity measured at the minimum allowed size. See Fig. 8. By relying on ramp-to-failure, we can use probability Vs. stress axes to describe reliability results relative to goals and relative to variables in investigative studies. For example, the maximum allowed layout size shown in Fig. 8 is depicted by the + “plus” symbols, which is the highest (most defective) population on Fig. 8, had about 20% fallout at 40 V. The minimum allowed layout size is depicted by the “square” and “circular” symbols, which is the lowest population (least defective) on Fig. 8 having about 5% fallout at 40 V. Without changing construction or materials, physical layout of the capacitors themselves can have consequences on the defectivity in MIM capacitors. For example, Fig. 9 shows how another layout design factor (A or B) can affect the number of defects in identical capacitors as measured side-by-side on 90 different wafers over a two year period. When the layout changes described in Figs. 8 and 9 are combined, defects can be cut by as much as 1/10th! However, the hunt to find capacitor defects also subsequently gets 10 times harder. For this reason, special experimental wafers intentionally include some capacitors with the more defective layout styles to enhance detection in other continuing studies. These more discerning layouts may exceed the limits allowed for actual products, but the violations help us hunt and find more defects.
Fig. 3. Example physical defect circa 1980–1990. Metal “spit” from evaporation deposition of capacitor bottom plate. Left photo shows deposition of the defect and subsequent shadowing. Right photo is Focused Ion Beam (FIB) cross-section of the defect formed within a MIM capacitor.
complete assessment of each individual sample's lifetime. As a result, the extrinsic and intrinsic failure populations are easily discernable. A probability plot, such as shown in Fig. 6, can provide population information and indicators of the mechanisms that might be causing the defective fallout. Typically, the majority population is free from defects and represents the higher breakdown voltages (50 V ± 5 V in Fig. 6) which are influenced by normal dielectric thickness variation within a process. Any type of defect would reduce the breakdown into the lower voltage region (< 44 V in Fig. 6). Even though capacitor ramping provides enchanting data for analysis and improvement, it does destroy every capacitor that is measured. Therefore, Voltage stress to failure cannot be used as a screen or a 100% measurement during production. Sacrificial capacitors would be needed to characterize defects and populations. With great care and full characterization of the surviving population, non-lethal voltage screening could help to screen weak capacitors and/or detect outlier wafers.
2. Mitigating defects – fabrication and semiconductor processing One of the most significant changes to reduce capacitor defects can be semiconductor fabrication processing methods. Sputter and evaporation methods are similar metal deposition techniques, but differences in these depositions can have significant impact on defectivity. For example, Fig. 7 shows some differences in leakage and breakdown
Fig. 4. Example physical defect detection and reduction. Scanning, detection, and count of metal “spits” from evaporation deposition of capacitor bottom plate. Significant reductions in physical defects were noted during the mid1990s [3].
3
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Fig. 5. Example of modern MIM capacitor construction.
Yield
Defects
Fig. 6. Typical ramp-to-failure probability plot for > 20,000 capacitors in a special population of capacitors designed to “hunt” for defects.
Wearout
Probability (Normal)
99 95 90 80 70
Defect Detection Opportunity
50 30 20 10 5 1 0.1
100ppm
0
5
10
15
20
25
30
35
40
45
50
55
60
Capacitor Breakdown (Volts)
2.2. Mitigating defects – chemical defects from fab processing and capacitor formation
Up until the discovery of chemical defects, it was presumed that environmental stresses such as temperature-cycling, high temperature bake, solder reflow simulations, temperature cycling, and unbiased humidity would not influence capacitor defectivity. This presumption was found to be correct, except in the presence of the chemical defects. For the most part, chemical defects have only been detected by comparing ramp-to-failure for experimental devices with control devices, both before and after environmental stressing.
At the beginning of the search for capacitor defects, it was expected that physical defects were the source of every low voltage fallout. However, a significant breakthrough was the discovery that “perfect” physically constructed capacitors could fail at unexpectedly low voltages. Fig. 10 shows the results of semiconductor process chemistry on the defectivity of capacitors. Manufacturing steps prior to, during, and after capacitor formation have been found to cause chemical defects which weaken the dielectric. Sometimes these defects are exposed during the processing itself, and others only manifest after the environmental stresses of actual use applications are applied. To evaluate the stress-induced defects, environmental stresses can be applied to experimental wafers prior to the ramp-to-failure capacitor testing. To delineate process-induced and application-induced defects, duplicate sets of capacitor structures are included side-by-side so that “before” and “after” voltage ramps can be compared before and after environmental stresses within each experiment.
2.3. Mitigating defects – surprise! electrical defects detected Another unexpected finding in the defect reduction effort was the finding of electrically caused capacitor defects. So far, these are suspected to be caused during processing and not a result of electrical measurement or induced by use applications. Fig. 11 shows the effect of removing electrical defects through process development at a particular manufacturing step. The electrical defects manifest during later processing, well after MIM capacitors are formed and passivated.
4
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Fig. 7. Effect on defectivity of evaporated and sputtered metal deposition methods.
Fig. 8. Effect on defectivity of a layout parameter. The highest defectivity (highest population graphed) was the largest in allowed layout size (+ at the top of the legend). The lowest defectivity (Square and round symbols - Lowest two populations graphed – on top of each other), were the smallest layout sizes (two symbols at the bottom of the legend).
sample size needed for measuring extrinsic defects in capacitors. 2) Physical defect detections were compared using electrical ramp-tofailure to find all damaged samples. However, correlation of visual to electrical results was found to be poor since visual defect detection methods are lacking. 3) Multiple assessments of defectivity were made, and methods of early detection and historical progress were revealed. Physical, chemical, and electrical defect types were discovered. 4) Example results of defect reduction methods on physical, chemical and electrical types of defectivity were described by several experiments. Design, layout, materials, and fabrication can all influence capacitor defectivity. 5) Historically, capacitors have been a leading cause of customer returns. Defectivity can be reduced by up to 97% using individual mitigation methods described here. A combination of several defect mitigation methods has reduced capacitor-caused returns from over 20% to < 5% over the past nine years.
2.4. Classifying failure mechanisms by appearance Examples of physical, chemical, and electrical failure mechanisms are shown as detected and located on special capacitor test structures in Fig. 12. Note that all capacitors subjected to ramp-to-failure testing would be expected to suffer visible damage. However, sometimes the damage might be obstructed or too tiny to be found. The examples shown in Fig. 12 are specific sites that failed at voltages in the extrinsic region of the probability plots. See Fig. 12 for an idea of underlying causes for failure. Since all defects are destroyed during the voltage ramp, some of the images are cross-sections “near” the destruction and not always within the catastrophic damage itself. 3. Summary of results There are five key findings of this work: 1) A defect measurement technique is described. This method includes an example of requirements regarding the capacitor layout and
Several defect types were classified, improvement methods were 5
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Fig. 9. Effect of capacitor layout on defect density of the same capacitor with different layouts. These capacitors, with identical capacitance values, were all ramped to failure. Layout Type A had an average of 2.79 defects per square centimeter, roughly 2.5 times Layout Type B which had an average of 1.1 defects per square centimeter for this sample of wafers.
established, and the magnitude of the results were quantified by experiments. Table 1 summarizes the key findings for each experiment. Overall, the reduction in capacitor fallout of customer returns from 20% in 2008 to about 5% in 2016 is shown in Fig. 1. 3.1. Impact This work blends failure mechanism information and defectivity measurements utilizing capacitor elements with fabrication and layout experimental findings in order to reduce extrinsic failures by ¼ over a 9 year period. Prior to the study period, capacitor failures were the #1 root cause of customer returns, sometimes accounting for as much as 35% of the fallout experienced by analysis of returns on a yearly basis. By the end of the defect reduction efforts (in just one factory), capacitor failures had dropped to 5%, whereas many of those fallouts now originate from other external factories which utilize different semiconductor technologies and have different capacitor formation methods. Fig. 10. Effect of process chemistry on capacitor defectivity. Fallout is comparing two similar chemistries after an environmental stress. Diamonds are the new chemistry, and they exhibit about 10% higher defectivity across the ramp voltage. The squares have about 10% lower fallout except at ramps between 47 and 55 V where the new chemistry fallout is significantly higher.
Acknowledgements The authors acknowledge the Table 1 continuous improvements made by process engineering and by design engineering to achieve the Fig. 11. Electrical defectivity in capacitors detected during voltage ramp-to-failure. Note the remarkable reduction in defectivity as measured on experimental lots.
6
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Fig. 12. Actual Photo images of three classifications of MIM capacitor defects: physical (five diagonal from upper-left to lower-right), chemical (three upper-right), and electrical (three lowerleft).
[2] William Roesch, “Reliability Basics” CS ManTech Workshop, (1999) (Vancouver BC). [3] William Roesch, Volume impacts on gaas reliability improvements, Microelectron. Reliab. 41 (8) (August 2001) 1123–1127 (Fig. 5). [4] Dorothy Hamada, William Roesch, Reliability studies on thin metal-insulator-metal (MIM) capacitors, Reliability of Compound Semiconductors Workshop, October 12, 2008 (Paper B.1, Monterey California).
Table 1 Capacitor defect reduction methods. Defect type
Method
Individual results
Physical
Reduce evaporation spits
Physical Physical Design
Evaporation to sputter Hillock removal Increase cap thickness
Physical Physical Chemical Chemical
Layout size reduction Layout type A Vs B Use good chemistry Deposition & chemistry
Electrical
“No Zapp” Process
Cut defectivity from > 400/cm2 to < 50/cm2 Cut defectivity from 50/cm2 to 20/cm2 Increase intrinsic breakdown > 4 V Lengthen intrinsic lifetimes No positive effect found on defectivity/ pF Reduce defects by as much as 75% Reduce defects by 60% Reduce defects by 66% Eliminate environmental aging susceptibility Reduce defects by 97%
improvement in customer satisfaction as depicted in Fig. 1. References [1] William Roesch, The technology trend and reliability challenges for III–V devices, Huawei Innovation Day Workshop, September 2, 2016 (Shenzhen China).
7
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Discovering and reducing defects in MIM capacitors William J. Roesch⁎, Dorothy June M. Hamada Qorvo, 2300 N.E. Brookwood Parkway, Hillsboro, OR 97124-5300, United States
A R T I C L E I N F O
A B S T R A C T
Keywords: Capacitor Defect Detection Classification Reduction Mitigation
Integrated circuit defectivity is becoming a top concern for Reliability Engineers and their customers. Device lifetimes and times to wearout are less important compared to the experience of an early or infant failure in the warranty period. Defects in circuit elements, such as capacitors, are as important as any other cause of device fallout. Historically, integrated capacitors have been a leading reason for early failure, so this work describes the detection, root cause analysis, and the mitigation of three types of capacitor defects.
1. Introduction
1.2. History – materials and capacitor physical defects
Analog and radio frequency integrated circuits typically use passive elements. Capacitors are commonly formed by silicon oxide or silicon nitride dielectrics formed between metal plates and they can range in sizes from square microns to square millimeters. These elements are called Metal-Insulator-Metal (MIM) capacitors, and they can be used as discrete die components or integrated into semiconductor circuits. The long history of Metal-Oxide-Semiconductor (MOS) gate capacitor developments have driven various improvements in measurement, characterization, defect detection methods for MIM capacitors.
With crude capacitor construction between evaporated and plated metals, the source of early MIM capacitor detects was those obvious physical materials which could affect the dielectric uniformity by causing localized thin regions. Stray materials, particles, stains, residues, and non-planar surfaces are typical defects that cause thinner dielectrics and higher electric fields which lead to instantaneous failure or early life fallout. See images in Fig. 3. Particle, or physical defects are the one of the most common types of defects reported to cause capacitor failures. Large physical defects can be detected by various particle detection (such as laser scanning) and/ or visual inspection (such as automated optical inspection) equipment. Examples of physical particle detection results are shown as a count of defects over more than a 1 year period in Fig. 4 [3]. Measurement of the physical defects per unit area and the reduction of defects over time are depicted in Fig. 4. Early learnings led to significant reductions in physical defects. Changes to the overall structure included planarizing dielectrics to remove plated airbridge variation, and shifts from evaporated to sputtered metal formation for the top and bottom capacitor electrodes. As a result, a modern MIM capacitor construction is depicted in Fig. 5.
1.1. History – why worry about capacitors? Examination of > 14,000 customer returns over a 9 year period indicates that capacitors are a leading cause of fallout [1]. Fig. 1 shows the total count of analyzed customer returns categorized by failure mechanism. For each year, the top 10 causes of returns are counted. Highest causes of returns are electrostatic discharge, electrical overstress, and transistor defects. Lower level causes of returns are cracked die, delamination, and package connectivity. While capacitors are not an inherent part of compound semiconductor active devices, they are often integrated in analog and mixed signal circuits as MIM components. In their earliest form, they were simply constructed between available interconnect materials as shown in Fig. 2 [2].
1.3. History – measurement and defect detection After the most obvious physical defects are discovered and mitigated, detection of capacitor defects becomes more difficult by surface
Abbreviations: Ave, average; AVG, average; Cap, Capacitor; cm2, square centimeter; CS, Compound Semiconductor; DPM, Defects Per Million; FIB, Focused Ion Beam; GaAs, Gallium Arsenide; ManTech, Compound Semiconductor MANufacturing TECHnology Conference; MIM, Metal Insulator Metal; MOS, Metal Oxide Semiconductor; pF, pico Farad; ppm, parts per million; RF, Radio Frequency; StDev, Standard Deviation; μm, micron; Vs, versus; #, number ⁎ Corresponding author. E-mail address: [email protected] (W.J. Roesch). http://dx.doi.org/10.1016/j.microrel.2017.10.021 Received 16 July 2017; Received in revised form 14 October 2017; Accepted 19 October 2017 0026-2714/ © 2017 Elsevier Ltd. All rights reserved.
Please cite this article as: Roesch, W.J., Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.10.021
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Fig. 1. Pareto Chart of customer fallout causes by year from 2008 through 2016. Capacitors were a top cause of failure prior to 2008, and were the third leading cause over the nine years reported in this chart. By 2016, returned capacitors had dwindled to #7.
Fig. 2. Pre-1990 MIM capacitor construction. Dielectric layer between “landed” airbridge (thick top metal) and local transistor interconnect layer (thinner bottom metal). Dielectric is silicon nitride, metals are gold, and substrate is GaAs.
delineation of intrinsic and extrinsic failure types. Detection of defectivity down to 100 ppm levels is indicated by sample sizes > 10,000 capacitors. Of course, the size (in area) of the capacitor has a direct impact on the detectability of defects which are affected by area – as most are physical defect types. Typical physical scans and visual inspections rarely exceed about a 20% defect detection capability in the correlation studies conducted by these researchers. Additionally, nonelectrical detection methods, such as Automated Optical Inspection, usually have a false positive detection rate of > 100% of the actual defects it catches. That means that scans and visual inspections classify more good capacitors as bad than bad capacitors as bad.
scanning and/or visual inspection methods. Electrical methods, such as ramping or step-stressing capacitors until failure, provide a much more complete assessment of each individual sample capacitor's lifetime. For example, the extrinsic and intrinsic failure populations are easily discernable in a voltage ramp to failure stress. A probability plot, such as shown in Fig. 6, can provide population information and also provide electrical indicators of the mechanisms that might be causing the defective fallout [4]. Examination of Fig. 6 clearly delineates the intrinsic (> 44 V) and extrinsic (< 44 V) failure types. The defective population in this plot is about 5% and the intrinsic population is about 95%. Although the ramp-to-failure method is destructive, it is 100% effective in detecting extrinsic capacitors, regardless of their underlying cause. While faster ramp rates lead to more optimistic (i.e. higher) predictions of the lifeending failure voltage, the speed of ramp doesn't seem to change the
1.4. Voltage stress to failure - magical Ramping or step-stressing capacitors until failure provides a 2
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Particle, As Deposited
FIB of Shorted Capacitor
of identical capacitors produced with sputtered and evaporated bottom electrode metals. Besides the inherent concentration of defects, the size of the defects, material properties, (such as roughness) can impact capacitor dielectrics as shown in Fig. 7. Three or more volts in breakdown could indicate systemic changes in the effective dielectric thickness.
2.1. Mitigating defects – layout of devices The effect of changing capacitor design by examining results on ramp-to-failure probability plots is a good way to show designers the effect of their choices on defectivity. For example, the results of adjusting a layout parameter can have remarkable effect. The layout parameter shown in Fig. 8 was thought to be innocuous for capacitor defectivity. This parameter is not related to either of the metal electrodes above or below the dielectric, or the dielectric itself. This layout parameter was varied from the specified minimum and maximum across a population of devices. At the maximum allowed size, defectivity was at least 4 × higher than defectivity measured at the minimum allowed size. See Fig. 8. By relying on ramp-to-failure, we can use probability Vs. stress axes to describe reliability results relative to goals and relative to variables in investigative studies. For example, the maximum allowed layout size shown in Fig. 8 is depicted by the + “plus” symbols, which is the highest (most defective) population on Fig. 8, had about 20% fallout at 40 V. The minimum allowed layout size is depicted by the “square” and “circular” symbols, which is the lowest population (least defective) on Fig. 8 having about 5% fallout at 40 V. Without changing construction or materials, physical layout of the capacitors themselves can have consequences on the defectivity in MIM capacitors. For example, Fig. 9 shows how another layout design factor (A or B) can affect the number of defects in identical capacitors as measured side-by-side on 90 different wafers over a two year period. When the layout changes described in Figs. 8 and 9 are combined, defects can be cut by as much as 1/10th! However, the hunt to find capacitor defects also subsequently gets 10 times harder. For this reason, special experimental wafers intentionally include some capacitors with the more defective layout styles to enhance detection in other continuing studies. These more discerning layouts may exceed the limits allowed for actual products, but the violations help us hunt and find more defects.
Fig. 3. Example physical defect circa 1980–1990. Metal “spit” from evaporation deposition of capacitor bottom plate. Left photo shows deposition of the defect and subsequent shadowing. Right photo is Focused Ion Beam (FIB) cross-section of the defect formed within a MIM capacitor.
complete assessment of each individual sample's lifetime. As a result, the extrinsic and intrinsic failure populations are easily discernable. A probability plot, such as shown in Fig. 6, can provide population information and indicators of the mechanisms that might be causing the defective fallout. Typically, the majority population is free from defects and represents the higher breakdown voltages (50 V ± 5 V in Fig. 6) which are influenced by normal dielectric thickness variation within a process. Any type of defect would reduce the breakdown into the lower voltage region (< 44 V in Fig. 6). Even though capacitor ramping provides enchanting data for analysis and improvement, it does destroy every capacitor that is measured. Therefore, Voltage stress to failure cannot be used as a screen or a 100% measurement during production. Sacrificial capacitors would be needed to characterize defects and populations. With great care and full characterization of the surviving population, non-lethal voltage screening could help to screen weak capacitors and/or detect outlier wafers.
2. Mitigating defects – fabrication and semiconductor processing One of the most significant changes to reduce capacitor defects can be semiconductor fabrication processing methods. Sputter and evaporation methods are similar metal deposition techniques, but differences in these depositions can have significant impact on defectivity. For example, Fig. 7 shows some differences in leakage and breakdown
Fig. 4. Example physical defect detection and reduction. Scanning, detection, and count of metal “spits” from evaporation deposition of capacitor bottom plate. Significant reductions in physical defects were noted during the mid1990s [3].
3
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Fig. 5. Example of modern MIM capacitor construction.
Yield
Defects
Fig. 6. Typical ramp-to-failure probability plot for > 20,000 capacitors in a special population of capacitors designed to “hunt” for defects.
Wearout
Probability (Normal)
99 95 90 80 70
Defect Detection Opportunity
50 30 20 10 5 1 0.1
100ppm
0
5
10
15
20
25
30
35
40
45
50
55
60
Capacitor Breakdown (Volts)
2.2. Mitigating defects – chemical defects from fab processing and capacitor formation
Up until the discovery of chemical defects, it was presumed that environmental stresses such as temperature-cycling, high temperature bake, solder reflow simulations, temperature cycling, and unbiased humidity would not influence capacitor defectivity. This presumption was found to be correct, except in the presence of the chemical defects. For the most part, chemical defects have only been detected by comparing ramp-to-failure for experimental devices with control devices, both before and after environmental stressing.
At the beginning of the search for capacitor defects, it was expected that physical defects were the source of every low voltage fallout. However, a significant breakthrough was the discovery that “perfect” physically constructed capacitors could fail at unexpectedly low voltages. Fig. 10 shows the results of semiconductor process chemistry on the defectivity of capacitors. Manufacturing steps prior to, during, and after capacitor formation have been found to cause chemical defects which weaken the dielectric. Sometimes these defects are exposed during the processing itself, and others only manifest after the environmental stresses of actual use applications are applied. To evaluate the stress-induced defects, environmental stresses can be applied to experimental wafers prior to the ramp-to-failure capacitor testing. To delineate process-induced and application-induced defects, duplicate sets of capacitor structures are included side-by-side so that “before” and “after” voltage ramps can be compared before and after environmental stresses within each experiment.
2.3. Mitigating defects – surprise! electrical defects detected Another unexpected finding in the defect reduction effort was the finding of electrically caused capacitor defects. So far, these are suspected to be caused during processing and not a result of electrical measurement or induced by use applications. Fig. 11 shows the effect of removing electrical defects through process development at a particular manufacturing step. The electrical defects manifest during later processing, well after MIM capacitors are formed and passivated.
4
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Fig. 7. Effect on defectivity of evaporated and sputtered metal deposition methods.
Fig. 8. Effect on defectivity of a layout parameter. The highest defectivity (highest population graphed) was the largest in allowed layout size (+ at the top of the legend). The lowest defectivity (Square and round symbols - Lowest two populations graphed – on top of each other), were the smallest layout sizes (two symbols at the bottom of the legend).
sample size needed for measuring extrinsic defects in capacitors. 2) Physical defect detections were compared using electrical ramp-tofailure to find all damaged samples. However, correlation of visual to electrical results was found to be poor since visual defect detection methods are lacking. 3) Multiple assessments of defectivity were made, and methods of early detection and historical progress were revealed. Physical, chemical, and electrical defect types were discovered. 4) Example results of defect reduction methods on physical, chemical and electrical types of defectivity were described by several experiments. Design, layout, materials, and fabrication can all influence capacitor defectivity. 5) Historically, capacitors have been a leading cause of customer returns. Defectivity can be reduced by up to 97% using individual mitigation methods described here. A combination of several defect mitigation methods has reduced capacitor-caused returns from over 20% to < 5% over the past nine years.
2.4. Classifying failure mechanisms by appearance Examples of physical, chemical, and electrical failure mechanisms are shown as detected and located on special capacitor test structures in Fig. 12. Note that all capacitors subjected to ramp-to-failure testing would be expected to suffer visible damage. However, sometimes the damage might be obstructed or too tiny to be found. The examples shown in Fig. 12 are specific sites that failed at voltages in the extrinsic region of the probability plots. See Fig. 12 for an idea of underlying causes for failure. Since all defects are destroyed during the voltage ramp, some of the images are cross-sections “near” the destruction and not always within the catastrophic damage itself. 3. Summary of results There are five key findings of this work: 1) A defect measurement technique is described. This method includes an example of requirements regarding the capacitor layout and
Several defect types were classified, improvement methods were 5
Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Fig. 9. Effect of capacitor layout on defect density of the same capacitor with different layouts. These capacitors, with identical capacitance values, were all ramped to failure. Layout Type A had an average of 2.79 defects per square centimeter, roughly 2.5 times Layout Type B which had an average of 1.1 defects per square centimeter for this sample of wafers.
established, and the magnitude of the results were quantified by experiments. Table 1 summarizes the key findings for each experiment. Overall, the reduction in capacitor fallout of customer returns from 20% in 2008 to about 5% in 2016 is shown in Fig. 1. 3.1. Impact This work blends failure mechanism information and defectivity measurements utilizing capacitor elements with fabrication and layout experimental findings in order to reduce extrinsic failures by ¼ over a 9 year period. Prior to the study period, capacitor failures were the #1 root cause of customer returns, sometimes accounting for as much as 35% of the fallout experienced by analysis of returns on a yearly basis. By the end of the defect reduction efforts (in just one factory), capacitor failures had dropped to 5%, whereas many of those fallouts now originate from other external factories which utilize different semiconductor technologies and have different capacitor formation methods. Fig. 10. Effect of process chemistry on capacitor defectivity. Fallout is comparing two similar chemistries after an environmental stress. Diamonds are the new chemistry, and they exhibit about 10% higher defectivity across the ramp voltage. The squares have about 10% lower fallout except at ramps between 47 and 55 V where the new chemistry fallout is significantly higher.
Acknowledgements The authors acknowledge the Table 1 continuous improvements made by process engineering and by design engineering to achieve the Fig. 11. Electrical defectivity in capacitors detected during voltage ramp-to-failure. Note the remarkable reduction in defectivity as measured on experimental lots.
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Microelectronics Reliability xxx (xxxx) xxx–xxx
W.J. Roesch, D.J.M. Hamada
Fig. 12. Actual Photo images of three classifications of MIM capacitor defects: physical (five diagonal from upper-left to lower-right), chemical (three upper-right), and electrical (three lowerleft).
[2] William Roesch, “Reliability Basics” CS ManTech Workshop, (1999) (Vancouver BC). [3] William Roesch, Volume impacts on gaas reliability improvements, Microelectron. Reliab. 41 (8) (August 2001) 1123–1127 (Fig. 5). [4] Dorothy Hamada, William Roesch, Reliability studies on thin metal-insulator-metal (MIM) capacitors, Reliability of Compound Semiconductors Workshop, October 12, 2008 (Paper B.1, Monterey California).
Table 1 Capacitor defect reduction methods. Defect type
Method
Individual results
Physical
Reduce evaporation spits
Physical Physical Design
Evaporation to sputter Hillock removal Increase cap thickness
Physical Physical Chemical Chemical
Layout size reduction Layout type A Vs B Use good chemistry Deposition & chemistry
Electrical
“No Zapp” Process
Cut defectivity from > 400/cm2 to < 50/cm2 Cut defectivity from 50/cm2 to 20/cm2 Increase intrinsic breakdown > 4 V Lengthen intrinsic lifetimes No positive effect found on defectivity/ pF Reduce defects by as much as 75% Reduce defects by 60% Reduce defects by 66% Eliminate environmental aging susceptibility Reduce defects by 97%
improvement in customer satisfaction as depicted in Fig. 1. References [1] William Roesch, The technology trend and reliability challenges for III–V devices, Huawei Innovation Day Workshop, September 2, 2016 (Shenzhen China).
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