DTMOS and FD-FVF based low voltage high performance Voltage Differencing Transconductance Amplifier (VDTA) and its application in MISO filter

Microelectronics Journal 63 (2017) 66–74

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DTMOS and FD-FVF based low voltage high performance Voltage Differencing Transconductance Amplifier (VDTA) and its application in MISO filter

MARK

⁎

Niharika Narang, Bhawna Aggarwal , Maneesha Gupta Department of Electronics and Communication Engineering, Netaji Subhas Institute of Technology, New Delhi, India

A R T I C L E I N F O

A B S T R A C T

Keywords: Voltage Differencing Transconductance Amplifier (VDTA) Fully Differential Flip Voltage Follower (FDFVF) Dynamic Threshold MOSFET (DTMOS) Multi Input Single Output (MISO), biquadratic filters

In this paper, two low voltage high performance Voltage Differencing Transconductance Amplifiers (VDTAs) are proposed. In proposed-I VDTA, Fully Differential Flip Voltage Follower is used to obtain output currents higher than biasing current. This VDTA offers higher transconductances and bandwidth. Proposed-II VDTA is DTMOS implementation of proposed-I VDTA. It utilizes the body effects and shows further improvement in the performance, while operating at lower supply voltage and consuming lesser power. Small signal analysis is done to show the improvements achieved in transconductances. Moreover, Multi Input Single Output and Biquadratic filters are realized using proposed VDTAs. These circuits are simulated in Mentor Graphics Eldospice (TSMC 0.18 µm Level 53 CMOS technology). Simulation results show that at a biasing current of 10 μA, proposed-I ( ± 0.7 V) and proposed-II ( ± 0.5 V) VDTAs have transconductances 415.62 μS and 422.89 μS, bandwidth 225.9 MHz and 296.21 MHz and power dissipation 145.43 μW and 102.14 μW respectively. To authenticate the robustness of proposed VDTAs, Monte Carlo and Corner analyses along with Process-Voltage-Temperature variations are done.

1. Introduction Integrated circuits are shrinking in size due to continuous downscaling of CMOS devices. This trend has tremendously increased the demand for active elements with low supply voltage and low power consumption in analog signal processing. In literature, many active elements, such as Operational Amplifier (Op-Amp), Operational Transconductance Amplifier (OTA), Current Conveyor (CC), Current Differencing Transconductance Amplifier (CDTA) and Voltage Differencing Transconductance Amplifier (VDTA) have been proposed [1–6]. VDTA has an edge over rest of the active elements because it has two different transconductances (gv1 and gv2) which can be independently controlled by external biasing currents. Various circuits like, oscillators, biquadratic filters, FDNRs (Frequency Dependent Negative Resistors) etc. can be realized using single VDTA [6,7]. Furthermore, it can be used to realize trans-admittance and trans-conductance mode applications [8]. In literature different VDTA architectures have been proposed [6,9–12]. Output currents of VDTA in [6,9] are limited by biasing current (IB). VDTAs proposed in [10–12] are unsuitable for low voltage applications. Nowadays, due to simple structure, unity gain and high

⁎

accuracy of Flip Voltage Follower (FVF), it is being significantly used as basic building block in low voltage and low power oscillators, amplifier, filters etc. [13]. Furthermore, FVF based structures (like Differential Flip Voltage Follower (DFVF), Fully Differential Flip Voltage Follower (FD-FVF) etc.) when used in input stage of these circuits increase their slew rate, current driving capability and reduce power consumption [13,14]. However, body effect in these FVF structures can alter the threshold voltage (Vt) and reduce performance of the circuit. This body effect can be compensated to a great extent and utilized to improve the working ability of the circuit by using Dynamic Threshold MOS (DTMOS) technique. It not only improves circuit performance but also reduces supply voltage requirement of the circuit [15–18]. In this paper, Fully Differential-Flip Voltage Follower (FD-FVF) based low voltage VDTA is proposed (proposed-I) which operates at low supply voltage, offers high output currents, transconductances and bandwidth. Moreover, DTMOS based FD-FVF VDTA (proposed-II) is proposed which further enhances the performance of proposed-I VDTA by increasing its transconductances and reducing supply voltages. Voltage mode Multi Input Single Output (MISO) [19,20] filter have been designed and simulated using the two proposed VDTAs. Implementation of transadmittance mode biquadratic filters (Lowpass, High-

Corresponding author. E-mail addresses: [email protected] (N. Narang), [email protected] (B. Aggarwal), [email protected] (M. Gupta).

http://dx.doi.org/10.1016/j.mejo.2017.03.002 Received 18 October 2016; Received in revised form 4 February 2017; Accepted 8 March 2017 0026-2692/ © 2017 Published by Elsevier Ltd.

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pass and Bandpass) [21] with proposed-II VDTA are also shown. The proposed filter consists of only one resistor and two capacitors and its performance is independent of component matching. This paper is arranged as follows: Various building blocks of proposed VDTAs (DTMOS technique, VDTA element, FD-FVF) are described in Section 2. The architecture of FD-FVF based proposed–I VDTA along with its small signal analysis is given in Section 3. DTMOS based proposed-II VDTA, along with further improvements achieved in this designed circuit are described in Section 4. Section 5 presents the application of the proposed circuits in MISO and Biquadratic filters. Simulation results are shown in Section 6 followed by the conclusions drawn. Fig. 2. VDTA symbol.

2. Building blocks of proposed VDTAs

⎡ IZ + ⎤ ⎢ ⎥ ⎢ IZ − ⎥ = ⎢ IX + ⎥ ⎢ ⎥ ⎣ IX − ⎦

2.1. Fully Differential Flipped Voltage Follower (FD-FVF) Flipped Voltage Follower (FVF) [13] is a unity gain voltage follower with shunt feedback. As discussed earlier, various differential structures can be designed using FVF. These structures provide the feature that output can be either in current or voltage form. Moreover, they exhibit class-AB behavior as the output currents can be programmed by means of biasing current source (IB), which is much lower than their maximum value. This fact makes FVF based circuits very attractive for low-power applications [14]. Structure of FD-FVF is shown in Fig. 1. In this circuit, if body effect is neglected, output drain currents (IDM5 and IDM6) are proportional to differential input voltage (VP – VN), applied at gate terminals of MOSFETs M1 and M2. FD-FVF provides fully differential operation and offers large common mode rejection ratio (CMRR) and output currents (IDM5 and IDM6) can be greater than or equal to IB. In this figure, if common mode signal is applied (i.e. VP=VN) and MOSFETs M1, M2, M5 and M6 are matched, then IDM5=IDM6=IB. A variation in VP – VN results in proportionate current variations of output currents (IDM5 and IDM6).

⎡g −gv1 ⎢ v1 − g ⎢ v1 gv1 ⎢ 0 0 ⎢ 0 0 ⎢⎣

⎤ ⎥ ⎡ VP ⎤ ⎥⎢ ⎥ V gv2 ⎥ ⎢ N ⎥ ⎥ ⎢⎣ VZ ⎥⎦ − gv2 ⎥⎦ 0

0

(1)

VDTA's dual tunability and flexibility to behave as both current and voltage mode device makes it a suitable fundamental block for designing various circuits like filters, oscillators, FDNRs etc. Nowadays, a lot of emphasis has been put in the direction to design high performance VDTA structures. Various VDTAs have been proposed time to time in literature [6,9–12]. First VDTA that was proposed in 2011 [6], consists of simple CMOS structure and is suitable for high frequency applications, but its output currents are limited by IB and offers lower transconductances. Low voltage and power consumption characteristics of VDTA given in [9] are achieved at the expense of very low transconductances and band width. VDTAs proposed in [10–12] provide various applications such as filters, oscillators etc. but are unsuitable for low voltage operations. 2.3. Dynamic Threshold MOSFET (DTMOS)

2.2. Voltage Differencing Transconductance Amplifier (VDTA)

In DTMOS technique [15], gate and body terminals of a MOSFET are tied together as shown in Fig. 3(a) and its schematic symbol is shown in Fig. 3(b). In a MOSFET, threshold voltage (Vt) is given as [16]:

VDTA is a differential device, which possess two transconductances (gv1 and gv2). These transconductances can be electronically controlled by its biasing current. Its symbolic representation is given in Fig. 2. Here, VP and VN are respectively positive and negative input terminals and Z+, Z-, X+ and X- are its output terminals. In VDTA, all input and output terminals have high impedance. The differential input voltage (VP – VN) produces currents at Z terminals (Z+, Z-) which are proportional to first transconductance (gv1) of VDTA. The voltage drop at Z+ terminal results in currents at X terminals (X+, X-), that are proportional to its second transconductance (gv2). These relationships between input voltages and output currents can be represented in matrix form as [6]:

Vt = Vt 0 − γ ( 2 | ϕF | −

2 | ϕF |−VBS )

(2)

where Vt0 is the threshold voltage at zero body bias and is given as [16]:

Vt 0 = 2 | ϕF |+VFB +

2qNa ϵs2 | ϕF | / Cox

(3)

hereγ = 2qNa ϵs /Cox is bulk threshold parameter, VFB is the flat band voltage, ϕF is the inversion layer potential, ϵs is Silicon permittivity, q is the electron charge, Na is the channel doping concentration per unit volume, Cox is the gate oxide capacitance per unit area. It can be observed from Fig. 3(a) that body voltage (VBS ) of DTMOS increases with increase in its gate voltage. This leads to decrease in Vt as per Eq. (1). However, VBS must be less than or equal to 2 | ϕF | to maintain negligible leakage current [15]. The minimal value of threshold voltage (Vt , min ) is achieved when VBS becomes equal to 2 | ϕF | and is given as [15]:

Fig. 1. Fully Differential Flip Voltage Follower (FD-FVF).

Fig. 3. (a) DTMOS transistor (b) schematic symbol.

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Fig. 4. FD-FVF based VDTA (proposed-I).

Vt , min = 2 | ϕF |+VFB

where μk is carrier mobility, W is effective channel width, L is effective channel length and IBk is the bias current of kth transistor. In Fig. 5, voltages at nodes D1 and D2 are respectively given as:

(4)

This reduction in Vt of DTMOS leads to increase in carrier mobility which results in high output current and transconductance of the device [15]. It can be calculated that transconductance of DTMOS has a value of (gm+gmb) where gm and gmb are respectively the gate and body transconductances of conventional MOSFET respectively [15,17]. Due to increase in transconductance, proportionate enhancement in bandwidth of DTMOS is also achieved. However, as discussed above, the increment in VBS must be limited by the value of 2 | ϕF | to keep leakage current negligible. Furthermore, in DTMOS based CMOS devices triple well technology has to be used [18].

The proposed FD-FVF based VDTA (proposed-I) is shown in Fig. 4. Two dual output OTAs [14] have been used to realize this structure. In Fig. 4, MOSFETs M1-M10, M21 and M22 constitute first dual output OTA and M11-M20, M23 and M24 constitute second dual output OTA. The transconductances (gv1 and gv2) of the proposed-I VDTA structure are equivalent to transconductance of individual OTAs. To derive gv1 for proposed-I VDTA (equivalent to transconductance of 1st dual output OTA), the equivalent low frequency small signal model (represented by bold lines) is shown in Fig. 5. In this figure, Vid is input differential voltage, Rb is output resistance of IB (which is very high) and gmk is transconductance of kth MOSFET and is given as:

⎡w⎤ IBkμk Cox ⎢ ⎥ ⎣ L ⎦k

(6)

⎞ ⎛⎛ V ⎞ VD2 = −gm2⎜⎜ id ⎟−VD 4⎟Rb ⎠ ⎝ 2 ⎠ ⎝

(7)

Applying KCL at different nodes (D3, D4, D5 and D6) and as VD7 = VD5 in Fig. 5, we get:

3. Proposed low voltage, high performance VDTA (proposed-I)

gmk =

⎞ ⎛V VD1 = (Rbgm1)⎜ id + VD3⎟ ⎠ ⎝ 2

⎛⎛ V ⎞ ⎞ ⎛⎛ V ⎞ ⎞ gm3VD1 = gm5⎜⎜ id ⎟−VD3⎟ + gm1⎜⎜ − id ⎟ − VD3⎟ ⎠ ⎝ ⎠ ⎝ 2 2 ⎝ ⎠ ⎝ ⎠

(8)

⎞ ⎛⎛ V ⎞ ⎞ ⎛⎛ V ⎞ gm 4VD2 = gm2⎜⎜ id ⎟−VD 4⎟ + gm6⎜⎜ − id ⎟ − VD 4⎟ ⎠ ⎝ ⎠ ⎝ 2 2 ⎠ ⎝ ⎠ ⎝

(9)

⎞ ⎛⎛ V ⎞ gm5⎜⎜ id ⎟−VD3⎟ = gm7VD5 ⎠ ⎝ 2 ⎠ ⎝

(10)

⎞ ⎛⎛ V ⎞ iout = gm8VD5 − gm6⎜⎜ − id ⎟−VD 4⎟ ⎠ ⎝ 2 ⎠ ⎝

(11)

VD3, as calculated from Eqs. (6) and (8) (assuming gm1=gm3=gm5 and Rb > > 1), is given as:

⎛V ⎞ VD3 = −⎜ id ⎟ ⎝ 2 ⎠

(5)

Fig. 5. Equivalent low frequency small signal model of FD-FVF based OTA.

68

(12)

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Using Eqs. (10) and (12), VD5 is obtained as:

⎛g ⎞ VD5 = ⎜⎜ m5 ⎟⎟Vid ⎝ gm7 ⎠

(13)

Similarly, assuming gm2=gm4=gm6 and using Eqs. (7) and (9), VD4 is calculated as:

⎛V ⎞ VD 4 = ⎜ id ⎟ ⎝ 2 ⎠

(14)

Substituting values of VD4 and VD5 in Eq. (11), and simplifying it, assuming gm7=gm8 (basic current mirror pair), iout can be calculated as:

iout =(gm5 + gm6 )Vid

(15)

From Eq. (15), first transconductance (gv1) of proposed-I VDTA is given as:

gv1 =

iout = (gm5 + gm6 ) Vid

Fig. 7. MISO filter based on proposed VDTAs.

(16)

Similarly, second transconductance gv2 for proposed-I VDTA (equivalent to transconductance of 2nd dual output OTA), can be derived as:

gv2 = (gm15 + gm16 )

gv1 = (gm5 + gmb5 + gm6 + gmb6 )

(18)

⎞ ⎛ gv2 = ⎜gm15 + gmb15 + g + gmb16⎟ m16 ⎠ ⎝

(19)

where gmbn is body transconductance of nth MOSFET (n=1, 2, 5, 6, 9–12, 15, 16, 19, 20). Comparison of Eqs. (18) and (19) with Eqs. (16) and (17) shows that transconductances of DTMOS based proposed-II VDTA increases further as compared to that of proposed-I VDTA.

(17)

Eqs. (16) and (17) show that FD-FVF configuration used in proposed-I VDTA, increases the transconductances by a factor of 2 as compared to the transconductances of VDTA given in [6,10–12].

5. MISO filter based on proposed VDTAs

4. DTMOS based VDTA (proposed-II)

Schematic of voltage-mode MISO filter, based on proposed-I and proposed-II VDTAs, is shown in Fig. 7 (shown by bold lines) [19]. This universal MISO filter structure consisting of one VDTA, one resistor and two capacitors realizes all types of filters. Circuit analysis yields voltage-mode biquadratic transfer function given as [19]:

In proposed-I VDTA (Fig. 4), body effect of MOSFETs has been neglected. If these body effects are considered, non–zero values of VBS for MOSFETs M1, M2, M5, M6, M9, M10, M11, M12, M15, M16, M19 and M20 will slightly degrade the circuit performance. In Fig. 6, proposed DTMOS based FD-FVF VDTA (proposed-II) has been shown. In this circuit, body effect of proposed-I circuit has been used in such a way that it enhances the performance of the circuit. Moreover, the operating voltage also gets reduced. In proposed-II VDTA, MOSFETs M1, M2, M5, M6, M9, M10, M11, M12, M15, M16, M19 and M20 are DTMOS transistors. As discussed in Section 2, DTMOS transistor has higher transconductance than a conventional MOSFET by a value of gmb. Using this property of DTMOS transistor (represented by dashed lines) in the equivalent low frequency small signal given in Fig. 5, transconductances (gv1, gv2 ) for proposed-II VDTA can be derived as:

gv1gv2 Vout (s ) =

C1C2

sgv2

Vin2(s ) + s 2Vin3(s ) C1 g g s s2 + + v1 v2 RC1 C1C2

Vin1(s ) −

(20)

Eq. (20) shows that MISO filter shown in Fig. 7 can implement the different basic filters just by changing the position of input signal (Vin). This implementation can be represented as:

LPF : Vin1 = Vin and Vin2 = Vin3 = 0 ; BPF: Vin2 = Vin and Vin1 = Vin3 = 0;

Fig. 6. DTMOS based FD-FVF VDTA (proposed-II).

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Fig. 8. Transadmittance mode biquadratic filters using VDTA. Table 1 Design parameters. Component name

Proposed-I VDTA

Proposed-II VDTA

VDD VSS IB C1,C2 M1-M6, M11-M16, M19, M20 M7, M8, M17, M18, M21-M24

0.7 V −0.7 V 10 μA 10 pF 7.2 µm/0.36 µm 14.4 µm/0.36 µm

0.7 V/0.5 V −0.7 V/−0.5 V 10 μA 10 pF 7.2 µm/0.36 µm 14.4 µm/0.36 µm

HPF : Vin3 = Vin and Vin1 = Vin2 = 0; BRF : Vin1 = Vin3 = Vin and Vin2 = 0;

APF : Vin1 = Vin3 = Vin and Vin2 = Vin. Natural frequency (ω0 ) and quality factor (Q) of this MISO filter are given as [19]:

ω0 =

Fig. 10. Transconductances of (a) proposed VDTAs at ± 0.7 V (b) proposed-II VDTA at ± 0.5 V.

gv1gv2 C1C2

(21)

Q=R

gv1gv2C1 C2

(22)

From Eqs. (21) and (22), it is clear that ω0 and Q can be controlled independently. The parasitics of VDTA involve parallel combination of capacitance and resistance at terminals Z+(CZ||RZ) and X- (CX||RX). These parasitics components are denoted in Fig. 7 by dashed lines [6]. Due to these parasitics natural frequency and quality factor given in Eqs. (21) and (22), get slightly modified and are given as [6]:

ω0 =

Q=

⎛1 1⎞1 gv1gv2 + ⎜ + ⎟ RX ⎠ RZ ⎝R (C1 + CX )(C2 + CZ ) ⎡ ⎛1 ⎢gv1gv2 + ⎜ R + ⎝ ⎣

⎤

1 ⎞ 1 ⎟ ⎥(C1 RX ⎠ RZ

⎛1 (C2 + CZ )⎜ R + ⎝

⎦

1 ⎞ ⎟ RX ⎠

(23)

+ CX )(C2 + CZ ) +

(C1 + CX ) RZ

(24)

Comparison between Eqs. (23) and (24) and Eqs. (21) and (22) shows that, parasitics degrade the bandwidth, natural frequency and quality factor by certain amount (depending upon CX, RX, CZ and RZ) and thereby, reduce overall performance of the circuit. 6. Biquadratic filter Transadmittance mode biquadratic filter is shown in Fig. 8 [21]. This filter is realized using 2 proposed-II VDTAs. ILP, IBP and IHP are the output current responses of this filter whereas input is a voltage source Vin. Hence, these type of filters are termed as transadmittance mode filters. The transfer function for different filter responses can be given

Fig. 9. (a) DC transfer characteristics of proposed VDTAs at ± 0.7 V. (b) DC transfer characteristics of proposed-II VDTA at ± 0.5 V.

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Table 2 Performance comparison of different VDTA Topologies. Reference

Supply voltage (V)

IB (µA)

Power dissipation (µW)

Transconductances {gm1= gm2} (µA/V)

BW of VDTA (MHz)

[6] [10] [11] Proposed(I) Proposed (II) Proposed(II)

± 0.9 ±1 ± 1.1 ± 0.7 ± 0.7 ± 0.5

10 10 10 10 10 10

105.40 187.67 223.86 145.43 144.70 102.86

163.29 246,46 205.53 415.62 489.13 422.89

50.42 105.6 94.78 225.9 360.8 238.2

s 2C1C2gv21 IHP = Vin D (s )

(27)

D(s ) = s 2C1C2 + sC1gv2 2 + gv11gv21 gv21

gv11

(28)

gv12

and are the transconductances of VDTA(1) and and where gv2 2 are the transconductances of VDTA(2) Pole frequency (ω0 ) and quality factor (Q) of this Biquadratic filter are given as [21]: Fig. 11. Frequency response of (a) proposed VDTAs at ± 0.7 V (b) proposed-II VDTA at ± 0.5 V.

ω0 =

gv11gv21 C1C2

(29)

as:

ILP = Vin

Q=

gv11gv12gv21 D (s )

sC1gv11gv21 IBP = Vin D (s )

(25)

1 gv2 2

gv11gv21C1 C2

(30)

(26)

Fig. 12. (a) Monte Carlo analysis showing variation in transconductance due to changes in aspect ratio for proposed FD-FVF based VDTA. (b) Monte Carlo analysis showing variation in transconductance due to changes in aspect ratio for proposed DTMOS based VDTA.

Fig. 13. (a) Transconductances for temperature variations from −25 to 75 °C in proposed-I VDTA. (b) Transconductances for temperature variations from −25 to 75 °C in proposed-II VDTA.

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are shown in Fig. 9(a) and (b). These figures show that both the proposed VDTAs are providing class AB behavior i.e. higher output currents can be achieved with a requirement of very less biasing current. From Fig. 9(a), it can be observed that under similar conditions of supply voltage (at ± 0.7 V) and biasing current (10 μA), output currents of proposed-II VDTA are even greater than that of proposed-I VDTA. As described in Section 2, the proposed-II VDTA circuit can operate at lower voltage as well. The DC transfer characteristic of proposed-II circuit operating at supply voltage of ± 0.5 V is shown in Fig. 9(b). From this figure, it can be observed that proposed VDTA-II provides more linearity as compared to proposed VDTA-I. In Fig. 10(a) and (b), AC analysis for transconductance has been plotted. These figures show that transconductances of both the proposed VDTAs are more than conventional VDTA (as described in Section 3). Fig. 10(a) shows the transconductances of proposed VDTAs at a supply voltage of ± 0.7 V. From this figure, it can be observed that the transconductance of proposed–II circuit (489.13 μS) is more than proposed-I (415.62 μS) (as explained in Section 3). Furthermore, the transconductance of proposed-II VDTA at a lower supply voltage ( ± 0.5 V) is plotted in Fig. 10(b) and is found to be 422.89 μS. Fig. 11(a) shows the bandwidth of the proposed VDTAs. From this figure, it can be observed that bandwidth of proposed-II circuit (360.89 MHz) is greater than proposed-I circuit (225.93 MHz) (as explained in Section 3). At supply voltage of ± 0.5 V, bandwidth of proposed-II circuit (296.21 MHz) is shown in Fig. 11(b). Simulations for both the proposed VDTAs are carried out at specified aspect ratios of MOSFETs. However, practically these values may get changed. In order to validate the robustness of proposed VDTAs against the variations of aspect ratios of MOSFETs, Monte Carlo analysis has been done for both the proposed circuits using 5% mismatches in aspect ratios with Gaussian distribution for 100 runs. In Fig. 12(a) and (b), these Monte Carlo simulations showing variations in transconductance of the proposed VDTAs are reflected. Comparison of performance parameters of different VDTA architectures given in literature and that of the proposed circuits is given in Table 2. It shows that both proposed VDTAs operate at lower voltages

Fig. 14. Transconductances for different process corners (TT, FF, FS, SF and SS) at ± 0.5 V and 25 °C in proposed-II VDTA.

7. Simulation results This section presents the simulation results of the proposed circuits as conferred in this paper. These simulations are carried out in TSMC 0.18 µm CMOS using Mentor Graphics Eldospice BSIM3 and Level 53 technology. Table 1 summarizes the design parameters for the proposed VDTAs and their application in MISO filter. These simulations are done using load resistor of 1 kΩ.

7.1. Performance analysis of proposed VDTAs VDTA provides two independently controlled transconductances (by biasing current) and offers output currents that depend upon these transconductances. Hence, emphasis is on achieving high transconductances at low biasing current and low supply voltage in order to achieve high performance VDTA. The DC transfer characteristics of proposed-I and proposed-II VDTAs Table 3 PVT variations in proposed VDTA-II. Voltage (V)

± 0.4

± 0.5

± 0.6

± 0.7

Temperature (°C)

−50 −25 0 25 50 75 −50 −25 0 25 50 75 −50 −25 0 25 50 75 −50 −25 0 25 50 75

FF

FS

SF

SS

TT

gV (µS)

BW (MHz)

Pdiss (µW)

gV (µS)

BW (MHz)

Pdiss (µW)

gV (µS)

BW (MHz)

Pdiss (µW)

gV (µS)

BW (MHz)

Pdiss (µW)

gV (µS)

BW (MHz)

Pdiss (µW)

423.17 363.83 304.74 250.50 198.65 128.41 557.68 512.99 472.57 434.96 386.06 282.82 589.35 540.10 496.08 455.54 403.02 296.68 621.64 567.34 519.24 475.21 418.17 305.26

66.65 51.14 43.62 41.22 39.47 34.01 451.67 402.50 378.43 346.55 315.44 178.09 465.58 438.57 401.86 389.97 338.26 248.42 479.06 440.57 398.85 388.57 365.67 302.45

85.38 88.01 91.82 97.31 107.36 144.75 100.83 100.94 101.07 101.47 105.56 148.18 123.74 122.81 122.41 122.51 126.92 179.69 148.69 147.42 146.36 145.82 150.74 214.16

411.99 354.24 296.42 243.31 192.51 124.30 544.49 501.71 462.84 426.54 379.15 278.30 575.00 527.95 485.72 446.67 395.87 292.11 605.87 554.08 508.01 465.68 410.58 300.52

63.21 51.58 39.70 45.91 79.76 119.82 425.85 378.55 356.55 346.55 308.06 176.09 438.57 389.86 379.57 367.48 335.50 243.42 443.22 415.67 380.51 370.95 335.08 246.96

83.63 86.40 90.34 95.96 106.15 143.12 98.42 98.69 98.97 99.50 103.63 146.50 120.16 119.95 119.75 119.99 124.64 177.61 144.74 143.83 143.07 142.78 147.94 211.76

58.98 57.32 55.16 52.71 47.78 33.04 536.56 492.10 451.10 404.17 299.79 118.66 569.78 522.61 479.81 431.21 328.08 173.80 599.20 547.46 500.92 448.09 338.53 206.07

176.40 167.29 154.21 141.31 132.52 124.79 367.57 324.74 266.89 210.10 107.76 36.92 438.57 413.50 379.55 356.90 273.84 48.22 465.17 425.85 409.85 374.80 278.46 52.68

234.52 246.47 260.06 274.94 294.78 347.25 101.94 102.37 102.96 105.55 133.38 344.05 123.13 122.93 122.80 125.25 159.04 542.03 146.96 146.09 145.44 147.76 188.08 709.57

53.14 52.08 50.48 48.55 44.24 30.64 529.94 486.78 446.60 399.89 294.02 113.66 562.18 516.50 479.85 426.83 323.56 167.53 590.05 540.11 494.98 443.11 333.63 201.68

145.49 139.89 132.87 121.20 114.14 104.78 335.75 294.05 259.08 201.12 102.37 36.16 414.59 383.26 352.60 324.38 250.58 45.70 411.42 378.05 362.39 333.08 268.53 47.59

243.34 255.55 269.40 284.55 304.70 357.97 100.25 100.82 101.55 104.39 133.89 350.43 120.73 120.75 120.92 123.50 159.19 560.06 143.75 143.17 142.83 145.56 188.43 737.41

119.22 110.48 101.73 93.45 82.06 56.30 542.27 498.85 459.18 422.89 348.85 204.44 572.90 525.69 483.23 441.12 366.87 242.00 602.77 550.95 504.75 489.13 379.07 254.16

286.24 263.34 233.37 213.78 110.68 116.48 397.67 378.83 327.50 296.21 222.12 159.91 438.21 416.99 378.83 355.89 297.21 118.95 445.00 420.45 385.83 360.89 311.99 143.51

144.94 154.39 165.53 178.15 195.49 243.09 100.31 100.62 100.99 102.14 113.70 231.25 121.77 121.56 121.45 122.30 135.99 295.36 145.86 144.96 144.24 144.70 160.83 356.71

*Pdiss= Power dissipation, gV=transconductance of VDTA (gV=gV1=gV2), BW=Bandwidth of VDTA.

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7.2. Performance analysis of MISO filter based on proposed VDTAs

(low power dissipation) and provide higher transconductances and bandwidth at same biasing current. Moreover, they operate at lower supply voltage of ± 0.5 V. It has been observed that proposed-II VDTA provides highest transconductances and bandwidth amongst all. Furthermore, to examine the effect of temperature variations on performance of the proposed VDTAs. These circuits are simulated for different temperature values varying from −25 to 75 °C. The simulated results achieved for transconductance is shown in Fig. 13(a) and (b). These figures show that proposed-I VDTA is less prone to the variations in temperature as compared to proposed-II VDTA. In the fabrication of MOSFET, variations in doping concentrations, device film thickness and lateral dimensions happen in between two wafers or across an individual die on wafer. These effects of process variation can be grouped into their effect on MOSFETs as: typical, slow and fast are defined as process corners [20]. The proposed VDTA-II is based on both PMOS and NMOS transistors, therefore, process corners for the proposed circuit are (i) Typical (TT), (ii) Fast Fast (FF), (iii) Fast Slow (FS), (iv) Slow Fast (SF) and (v) Slow Slow (SS). To confirm the proper working of the proposed circuit in complete design space, it is essential to simulate it at all process corners as the probability of circuit failure is more at these corners. In order to authenticate the robustness of the proposed circuit (Fig. 6), it was simulated at the five process corners specified above. The simulated response of VDTA transconductances (gv1=gv2) for different process corners (TT, FF, FS, SF and SS) at a supply voltage of ± 0.5 V and temperature of 25 °C is shown in Fig. 14. To show these process variation along with the changes in supply voltage and temperature i.e. Process-Supply Voltage-Temperature (PVT) variations are tabulated in Table 3. It shows that with the variation of 20% in supply voltage and −50 to 75 °C in temperature, the proposed VDTA-II works within acceptable range in whole design space.

MISO filter is a standard filter which can be used in communication such as phase locked loop, FM stereo demodulator etc. [19,20]. MISO filters are realized using the proposed VDTAs. Figs. 15(a)–19(a) show frequency response for different types of filters. The bandwidth of MISO filter using proposed-II circuit (7.8 MHz) is greater than that of MISO filter using proposed-I circuit (6.2 MHz). As described in Section 2, proposed-II VDTA can operate at low voltage. Figs. 15(b)–19(b) show

Fig. 17. Frequency response of band pass filters based on (a) proposed VDTAs at ± 0.7 V (b) proposed-II VDTA at ± 0.5 V.

Fig. 18. Frequency response of Notch filters based on (a) proposed VDTAs at ± 0.7 V (b) proposed-II VDTA at ± 0.5 V. Fig. 15. Frequency response of Low pass filters based on (a) proposed VDTAs at ± 0.7 V (b) proposed-II VDTA at ± 0.5 V.

Fig. 16. Frequency response of high pass filters based on (a) proposed VDTAs at ± 0.7 V (b) proposed-II VDTA at ± 0.5 V.

Fig. 19. Frequency response of all pass filters based on (a) proposed VDTAs at ± 0.7 V (b) proposed-II VDTA at ± 0.5 V.

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Fig. 20. Frequency response of lowpass, bandpass and high pass transadmittance mode biquadratic filters using proposed-II VDTA at ± 0.5 V.

the different filters realized using proposed-II VDTA operating at supply voltage of ± 0.5 V. At this operating voltage, bandwidth of proposed-II VDTA based MISO filter is 6.6 MHz.

(2008) 15–32. [2] S. Baswa, M. Bikumandla, J. Ramirez-Angulo, A.J. Lopez-Martin, R.G. Carvajal, G. Ducoudray-Acevedo, Low-voltage low power super class-AB CMOS Op-Amp with rail-to-rail input/output swing, in: Proceedings of the 5th IEEE International Caracas Conference on Devices, Circuits and Systems, 1, 2004, pp. 83–86. [3] J. Liu, Y. Han, L. Xie, Y. Wang, G. Wen, A 1-V DTMOS-based fully differential telescopic OTA, in: Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014, pp. 49–52. [4] K. Moustakas, S. Siskos, Improved low-voltage low-power class AB CMOS current conveyors based on the flipped voltage follower, in: Proceedings of the IEEE International Conference on Industrial Technology (ICIT), 2013, pp. 961–965. [5] S.K. Rai, M. Gupta, Performance enhancement of current differencing transconductance amplifier (CDTA) by using a new approach of gm boosting and its application, Opt.-Int. J. Light Electron Opt. 127 (15) (2016) 6103–6114. [6] A. Yesil, F. Kacar, H. Kuntman, New simple CMOS realization of voltage differencing transconductance amplifier and its RF filter application, Radioengineering 20 (3) (2011) 632–637. [7] D. Prasad, D.R. Bhaskar, Grounded and floating inductance simulation circuits using VDTAs, Circuits Syst. 3 (2012) 342–347. [8] C. Shankar, S.V. Singh, A new trans-admittance mode biquad filter using MO-VDTA, WSEAS Trans. Circuits Syst. 14 (2015) 8–18. [9] A. Uygur, H. Kuntman, DTMOS-based 0.4 V ultra low-voltage low-power VDTA design and its application to EEG data processing, Radioengineering 20 (2) (2013) 458–466. [10] C. Shankar, S.V. Singh, Single VDTA based multifunction trans-admittance mode biquad filter, Int. J. Eng. Technol. (IJET) 7 (6) (2016) 2180–2188. [11] D. Singh, P. Kumar, CMOS realization voltage differencing transconductance amplifier and based Tow-Thomas filter, Int. J. Sci. Res. Eng. Technol. (IJSRET) 4 (8) (2015) 898–901. [12] J. Jerabek, R. Sotner, K. Vrba, Electronically adjustable triple-input single-output filter with voltage differencing transconductance amplifier, Rev. Roum. Sci. Tech.–Électrotech. Énerg. 59 (2) (2014) 163–172. [13] R.G. Carvajal, S. Member, J. Ramírez-angulo, A.J. López-martín, A. Torralba, S. Member, J. Antonio, G. Galán, A. Carlosena, F.M. Chavero, The flipped voltage follower: a useful cell for low-voltage low-power circuit design, IEEE Trans. Circuits Syst.-I 52 (7) (2005) 1276–1291. [14] B. Calvo, S. Celma, M.T. Sanz, J.P. Alegre, F. Aznar, Low-voltage linearly tunable cmos transconductor with common-mode feedforward, IEEE Trans. Circuits Syst.-I 55 (3) (2008) 715–721. [15] F. Assaderaghi, D. Sinitsky, S.A. Parke, J. Bokor, P.K. Ko, Dynamic thresholdvoltage MOSFET (DTMOS) for ultra-low voltage VLSI, IEEE Trans. Electron Devices 44 (3) (1997) 414–422. [16] P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, 2nd ed., Oxford University Press, United Kingdom, 2011. [17] V. Niranjan, A. Kumar, S.B. Jain, Low-voltage and high-speed flipped voltage follower using DTMOS transistor, in: Proceedings of the International Conference on Signal Propagation and Computer Technology (ICSPCT), 2014, pp. 145–150. [18] V. Niranjan, A. Kumar, S.B. Jain, Triple well subthreshold CMOS logic using bodybias technique, in: Proceedings of the IEEE International Conference in Signal Processing, Computing and Control (ISPCC), 2013, pp. 1–6. [19] D. Prasad, D.R. Bhaskar, M. Srivastava, Universal voltage mode biquad filter using voltage differencing transconductance amplifier, Indian J. Pure Appl. Sci. 51 (2013) 864–868. [20] N.H.E. Weste, D. Harris, A. Banerjee, CMOS VLSI design – a circuits and systems, 37, Perspective, third ed., Dorling Kindersley India for Pearson Education, South Asia, 2006. [21] G. Gupta, S.V. Singh, S.V. Bhooshan, VDTA based electronically tunable voltagemode and trans-admittance biquad filter, Circuits Syst. 6 (2015) 93–102.

7.3. Performance analysis of transadmittance mode biquadratic filter based on proposed-II VDTA Transadmittance mode biquadratic filter is realized using the proposed-II VDTA at supply voltage of ± 0.5 V. Frequency response for Lowpass, Highpass and Bandpass filters are shown in Fig. 20. The simulation results shows that pole frequency of these transadmittance mode biquadratic filters at C1=C2=10 pF is 6.6 MHz, which is very near to the theoretically calculated value of 6.8 MHz. This filter designed using proposed VDTA-II dissipates only 204.35 μW power. 8. Conclusions Two low voltage high performance VDTAs are proposed in this paper. In proposed-I VDTA, FVF based fully differential structure (FDFVF) has been used as a core for the architecture. The main advantage of this structure is that output current can be greater than the biasing current. To further decrease the supply voltage and enhance the circuit performance, DTMOS technique is used in proposed-II VDTA. This technique further increases the transconductance and decreases the threshold voltage which results in reduction of supply voltage. Simulations of proposed circuits at same biasing current are shown at supply voltages of ± 0.7 and ± 0.5 respectively using Mentor Graphics Eldospice in TSMC 0.18 µm CMOS technology. The comparative analysis of the VDTAs proposed in the paper and available in literature (at same biasing current and same technology) has been shown. It has been observed that these proposed VDTAs are capable of working at low supply voltage and provide higher transconductances and bandwidth. The main advantage of these proposed VDTAs is that they provide higher transconductances as their output currents are not limited by biasing current as compared to other VDTA topologies present in literature. Moreover, proposed-II VDTA offers higher output currents as compared to proposed-I VDTA at similar input voltage. Furthermore, application of these VDTAs in real time applications like MISO and biquadratic filters are also shown. These circuits also confirm the improvements achieved. References [1] D. Biolek, R. Senani, V. Biolková, Z. Kolka, Active elements for analog signal processing: classification, review, and new proposals, Radioengineering 17 (4)

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