Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications

Solid-State Electronics 54 (2010) 104–114

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Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications M. Bawedin *, S. Cristoloveanu, D. Flandre, F. Udrea University of Cambridge, Engineering Department, 9 JJ Thomson Avenue, Cambridge CB3 0FA, United Kingdom

a r t i c l e

i n f o

Article history: Received 24 April 2009 Received in revised form 22 May 2009 Accepted 7 September 2009 Available online 12 January 2010 The review of this paper was arranged by O. Engström

a b s t r a c t Even in fully-depleted (FD) SOI MOSFETs, the floating-body potential variations may lead to strong transient effects on the current characteristics. A physics-based model, enabling the fast computing of the potential variation with time, is proposed in this paper. The model is validated, for a wide range of technological parameters and biases, by 2D numerical simulations. This model reproduces the experimental data and clarifies the physics mechanisms responsible for the transient variations of gate and drain currents. Relevant applications in the field of EEPROM and capacitorless floating-body DRAM memories are addressed. Ó 2009 Elsevier Ltd. All rights reserved.

Keywords: 1T-DRAM SOI MOSFETs Transient Body potential Model 1T-DRAM Band-to-band (B2B) tunneling Dynamic gate coupling

1. Introduction Fully depleted (FD) SOI transistors with single or multiple-gates are best candidates for further CMOS miniaturization. FD MOSFETs are traditionally assumed to be free of floating-body effects (FBE) which severely affect Partial Depleted (PD) transistors [1]. This assertion is true only for static mode of operation. In dynamic mode, the body potential can temporarily escape the gate control, leading to a number of dynamic FBEs: current overshoot and undershoot [2], gate-induced floating-body effect (GIFBE) [3], Meta-Stable Dip (MSD) effect [4]. These dynamic FBEs effects deserve attention because they have important practical implications: development of capacitorless single-transistor DRAM, EEPROM programming and history effects in integrated circuits. The dynamic variation of the body potential has been up to now mainly investigated via numerical simulations, which are tedious and extremely time consuming (days). On the other hand, a full analytical model is not tractable due to the complexity of the problem. The solution proposed in this paper is to develop a semi-analytical model which can be easily implemented for fast simulations (minutes). * Corresponding author. Tel.: +44 32 10 47 25 81; fax: +44 32 10 47 25 98. E-mail address: [email protected] (M. Bawedin). 0038-1101/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2009.12.004

The transient FBEs we investigate take place in a particular SOI MOSFET operating mode. Indeed, in case of usual digital or analog circuit applications, the front-gate bias range extends roughly between the flat-band voltage and 1 V above the threshold voltage, that is, for a front-surface potential varying from depletion to strong inversion. Less attention has been paid to floating-body effects which occur at bias range much lower than the flat-band voltage for nMOS. Indeed, before the recent interest generated by capacitor-less DRAMs on the SOI memory market, there was no practical application justifying a detailed analysis [5–8]. In this work, we address dynamic FBEs, such as capacitive coupling in deep depletion and body charging by band-to-band (B2B) tunneling which are relevant for the operation of single-transistor capacitor-less DRAM (1T-DRAM). A simple physics-based 1D model reproducing the transient variation of the non-equilibrium body potential is proposed in Section 2. The model is validated by comparison with full 2D numerical simulations as well as measurements. As shown in Section 3, this model is suitable for a wide range of technological parameters (gate oxide and silicon film thicknesses, doping levels in body and substrate), gate voltages (from strong inversion to accumulation) and bias scan speeds (from 1 lV/s to 1 GV/s). It exhibits very short computation time even for slow scan speeds (<1 lV/s) and allows identifying the contribution of the different injecting currents. Typ-

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ical applications for the optimization of EEPROM and 1T-DRAM memories are discussed in Section 4. Most results are focused on the practical case of FD SOI nMOSFETs with silicon film thicknesses from 100 nm down to 10 nm. However, the model is rather general and can also be applied to PD SOI transistors.

inversion (or depletion) to accumulation. The potential reference is the intrinsic Fermi level of silicon.

(

si V G1  V FB1 ¼ US1 þ CeOX1  ES1

2. Model principles

f ðUðyÞÞ ¼ The model aims at reproducing the transient characteristics of the floating-body potential in strong non-equilibrium regime. Typical experimental curves for nMOSFET are illustrated in Fig. 1. Remark the non-monotonous variation of the body potential and resulting gate current when the front-gate voltage is scanned from positive (VG1 = 0.5 V) to negative (VG1 = 5 V) values. The transient characteristics are only slightly influenced by the scan speed (SS) and gate bias if VG1 is higher or close to the threshold voltage. In depletion, the capacitive coupling between body and front gate is evidenced by a body potential decrease with a slope which does not depend on the scan speed. An abrupt change in body potential is visible when the top interface moves from inversion (or depletion) into accumulation mode, the back gate being grounded. The upturn in body potential variation occurs for a front-gate voltage much lower than the conventional flat-band value (1 V), which suggests deep depletion due to the very negative body potential. PD devices were previously modeled by introducing a floating node B and a body voltage VB for the quasi-neutral region of the film [10,11]. In order to account for non-equilibrium effects in FD MOSFETs, the key ingredient of our model is the distinction of electron and hole quasi-Fermi potentials. The model uses the standard analytical boundary or continuity conditions (Gauss law) at the front and the back oxide interfaces (Eq. (1)) and the discretized form of the Poisson equation (Eq. (2)) [12–15]. In nMOSFETs, the Poisson equation is related to a pdoped silicon film where the deficit or excess of majority carriers (holes) beyond conventional depletion or quasi-neutral regimes has to be taken into account. In this case, the hole quasi-Fermi level Wp can no longer be considered as always equal to zero. Therefore, Wp depends on the injected and/or generated majority carriers and consequently becomes a function of time. Since this model is intended to work with both minority (inversion mode) and majority (accumulation mode) carriers, the complete form of the Poisson Eq. (2) is required including the electron quasi-Fermi level Wn. Indeed, one of the interests of this model is to describe what happens when one interface is in inversion mode while the other is switched from

ð1Þ

si V G2  V FB2 ¼ US2  CeOX2  ES2

@ 2 UðyÞ @EðyÞ q ¼ ¼  ðp  n  NA Þ @y2 @y esi

ð2Þ

with p ¼ ni  exp½ðWp  UðyÞÞ=/t  and n ¼ ni  exp½ðUðyÞ- Wn Þ=/t  where Wp and Wn are the hole and electron quasi-Fermi levels, COX1(2) (=eOX/tOX1(2)) is the front (back)-oxide capacitance and ES1(2) is the front (back) surface electric field. The fourth order Cowell’s method was chosen to perform the potential discretization by linearizing the second order term @ 2 UðyÞ=@y2 of the Poisson equation all over the silicon film [12]. If ‘‘N” discretization points are considered, we obtain a system with ‘‘N” equations (F1 ? FN in system (3)) and N unknown values (U1 ? UN). This system has to be solved using the boundary conditions (1). Nevertheless, the hole quasi-Fermi level Wp remains to be determined. Consequently, one additional equation FN+1 is required. This equation accounts for the total hole charge injected into or extracted from the body and will be established hereafter. 8 F 1 ðUð1Þ . . . UðNþ1Þ Þ ¼ Uð2Þ  Uð1Þ þ H  CeOX1 ðV G1  V FB1  Uð1Þ Þ ¼ 0 > > si > > > 2 ð1Þ ðNþ1Þ ð3Þ ð2Þ ð1Þ > > F ð U . . . U Þ ¼ U  2 U þ U  H12  ½f ðUð3Þ Þ þ 10  f ðUð2Þ Þ 2 > > > > > > þf ðUð1Þ Þ ¼ 0 > > > > > .. > > . > > > > < F N1 ðUð1Þ . . . UðNþ1Þ Þ ¼ UðNÞ  2UðN1Þ þ UðN2Þ  H2  ½f ðUðNÞ Þ 12

> þ10  f ðUðN1Þ Þ þ f ðUðN2Þ Þ ¼ 0 > > > > > F N ðUð1Þ . . . UðNþ1Þ Þ ¼ UðNÞ  UðN1Þ  H  CeOX2 ðV G2  V FB2  UðNÞ Þ ¼ 0 > > si > > > N > P > ðNþ1Þ ðKÞ ð1Þ ðNþ1Þ > ; t i Þ ¼ ni  expðUðti Þ =/t Þ  expðUðti Þ =/t Þ  H > > F Nþ1 ðU . . . U > > K¼1 > > > N > P > ðNþ1Þ ðKÞ > expðUðti1 Þ =/t Þ  H  IF ðt Þ ¼ 0 : ni  expðUðti1 Þ =/t Þ  i1

K¼1

ð3Þ ð1Þ

ðNÞ

ðNþ1Þ

with U ¼ US1 ; U ¼ US2 ; U ¼ Wp . H is the distance between two mesh points and N is the number of discretization points; IF ðt Þ is the injection factor at time ti1, dei1 scribed in Eq. (6).

Fig. 1. Measured dynamic (a) gate current IG1 and (b) corresponding body potential UB versus a decreasing front-gate voltage VG1 scan in a PD SOI nMOSFET. The scan speed SS is varied from 0.1 to 25 V/s. The inset shows the SOI MOSFET configuration. The gate width and length are 100 lm. The thicknesses of the gate oxide, buried oxide and silicon film are 4, 400 and 100 nm, respectively. The body doping is 5  1017 cm3. The drain, source and back gate are grounded, whereas the body is floating [9].

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We further assume that Wp is constant in the vertical direction (i.e. between the front and back gates) as shown by TCAD simulations and that only the holes control the body potential. Since low drain voltages are considered and the electrons are instantly supplied by the N+ source and drain, the electron quasi-Fermi level Wn is fixed to zero volt. Hence, only one additional equation is required to determine Wp and solve the system. The main complexity of this modeling consists in getting the link between the ‘‘lateral” (x-axis, Fig. 2a) current equations, i.e., the injected hole charges, and the non-equilibrium ‘‘vertical” profile (y-axis, Fig. 2b) of the body potential. There are two dominant sources of holes, which drive the transient body potential variations: (i) the reverse hole drift–diffusion current in the body-todrain (source) junction (Eq. (4)) depending on the dynamic value of the hole quasi-Fermi level Wp and (ii) the B2B tunneling generation (Eq. (5)) which is due to the vertical electric field enhancement in the gate-to-drain overlap region (Fig. 2a).

IDD ffi 2  q 

    W  tsi  Dp n2i Wp   exp 1 LDD ND /t

IB2B ffi 2  W  DL  q 

N X

PðEðK  HÞÞ  H

ð4Þ

(5). Nevertheless, the discretization procedure in the overlap region can be applied with more complex B2B tunneling models [19,20], which take into account phenomena such as phonon assisted band-to-band tunneling, generation–recombination or even temperature effects. In particular, band-to-band tunneling fades away near the insulator interfaces if no states to tunnel into are available. The procedure to combine the junction leakage currents and the discretized body potential is performed by equating at each bias/ time: (i) the time derivative of the total hole charge integrated over the whole body thickness and (ii) the sum of the IDD and IB2B currents (Eq. (6)). N X K¼1

PðEðK  HÞÞ ¼ A  E2 ðK  HÞ  expðB=EðK  HÞÞ qffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffi m=Eg and B ¼ p=2qg  E3g .

with

A ¼ q2 =18pg2 

Notice that the P body/N+ drain(source) junction current Eq. (4) does not take into account the SRH generation. Therefore, the usual Debye length was substituted in Eq. (4) by LDD, the distance between the drain (source) contact and the body/drain (source) metallurgical junction (Fig. 2a). It was also assumed that the minority hole density in the drain is constant and equal to n2i =N D . The B2B current calculations can be performed via an analytical equation [16,17] or a discretized expression like Eq. (5) [18]. We use Eq. (5) where the required vertical electric field E is obtained by a second discretization of the potential in the gate-to-drain overlap region. In this region, we consider the potential in steady-state regime, hence the hole quasi-Fermi level Wp is equal to zero. The discretized system in the gate-to-drain overlap can be readily computed in the same way as the ’non-equilibrium body potential’ system (3), except that the last equation becomes useless since Wp = 0. Therefore, for each gate voltage and time step, the total amount of holes generated by B2B tunneling can be determined. Notice that the computation time required to solve the ‘gate-todrain overlap’ system is negligible. Due to their simplification, Eqs. (4) and (5) do not take into account the full mechanisms complexity in the gate-to-drain overlap region but the accuracy of this model will be demonstrated with the simple B2B tunneling model

pðK  H;ti1 Þ  H þ IF ðt

K¼1

i1 Þ

ðcm2 Þ

ð6Þ

Dt  ðIDD ðt i1 Þ þ IB2B ðt i1 ÞÞ qW L t i ¼ t i1 þ Dt i1 Þ

¼

K¼0

with W the gate width and DL the gate overlap length. E is the vertical electric field in the gate-to-drain overlap region and

N X

with pðK  H; t i Þ the hole density at time ti and coordinate K  H;

IF ðt

ð5Þ

pðK  H; t i Þ  H ¼

) F Nþ1 ¼

N X K¼1

pðK  H; t i Þ  H 

N X K¼1

pðK  H; t i1 Þ  H  IF ðt

i1 Þ

Obviously, the proposed expressions for drift–diffusion current (Eq. (4)) and B2B tunneling generation (Eq. (5)) can be exchanged with other similar models. Indeed, the system (3), yielding the potential within the body, can be considered as a ’black box’ where the injection factor IF is the external input. The system (3) is solved with the Matlab simulator [21] by the Gauss–Newton algorithm for the non-linear least squares problems. In order to improve the convergence and reduce the computation time, the Jacobian (i.e., the partial derivative matrix of this system) can also be implemented. Otherwise, if the code to analytically compute the Jacobian is not available, Matlab uses a numerical finite differentiating method to approximate the Jacobian which is more time consuming. The procedure to handle the system during the voltage sweep is the following. First, at the time t0 (=0 s) before the front-gate-voltage scan starts, the total body hole charge Qp(t0) =ðq  W  L P pðK  H; t0 Þ  HÞ has to be determined at steady state, i.e. when VG1 is at least higher than the flat-band voltage VFB1. Since the hole quasi-Fermi level Wp and the injection factor IF(t0) can be considered as equal to 0, the system (3) is readily solved yielding the initial potential profile in the body as well as the total hole charge at t0. When the VG1 scan begins, the front-gate voltage step DVG1 during the Dt period induces a hole charge variation DQp proportional to IF (ti1) (Eq. (6)). At the next DVG1 step (at t1 = t0 + Dt), the body potential and the hole quasi-Fermi level are computed with the

Fig. 2. (a) Schematic showing the two relevant hole injection mechanisms acting when the body P-drain N+ junction is reverse biased (1). Band-to-band (B2B) tunneling at the gate-to-drain overlap and (2) the reverse drift–diffusion current. (b) Schematic view of the front-gate oxide, body silicon film and back-gate oxide in a SOI MOSFET. The body potential U is discretized with N distinct points. U(K) is the body potential value at a distance (K  1)xH from the front interface with H the step. US1 and US2 are the front and back-surface potentials. The boundary conditions are imposed by the front gate, back gate and flat-band voltages VG1, VG2, VFB1, VFB2, respectively.

M. Bawedin et al. / Solid-State Electronics 54 (2010) 104–114

upgraded total hole charge, i.e. Qp(t1) = Qp(t0) + DQp; this procedure is repeated for the following voltage steps DVG1.

3. Results and discussion 3.1. Dynamic variation of body potential Let’s first introduce the principles of the body potential variations when one interface is driven from inversion or depletion regime into the accumulation mode. At the initial stage (Fig. 3a and b: VG1 = 0 V), both interfaces are in inversion or depletion mode. When the front-gate voltage VG1 starts decreasing from 0 V to negative values, there is channel coupling between the front and back interfaces. The usual, steadystate coupling can be observed as long as VG1 remains higher than the front flat-band voltage VFB1 (0.9 V, Fig. 3). Once VG1 becomes lower (VG1 < VFB1), the standard channel coupling turns off. Nevertheless, the potential keeps decreasing with VG1, by dynamic gate coupling, all over the body, from the front to the back interface (Fig. 3b). The whole body enters into the ’deep depletion’ non-equilibrium regime. Indeed, since the front interface cannot accumulate instantly, i.e. the injected hole charge is lower than the total charge required to reach the steady state, the potential drop arises from the capacitive coupling between the front gate, the back gate, the body and the reverse-biased junctions. In that case, the holes are mainly supplied by the drift–diffusion current through the body-to-drain (source) reverse-biased junction (Fig. 2a, mechanism (2)). It can also be observed that a hump in the hole quasiFermi level takes place (Fig. 3a: VG1 = 1.1 V), when the generated B2B tunneling hole charge becomes higher than the charge supplied by the drift–diffusion current (Fig. 4, see a). Notice that the SRH injection component is negligible here and cannot influence the body potential behavior whatever the gate bias and the scan speed. Next, as VG1 keeps decreasing, a sudden increase of the potential can be observed all over the body (Fig. 3a and c: VG1 < 1.7 V). Since the B2B tunneling generation increases exponentially as VG1 becomes more negative, the total hole charge required to reach

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the steady state can be exceeded. Consequently, the potential starts rising for a VG1 value (1.7 V) which mainly depends on the B2B tunneling injection efficiency, i.e. on the technological parameters in the gate-to-drain overlap region. Obviously, if the scan speed is increased, as the B2B tunneling current is time independent, the completion of the body charge and the minimum of the potential occur for a more negative front-gate voltage value (see also Fig. 5). Finally, the body potential reaches a ‘saturation’ regime (Fig. 3a and c: VG1 < 2 V) when the hole charge supplied by B2B tunneling is balanced by the charge extracted from the body via the forward drift–diffusion current (Fig. 4, see region (c)). Indeed, once the body

Fig. 4. Modeled total hole charge, supplied by drift–diffusion |QpDD| and by B2B tunneling QpB2B, versus decreasing front-gate voltage VG1 (scan speed SS = 1 V/s, same device as in Fig. 3). The circled zones correspond in Fig. 3a to: (a) the hole quasi-Fermi level Wp hump, (b) the Wp cross-over zero value, causing the change in junction current from injection to extraction, and (c) the saturation of potential UB and Wp.

Fig. 3. (a) Modeled hole quasi-Fermi Wp potential in the body, front-surface (US1) and back-surface (US2) potentials plotted versus a decreasing front-gate voltage VG1 whose scan speed is SS = 1 V/s. The corresponding body potential UB(y) versus vertical (y) position is displayed at each 30 mV VG1 step for the VG1 range (b) from 0 to 1.7 V (decreasing UB ;) and (c) from 1.7 V to 2.3 V (increasing UB "). Technological parameters: the thicknesses of silicon film, front-gate oxide and buried oxide are 80 nm, 6 nm and 400 nm, respectively. The channel length and width are 1 lm. The doping levels of n-type polysilicon gate, p-type silicon film, p-type substrate and n-type drain (source) are equal to 1020, 1015, 1015 and 1020 cm3. The front-oxide and back-oxide charges are 5  1010cm2. The source VS, drain VD and back-gate VG2 are grounded (=0 V).

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potential increases enough so that the hole quasi-Fermi level becomes higher than zero, the drift–diffusion current flow is inverted (Fig. 4, see (b)), in other words, the body-to-drain (source) junction becomes forward biased. Therefore, the ‘drift–diffusion’ holes are extracted from the body while the B2B tunneling generation keeps injecting. The compensation of the B2B tunneling injection by the forward drift–diffusion current is a self-limiting mechanism, preventing the body potential to increase endlessly as VG1 becomes more negative. Actually, when VG1 decreases (<2 V) in the ‘saturation’ region, the potential keeps increasing slightly as a result of the balance between the total required body hole charge, the B2B tunneling and the drift–diffusion. The drift–diffusion hole extraction remains marginally lower than the B2B tunneling injection when VG1 is more negative. Hence, the potential increase is slowing down but not totally stopped. Conventional 2D simulators [22] do not take into account the B2B generation component in the total hole current probed at the drain (source) contact; only the influence of the B2B generation on the hole quasi-Fermi level Wp variations and the hole drift–diffusion current IDD (4) can be observed. The advantage of our model is that the contributions of the two currents (B2B and drift–diffusion) can be isolated. The corresponding hole charges QP injected by B2B tunneling QpB2B and adjusted by drift–diffusion QpDD are

plotted in Fig. 4. This figure indicates the bias regions where either mechanism dominates. It also clarifies the origin of the various features observed in the body potential variation (Fig. 3a): hump, minimum and saturation. Our model describes the dynamic potential variation which can occur in fully (FD) as well as in partially (PD) depleted MOSFETs. The main difference between FD and PD devices lies in the coupling efficiency, and therefore depends on the boundary conditions (1) at the front and back gates, on doping and body thickness. Notice that for a bulk device with the gate biased in accumulation and the substrate grounded, the required hole charge is instantaneously supplied and the bulk potential is fixed at zero volt; hence, the gate surface potential is pinned at a negative value around 0.3 V whatever the gate voltage can be [23]. 3.2. Model validation The model was validated for several doping levels and transistor architectures. In this section, the numerical simulation and model results are compared for two devices which differ in terms of silicon film and gate oxide thicknesses. The model accuracy was also verified for various gate scan speeds. The physics models used with the 2D numerical simulator [23] are: the Boltzmann–Dirac statistics for the carrier distribution, the

Fig. 5. Modeled and numerically simulated (Sentaurus) hole quasi-Fermi potential Wp in the body and front-surface US1 potential versus a decreasing front-gate voltage VG1 for several scan speeds SS=(103, 103, 106) V/s. Device (a) has the same technological parameters as in Fig. 3. In device (b) the thicknesses of silicon film, front-oxide and buried oxide are 10 nm, 2 nm and 150 nm, respectively. The channel length L and width W are 0.5 and 1 lm. The front-oxide charge QOX1 is 1  1012 cm2.

M. Bawedin et al. / Solid-State Electronics 54 (2010) 104–114

Shockley–Read–Hall (SRH), the Selberherr impact ionization and the band-to-band (B2B) tunneling (same as in Eq. (5)) for carrier generation, and finally, the continuous Fowler–Nordheim/Direct tunneling model for the gate current. Notice that the B2B tunneling model and all the technological parameters employed in our model are the same as in simulations. The model accuracy is illustrated in Fig. 5 for two different FD SOI MOSFETs with relatively thick body (80 nm, device (a)) and ultrathin body (10 nm, device (b)). The agreement between model and simulation is excellent for a variety of scan speeds. All curves display the specific transient behavior, i.e. the ‘bell shape’ of surface and body potentials when the devices enter into the deep depletion regime. Remark how the non-equilibrium region is amplified for very fast scans. The model reproduces the numerical simulations even for advanced FD transistors with 10 nm body thickness and 2 nm thick gate oxide (Fig. 5b). In this case, the coupling effect is very strong (super-coupling [24]), the potential profile tends to be flat across the film, and the potentials at the two interfaces become superposed. As a consequence of super-coupling and ultrathin gate oxide, the dynamic drop in body potential is significantly reduced and the saturation region occurs at a lower gate bias (VG1 = 1.5 V).

3.3. Impact of technological parameters A key asset of our model is the computation time, drastically reduced (minutes) as compared to full 2D numerical simulations (days). The second advantage is the possibility to identify and quantify the contribution of each source of majority carriers. Thanks to this flexibility, a systematic and refined study of the main technological parameters acting on the dynamic potential behavior was performed. The results show that the dynamics of body potential is governed by B2B tunneling. When this mechanism is artificially blocked, the model and 2D simulations still match, but show a monotonous decrease in body potential (Fig. 6), failing to reproduce the intricate UB signature experimentally observed in Fig. 1b. As a matter of fact, the device parameters modulating the dynamic potential variation are all related to the B2B tunneling efficiency in the gate-to-drain (source) overlap region. These parameters are the gate-oxide thickness tOX1, the drain doping ND and the gate oxide charge QOX1.

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Fig. 7 shows that the B2B tunneling is strongly enhanced when the gate-oxide thickness tOX1 is reduced. Indeed, the electric field ES1 at the front interface increases proportionally with the electric field EOX1 through the gate oxide (Gauss law, ES1 / EOX1 / 1/tOX1). Therefore, the body potential can reach the saturation regime (Fig. 7a) faster, i.e. for less negative VG1. In addition, the technological parameters (tOX1, QOX1) modify the flat-band voltage VFBB of the body and VFBO of the overlap regions (Eq. (7) [2]):

  q  Q OX1 V FBB ¼ /t  log n2i =NA  Npoly  eOX =tOX1   q  Q OX1 V FBO ¼ /t  log ND =Npoly  eOX =tOX1

ð7Þ

For example, if VFBO becomes more positive, the front surface enters into inversion regime for higher (less negative) VG1 values. This means that the surface electric field ES1 and consequently the B2B tunneling generation are enhanced. As indicated in Eq. (7), a heavier drain doping or a lower gate oxide charge tends to amplify B2B tunneling generation because the flat-band voltage VFBO is increased. Notice that, although a thinner gate oxide increases VFBO, the electric field enhancement is primarily due to capacitive coupling. The parameters included in the flat-band voltage (7) impact on the gate coupling in the body as well as in the gate-to-drain overlap region. To make the analysis easier, different values of the body flat-band voltage VFBB were imposed, without examining independently each parameter (front-oxide charge QOX1, polysilicon doping NPoly). All other technological parameters were set to the default values given in Fig. 3. Since (QOX1, NPoly) also affect the body charging, the ‘‘medium” VG1 scan speed of 100 V/s is chosen. This enables to observe the body potential return to equilibrium for quite low |VG1| values. Three VFBB values were tested (1.1, 0.8, +0.2)V. From a technological point of view, the first value could correspond to a high doped N-type polysilicon gate or/and a high front interface oxide charge QOX1, the second is the default case (see Fig. 3 parameters), and the last one is referred to a P-type polysilicon gate. It is also important to take into account this parameter variation effect on the drain flat-band voltage VFBO. Indeed, they can strongly affect the vertical electric field at the drain front surface, and hence, the B2B tunneling injection.

Fig. 6. (a) Modeled body hole quasi-Fermi WpB and front-surface US1 potentials versus a decreasing front-gate voltage VG1 scan for scan speed SS 102, 102 and 109 V/s and (b) the corresponding hole drift–diffusion current Ih. The Ih characteristics become ‘frozen’ for SS > 106 V/s. Only the hole drift–diffusion Eq. (4) is used. Other parameters as in Fig. 3.

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Fig. 7. (a) Modeled front – US1 and back – US2 surface potentials and (b) their corresponding total injected hole drift–diffusion QpDD and B2B tunneling QpB2B charges versus a decreasing front-gate voltage VG1 scan. Three different front-gate-oxide thicknesses tOX1 are compared. The scan speed is 106 V/s. The hole drift–diffusion (4) and B2B tunneling (5) current equations are coupled. Other parameters as in Fig. 3.

When the front flat-band voltage VFBB is increased (from 1.1 V to +0.2 V), the body potential enters in the depletion regime for less negative VG1 (Fig. 8a). This means that, for a given front-gate voltage VG1, the front and backbody potential values are more negative, i.e., the gate-to-channel coupling is considerably improved. For VG1 lower than VFBB, since the gate oxide thicknesses tOX1 and tOX2 remain constant, the body potential slope is not altered whatever the VFBB values (Fig. 8a). Hence, the capacitive coupling can be sensibly improved as it is expected for 1T-DRAM performance. Concerning the injected hole charge efficiency, as the front flatband voltage VFBB increases, it can be seen that the injected hole drift–diffusion charge QpDD is slightly enhanced in the low VG1 range (Fig. 8b, 1 V < VG1 < +0.5 V). Indeed, since UB enters in the depletion regime for a less negative VG1, the drop in hole quasi-Fermi level Wp begins also for a less negative VG1 value (Fig. 8a). Nevertheless, this charge variation is insignificant and cannot disturb the gate-to-channel coupling.

On the other hand, the B2B tunneling charge QpB2B is far more disturbed by the VFBO variations. When VFBO becomes less negative (e.g., due to lower front-interface charge QOX1 and/or the polysilcon doping NPoly), the front-surface drain field is enhanced, as well as the B2B tunneling charge QpB2B injection (Fig. 8b, VFBB from 1.1 V to 0.8 V). This means that the coupling efficiency is improved while the B2B tunneling injection is enhanced. As a result, the steady-state body potential occurs for less negative VG1 values (Fig. 8a). If a P-type polysilicon gate is used (VFBB = +0.2 V), the coupling efficiency is drastically improved, but the counterpart is the B2B tunneling injection enhancement at low negative VG1 values. We can conclude that the improvement of the capacitive coupling is balanced by the increase in the B2B tunneling charge injection. These considerations are very relevant for 1T-DRAM applications. Indeed, a primary requirement is to achieve an excellent capacitive coupling together with the lowest hole charge

Fig. 8. (a) Modeled body hole quasi-Fermi Wp and front-surface US1 potentials and (b) their resulting total injected hole drift–diffusion QpDD and B2B tunneling QpB2BT charges versus a decreasing front-gate voltage VG1 scan. Several front flat-band voltage VFBB values are compared. The scan speeds SS = 106 V/s. The hole drift–diffusion current equation is coupled with the B2B tunneling model.

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injection during memory reading (at low negative VG1). Our results indicate that a compromise will be needed. The influence of the body thickness has been investigated while keeping all other parameters constant. A basic advantage of ultrathin SOI MOSFETs is that the reverse drift–diffusion current is lowered proportionally to tSi as stated in Eq. (4). Nevertheless, the B2B tunneling generation is still the dominant injection mechanism and its efficiency remains intact. Indeed, in the inverted overlap regions, the depletion layer is confined to the front interface since the drain and the source are heavily doped. Actually, the peak of the electric field and B2B tunneling generation are located within 5 nm from the interface [25]. As a result, even if tSi is reduced down to 10 nm, the body potential saturates for the same front-gate bias since the holes accumulate to a large extent near the front interface. 4. Model applications The principles of the transient floating-body potential variations have been established and modeled. There are several practical applications of the model in the field of transient currents, switching of digital circuits, history effects, etc. We will focus on two examples relevant for memory operation. 4.1. Gate current The transient variation of the drain current as the gate voltage switches between two levels is well documented [26,27]. Less attention has been paid to the influence of transient floating potential on the gate current variations [9]. This relationship is enabled by the capacitive coupling in SOI technology. The gate current characteristics are especially important for non-volatile (EEPROM) memory applications since the transient floating-body potential effect can strongly influence their programming times. Fig. 1a and b has already introduced the special characteristics of the gate current and corresponding body potential measured by scanning the front gate from positive to negative values. In this case, the B2B tunneling or leakage currents are not efficient enough to supply holes instantaneously. Notice that similar curves can be

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obtained by scanning the back gate. When one interface (front or back) moves from inversion/depletion into the accumulation regime, the transient gate current IG1 displays unusual, non-monotonic variations. In Fig. 1a, there are two different peaks (around VG1 = 0.5 V and 4 V) and two distinct valleys (around 2 V and 4.5 V). Fig. 1a shows that the positions and levels of the peaks/valleys strongly depend on the VG1 scan speed SS. Faster the scan, more prominent these features are. For 25 V/s scan, the gate current is 1–2 orders of magnitude higher than for 0.1 V/s scan. Fig. 9a shows the similarity in gate current characteristics measured on FD and PD MOSFETs operated in floating-body mode. The devices under test had different Si-film thickness: 120 nm for PD and 40 nm for FD SOI nMOSFETs. For both devices, the gate oxide was 4.5 nm thick, the BOX thickness was 400 nm and lightly-doped drain/source were used. Fig. 9b compares the gate current characteristics measured in PD MOSFET by connecting or not the body contact. When the body contact is grounded, the gate current recovers the usual Fowler– Nordheim tunneling behavior. All above observations suggest that the gate current variations originate from the transient behavior of body potential UD. In order to further investigate this link, the body potential characteristics were monitored on PD devices by using the body contact. The experiment provides the average potential value, through the whole body, as a function of gate-bias scan (Fig. 1a). This measurement is not feasible in FD MOSFETs where no body contact is available. However, the PD results can be extended to FD MOSFETs because the experimental gate currents exhibit similar features (Fig. 9a), and the modeled potential variations are also similar. We can simply formulate the relation between the gate current and the body potential. The dynamic gate-current peaks are directly associated to the transient variations of the body potential UD and the front-gate voltage VG1:

IG1C DðV G1 ðtÞ  UB ðtÞÞ ¼ C Dt

ð8Þ

where C is an adjusting capacitive coefficient. Thanks to the body potential UD extracted from measurements or simulations, the ratio IG1C/C can be calculated and compared

Fig. 9. Measured dynamic gate current IG1 plotted versus decreasing front-gate voltage VG1 scan in (a) FD and PD SOI nMOSFETs, (b) PD SOI nMOSFET with floating and grounded body contact. The gate width and length are 100 lm. The thicknesses of the gate and buried oxides are 4.5 and 400 nm, respectively. The silicon film thicknesses of the FD and PD MOSFETs are 40 and 120 nm. The drain, source and back gate are grounded.

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with the ‘real’, measured IG1M or simulated IG1S, front-gate current. Fig. 10 shows very good match between IG1M/S current and IG1C/C ratio, demonstrating that Eq. (8) can accurately reproduce (for VG1 > 4 V) and explain the transient gate current behavior. In the 4 V < VG1 < 0 V range, IG1 is dominated by the UD(VG1) variations following Eq. (8). This is confirmed in Fig. 10a by the superposition of the two experimental characteristics, IG1R and IG1C/C, in PD MOSFETs. For very negative VG1 (<4 V), the large increase of IG1R denotes the onset of Fowler–Nordheim tunneling, which has not been included in Eq. (8). Fig. 10b shows the case of a FD MOSFET. The gate current has been numerically simulated whereas the body potential profile has been calculated with our model. Since the front-surface potential is known, we can rewrite Eq. (8) in an accurate form:

IG1C DðV G1 ðtÞ  US1 ðtÞÞ ¼ C1 Dt

ð9Þ

where coefficient C1 is well defined and stands for the equivalent quasi-static oxide capacitance. A perfect agreement between the two curves is observed in Fig. 10b, confirming the validity of both the model and Eq. (9). (Again, for VG1 < 4 V, the gate current becomes dominated by Fowler–Nordheim tunneling.) The difference between the accurate Eq. (9) and the empirical Eq. (8) comes from the fact that the measured potential UD is an average value over the silicon film and, therefore, differs from the front-interface potential US1. 4.2. Floating-body DRAM memory If the transient FBE can be considered as a parasitic mechanism for SOI non-volatile EEPROM, it turns into an essential advantage for the emerging family of capacitor-less 1T-DRAMs. Since the scaling of conventional bulk-Si DRAMs is compromised by the difficulty of squeezing the storage capacitor, the solution, offered by the SOI technology, is to eliminate the capacitor. The floating body of SOI transistors can indeed be used for charge storage. All 1TDRAMs take advantage of the floating-body effects in SOI transistors. Bit ‘1’ reflects the presence of majority carriers in the body which increases the potential and the drain current, whereas bit ‘0’ is characterized by a lower current achieved by the removal of majority carriers from the body.

In the MSDRAMs proposed in [8], the transient variation of the floating-body potential impacts on the drain current characteristics leading to a remarkable hysteresis phenomenon (Fig. 11), the Meta-Stable Dip (MSD) effect [4]. MSD is a combination of gate coupling and floating-body transient mechanisms. The back channel is used to probe the presence (bit ‘1’) or absence (bit ‘0’) of majority carriers at the front interface. The MSD hysteresis results in a very large difference between the forward-mode and reversemode currents, useful for memory applications. Bit ‘1’ is programmed by applying a sufficiently negative gate bias VG1 which enables B2B tunneling for body charging. When the front accumulation layer is completed, the device operates in steady state and the back-channel current is high. Bit ‘0’ is set with VG1 = 0. The bits are read in the memory window (4 < VG1 < 2 V, Fig. 11a). Reading ‘0’ triggers the dynamic drop in the body potential (Fig. 11b), as discussed in Figs. 3–7. The back interface becomes depleted and the drain current is off. Unlike bit ‘1’, bit ‘0’ corresponds to deep depletion and is eventually destroyed by majority carrier generation, needing to be refreshed. Our program is helpful for understanding the programming and reading mechanisms. It also serves to optimize the MSDRAM architecture and bias, in order to achieve very long retention time, short programming time and low-voltage operation. An example is given in Fig. 12a. From the potential variation, it is clear that bit ‘1’ should be programmed with VG1 < 4.5 V, otherwise B2B tunneling is not able to supply enough holes to the front accumulation channel. The memory window corresponds to the bias range where the back interface is deep depleted. Fig. 12 also indicates the strategy for selecting the back-gate voltage. If VG2 is low (10 V), the back channel can easily be suppressed because the channel coupling is strong. The drop in back-surface potential parallels that of the front-surface potential (Fig. 12a and b), during the VG1 reverse scan. The problem is that the ‘1’ bit current is too low. Conversely, for high VG2 (40 V), the back channel is always in strong inversion and hardly affected by the front-gate bias (Fig. 12a). This is because the back-surface potential is pinned to 0.5 V (Fig. 12c), regardless of VG1 scan. The back channel cannot be cut-off and the MSD effect vanishes. A trade-off is observed for VG2 = 20 V. This bias is low enough to enable channel-to-gate coupling and large enough to guarantee a reliable measure of ‘1’ bit current.

Fig. 10. Gate current versus a decreasing front-gate voltage VG1 scan in the (a) measured PD (IG1M) and (b) simulated FD (IG1S) SOI nMOSFET. The devices are tested for a scan speed of 1 V/s. For each current characteristic, the IG1C/C ratio is calculated with Eq. (8). The drain, source and back gate are grounded, whereas the body is floating [9].

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Fig. 11. Measured (a) drain current ID and (b) corresponding body potential UB plotted versus a decreasing (reverse) and increasing (direct) front-gate-bias scan. The MSD hysteresis effect is amplified in the memory window. FD nMOSFET with back-gate voltage VG2 = 20 V. The nMOSFET has a 400 nm BOX and 10 nm thick gate oxide. The 80 nm thick Si film is 5  1015 cm3 doped. The channel length and width are 1.5 and 20 lm.

Fig. 12. (a) Modeled front-surface (US1) and back-surface (US2) body potentials versus decreasing front-gate voltage VG1 for different back-gate voltages VG2. The corresponding body potential profiles UB(y) versus vertical position is displayed for VG2 equal to (b) 10 V and (c) 40 V. Same parameters as in Fig. 3. VG1 is varied with SS = 106 V/s speed and 50 mV steps.

Two aspects deserve attention. First, the variation of the frontsurface potential is dictated by the gate-bias scan and depends weakly on VG2. Second, since VG2 has no significant impact on the hole injection rate (via B2B tunneling and drift–diffusion) and on the memory window position, the body potential minimum occurs for the same VG1 bias (3 V, Fig. 12a). The model is instrumental for rapidly comparing architectural and biasing solutions to enhance the memory speed and retention capability. The crucial point is to intensify B2B injection while writing ‘1’ and to minimize drift–diffusion and B2B tunneling during the reading mode. Carrier injection by B2B tunneling can be tuned by using appropriate technology modules: high-K dielectric, lightly-doped source and drain, etc. Drain engineering is also

important for preventing the charge loss in retention mode. The gate and drain voltages are selected to reinforce B2B for programming ‘1’ and to suppress it during stand-by.

5. Conclusion The main current components driving the dynamic body potential variation in depletion and accumulation regimes were investigated in fully-depleted SOI MOSFETs. TCAD 2D numerical simulations have been used to identify the dominant phenomena which must be taken into account, namely the drift–diffusion and B2B tunneling injection. Nevertheless, since the simulator is

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not able to provide these two current contributions separately, the interpretation of the experimental results was difficult and unclear. To solve the problem, we have proposed a physics-based model where the numerically discretized Poisson equation in the silicon film is coupled with analytical boundary conditions and current equations. The link between the body potential and the injected hole charge was achieved via the discretized sum of body hole concentration. Main advantages of our model are: implementation simplicity, fast computation time, convergence improvement even for extremely slow gate-voltage scan. The possibility to separate the B2B tunneling current component from the drift–diffusion one is a remarkable asset, which enabled us to explain how the steady state is gradually reached when one interface is becoming accumulated in a fully-depleted SOI MOSFET. This discrimination is also useful for optimizing independently the B2B tunneling and drift–diffusion currents, which are key ingredients for floating-body memory applications. The effect of the transient body potential variations on the gate current in time domain was revealed and explained. The complex behavior of the gate current, due to floating-body even in FD MOSFETs, had escaped attention in the past, mainly because it occurs in accumulation and does not affect the operation of digital SOI circuits. However, the dynamic floating-body effects can modify the charging and discharging capability of SOI EEPROMs and DRAMs. These mechanisms will presumably become even more critical with device scaling. Acknowledgements This work has been sponsored by EUROSOI+ and SINANO projects. References [1] Colinge JP. Silicon-on-insulator technology: materials to VLSI. 3rd ed. Springer; 2005. [2] Cristoloveanu S, Li S. Electrical characterization of silicon on insulator materials and devices. Boston (USA): Kluwer Academic Publishers; 1995. [3] Cassé M, Pretet J, Cristoloveanu C, Poiroux T, Fenouillet-Beranger C, Fruleux F, et al. Gate-induced floating-body effect in fully depleted SOI MOSFETs with tunneling oxide and back-gate biasing. J Solid-Sate Electron 2004;48(7):1243–7. [4] Bawedin M, Cristoloveanu S, Yun JG, Flandre D. A new memory effect (MSD) in fully depleted SOI MOSFETs. J Solid-Sate Electron 2005;49(9):1547–55.

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