- Email: [email protected]
E-beam detector devices for IC controllability
Microelectromc Elsevier
Engmcermg
16 (1YYZ) 4654.12 465
E-BEAM DETECTOR Jordi MADRENAS
DEVICES FOR IC CONTROLLABILITY
and Joan CABESTANY
Departament d’Enginyeria Electronica. Universitat Politecnica de Catalunya UPC. Jorge Girona Salgado, s/n. 08034 BARCELONA
(SPAIN).
Fax: +34-3-401.68.01 Tel: +34-3-401.67.47
Abstract Electron-beam detecting devices for IC controllability purposes are presented in this paper. For an electron-beam IC controlling cell to be practical, it should detect the beam at normal observation beam energies (less than 2 kV), be small in size, and have a short response time. Logic state generation has been experimentally achieved by charging a MOS transistor floating gate or injecting current to a parasitic bipolar transistor floating base. To improve speed, electron beam sensitive CMOS devices (floating-gate MOST, floating-base parasitic BJT) and amplifiers have been designed and manufactured. Simulations show speed ranges of microseconds.
1. INTRODUCTION
The performance of Electron Beam Testing techniques in functional analysis and fault detection of ICs is well known. The surface voltages of the IC can be observed because of changes in the collection efficiency of secondary electrons. To measure the surface voltages, the electron beam must interact with the IC surface. Damage in the circuit will not be produced if the beam energy is low enough. Accelerating voltages up to 2 kV are generally considered safe for observation of MOS ICs without damaging it or changing in a high degree its behavior [l-3]. However, the effects of the beam on the circuit could be used advantadgeously to change the circuit behavior (reconfiguration) or to generate logic states (controllability) inside the IC, without additional pads. This can be a complement for the observation capabilities of EBT.
0167-9317/92/$05.00
0 1992 - Elsevier Science Publishers
B.V.
All rights reserved.
466
J. Madrenas, J. Cabestany I E-beam detector devices for IC controllability
Some attempts have been done to achieve reconfiguration or controllability detecting the electron beam. This can be done by generating electron-hole pairs in a reverse biased PN junction [4], by charging the passivation layer over a floating-gate MOS transistor [5], or by charging the upper metal layer connected to the floating-gate MOS transistor [6]. It is necessary for a practical controlling circuit that it detects the electron beam at low energies (compatible with observation ranges of energy, < 2 kV), to be small in size to optimize silicon area occupation and as fast as possible to provide an acceptable testing waveform. To accomplish these conditions, the floating metal charging seems to be the most promising approach. In this work, the design, simulation, and some experimental results of two different detector circuits are presented: a floating-gate MOS transistor-based differential amplifier, and a parasitic floating-base bipolar transistor-based detector circuit.
2. FLOATING-GATE MOS TRANSISTOR-BASED DIFFERENTIAL AMPLIFIER
The floating gate of a MOS transistor is connected to the upper metal layer. When the beam is addressed to the metal, charging of the capacitance is produced. The charging can be positive or negative, depending on the secondary emission coefficient. A guard ring of metal is layed around the target metal. Depending on the voltage of the guard ring, the local field effect can be changed [7] and, in some degree the electron collection of the target metal. When the target voltage is positive and the guard ring is connected to ground the electric field will push the secondary electrons of lower energy back to the target.
2.1. &II design The detector circuit is a basic MOS differential amplifier, shown in Figure 1. The inverting and non-inverting input MOS transistors gates (M3 and M4 in Fig. 1) are virtually floating and biased to V&2 through the high impedance of an inverse PN junction (M5 and M6) [2]. The symmetrical differential amplifier is thus in equilibrium. Small differential voltage changes produced by the beam current in one of the floating gates will be amplified. A Schmitt Trigger buffer at the output restores the logic value and prevents the generation of false logic states due to some noise or input offset of the amplifier. Some variations of the cell have been designed and sent to manufacturing. In Figure 7, a microphotograph of the manufactured circuit is shown. The described cell is placed in the upper left side of the chip, and its logic output can be measured in the upper left pad. 2.2. Simulation For a first estimation, let us assume that 1 nA constant current can be collected from the beam by the target metal, and that its capacity to ground is of the order of 0.1
J. Madrenas,
467
J. Cabestany I E-beam detector devices for IC controllability VDD P
Fig. 1. Floating-gate
MOS E-beam
detecting
cell.
pF. Under these conditions, 10 microseconds are enough to generate a 100 mV voltage increment on the target metal. The basic cell of Figure 1 has been simulated, and the results are presented in Figure 2. When the beam current charges the target, slight changes in the voltage of the M3 gate are produced. The voltage difference with the M4 gate voltage is amplified and the logic state of V,,, changes. Observe the transitions of V, and V,,, when V, follows a sinusoidal waveform around the voltage of polarisation V&2. Taking into account the considerations of the former paragraph, an amplitude of 100 mV has been considered. The selected frequency is 100 kHz. From Fig. 2 it can be seen that a response of some microseconds is easily achieved provided the beam is able to produce the supposed voltage change. The transition of the output can be done by charging either one of the two targets, because of the symmetry of the design. In order to make sure the output will remain at a fixed logic state when the cell is not activated, a slight assimmetry in the transistors could be created. 23. Experimental results Up to now, the experimental work on the floating-gate transistor approach
Fig. 2. Differential amplifier response simulation.
cell
468
J. Madrenas, J. Cabestany 1 E-beam detector devices for IC controllability
consists on the charging of MOST gates using a 1 kV and 2 kV accelerating voltages, and beam currents of approximately 1 nA Waveforms in the order of 100 Hz have been generated. Even though it has not been possible yet to experiment with the differential cell, it seems reasonable to suppose that the circuit can easily improve in some orders of magnitude that frequency.
3. PARASITIC
FLOATING-BASE
BIPOLAR
TRANSISTOR
DETECTOR
The second approach is based on the capability of implementing bipolar transistors in a CMOS technology [8]. The main advantage that a bipolar transistor (BJT) presents in front of the MOS transistor is the smaller base capacitance which could lead to faster detection times. The functioning principle is based on the injection of current in the floating base, which is amplified by the device. Since the BJT acts as a current amplifier, it could ideally follow exactly the temporal variations of the electron beam. In practise the real device will have some limiting factors, as junction capacitances, base transit time, etc. Using this kind of device, modelling becomes a problem, since the manufacturer only provides the parameters of the supported active devices, namely, the NMOS and PMOS transistors for the CMOS technology. In that technology, vertical-type and lateral-type transistors are inherently available. The SPICE parameters of the vertical transistor have been extracted using a program which calculates electrical parameters from technology parameters. SPICE parameters of a minimum dimension parasitic PNP BJT in a 1.5micron n-well CMOS technology have been obtained and in some structures the forward current gain is higher than 10 at base currents of 1 nA. It should be noted that technological parameters can have large deviations and some margin of error is provided.
Guard r’“(
.__
Fig. 3. Floating-base
BJT detecting
cell.
J. Madrenas,
J. Cahestany i E-beam detector devices for IC controllability
469
3.1. Cell design The basic floating-base detector circuit is shown in Figure 3. The functioning principle is the following. The PNP switch is normally turned off, because no current flows through the floating base. Ml and M2 form a current mirror limited by the polarising resistor R. So M2 will discharge the gate of M4, V, will be 0 V and the output remains at a low logic state. When the beam current turns on the PNP switch, a current flows through M2, and V, will rise. If the current is enough to make V, > V, (threshold voltage) of the M4 transistor, it will eventually turn on and the logic value of the output will change to the high logic state. Note that PNP devices are used, since available technology was n-well type. Darlington configurations of 3 or 4 BJT transistors have been chosen to have enough current gain. For a good integration, the resistor is implemented using PMOS transistors. M3 and M4 form a pseudo-NMOS inverter [9], restoring the logic levels, and the pair M5-M6 form an inverting buffer. If beam current is amplified enough, the obtained current will drive the gate of a MOS transistor in some microseconds. As in the floating-gate case, different variations of the cell have been designed and manufactured. The chip microphotograph is shown in Figure 8.
*or)
3.2. Simulation The described circuit (Fig. 3) has 4 10 0 6 2 been simulated, and the voltage tie) waveforms obtained are presented in Fig. 4. Floating-base cell response and the intermediate Figure 4. VIN, V,,, simulation. voltages V, and V, are displayed. Vi, is the voltage that appears at the floating base when a sinusoidal beam current (amplitude: 0.2 nA, DC current: 0.2 nA) is injected at a frequency of 100 kHz. When the injected current is small (in Fig. 4, between 6 us and 9 us), Vi, is higher and V, is kept low, as well as V,,,. When the amplified beam current raises V, up to some value higher than 1 V, then the output switches to the high logic state. The peak voltage value of V,, near to 7.5 us is achieved when the injected current is 0. Note that the inverting stages M3-M4 and M5-M6 regenerate the voltage to achieve a well-defined logic value. Smaller values of current can turn on the switch and a better behavior than in the case of the floating-gate cell is obtained. However, the modelling of the BJT cannot be as reliable as the one for the MOST.
470
J. Madrenas.
J. Cabestany I E-beam detector devices for IC controllability
3.3. Experimental results The lower right cell of Fig. 8 is shown in more detail in Figure 5. The cell corresponds to the circuit of Fig. 3. In the center of the picture, the guard ring and the floating-base target can be observed. The output is brought to the lower right output pad, so the obtained waveform can be observed with an oscilloscope. The working conditions were V, = 1 kV I, = 3 nA As stated before, when the beam is not addressed to the target, the output remains to low logic state. When the beam is continuously injecting current to the target, the output is set to high logic state. So the functional static behavior of the circuit is correct. Some dynamic measurements have been done. The beam has been scanned in a region containing the target. When scanning lines out of the target, the output remains low. When the beam passes across the target, the output switches to the logic high state, and it remains high while scanning lines across the target, even if the beam is out of it.
Fig. 5. Parasitic floating-base BJT e-beam detector
cell.
Fig. 6. Floating-base cell switching.
This is, the output switches at an image frequency and not at a line frequency, because the response time is not fast enough to follow the line frequency. In Figure 6 a microphotograph of such a scanning is shown. Three horizontal bands are observed. The
J. Madrenas,
J. Cabestany
I E-beam
detector
devices
471
for IC controllability
middle band corresponding to the high logic state of the output, when the beam makes the switch turn on. The upper and lower bands correspond to the low state of the output. The states are distinguishable because of the effects that the voltage changes produce on the image. The observed bands correspond to the observed logic states in the oscilloscope. The guard ring is connected to ground for a better electron collection. Waveforms have been observed at a 50 Hz image frequency. Up to not been possible to do further experimental work, and determine operating frequency. Anyway, the response time of the circuit is worse as reason thought is that the behavior of the bipolar transistors differs from This can change the working conditions of the circuit.
Fig. 7. Floating-gate MOS E-Beam detector IC.
Fig. 8. Parasitic floating-base BJT E-Beam detector
the date, it has the maximum expected. The the modelling.
IC.
4. CONCLUSIONS
Electron-beam controllability of ICs at observation beam energies has been obtained. The beam can inject current in a floating Al metal, and thus, be detected to generate in-circuit logic states. Experimentally obtained frequencies are under the 100 Hz. Cells dimensions are smaller than 100 urn x 100 urn, a usual size for a pad.
472
J. Madrenas, J. Cahestany I E-beam detector devices for IC controllability
Two efficient e-beam detector circuits for e-beam IC controllability have been presented. The simulation calculations show that the response times will be in the microsecond range, which is an acceptable value for many test purposes and a promising figure towards an optimized detector circuit. The floating-gate MOS transistor is inherently slow due to its gate capacitance, so using it in the linear region improves its response since only small voltage changes are needed to detect the beam. The new use of the parasitic bipolar transistor that can be implemented in CMOS technology as a detector device has been reported. Electrical parameters of the BJT have been extracted and current gains higher than 10 can be expected. As a drawback, the modelling of the BJT cannot be so reliable as that for the MOST. The two designs have been manufactured, and some experimentation done. However, it has not been possible to provide final results for the presented cells. Present work is directed to further experimentation, and to the determination of the most performant approach, in terms of detection speed. The fact is that both are suitable to generate logic states at lower frequencies than expected.
5. ACKNOWLEDGMENT
support
The authors would like to thank for the experimental activities.
the TIM3
Laboratory
from
Grenoble
their
6. REFERENCES
1 Menzel E., Kubalek E., Scanning Electron Microsc., 305322, 1981. 2 Wolfgang E., “Electron Beam Testing”, Handbook of advanced semiconductor technology and computer systems, Van Nostrand Reinhold, 148-180, 1988. 3 Ura K., Fujioka H., “Electron Beam Testing”, Hawkes P.W., ed., Advances in electronics and electron physics, Vol. 73, New York, Academic Press, 233-317, 1989. 4 D. Micollet, “Etude de la controlabilite des circuits integres par faisceaux d’electrons”, Doctoral Thesis, INPG, France, 1988. 5 P. Girard et al., Microelec Eng, 12, 1990. 6 P. Nouet et al., Intl. Workshop on Defect and Fault Tolerance in VLSI Systems, Grenoble, France, 1990. 7 K. Nakamae et al., J. Phys. D, 14, 1981. 8 Haskard M.R., Analog VLSI Design, Prentice Hall, 1988. 9 Weste N., Eshraghian K., Principles of CMOS VLSI Design, Addison-Wesley Publishing Company, 1985.
Engmcermg
16 (1YYZ) 4654.12 465
E-BEAM DETECTOR Jordi MADRENAS
DEVICES FOR IC CONTROLLABILITY
and Joan CABESTANY
Departament d’Enginyeria Electronica. Universitat Politecnica de Catalunya UPC. Jorge Girona Salgado, s/n. 08034 BARCELONA
(SPAIN).
Fax: +34-3-401.68.01 Tel: +34-3-401.67.47
Abstract Electron-beam detecting devices for IC controllability purposes are presented in this paper. For an electron-beam IC controlling cell to be practical, it should detect the beam at normal observation beam energies (less than 2 kV), be small in size, and have a short response time. Logic state generation has been experimentally achieved by charging a MOS transistor floating gate or injecting current to a parasitic bipolar transistor floating base. To improve speed, electron beam sensitive CMOS devices (floating-gate MOST, floating-base parasitic BJT) and amplifiers have been designed and manufactured. Simulations show speed ranges of microseconds.
1. INTRODUCTION
The performance of Electron Beam Testing techniques in functional analysis and fault detection of ICs is well known. The surface voltages of the IC can be observed because of changes in the collection efficiency of secondary electrons. To measure the surface voltages, the electron beam must interact with the IC surface. Damage in the circuit will not be produced if the beam energy is low enough. Accelerating voltages up to 2 kV are generally considered safe for observation of MOS ICs without damaging it or changing in a high degree its behavior [l-3]. However, the effects of the beam on the circuit could be used advantadgeously to change the circuit behavior (reconfiguration) or to generate logic states (controllability) inside the IC, without additional pads. This can be a complement for the observation capabilities of EBT.
0167-9317/92/$05.00
0 1992 - Elsevier Science Publishers
B.V.
All rights reserved.
466
J. Madrenas, J. Cabestany I E-beam detector devices for IC controllability
Some attempts have been done to achieve reconfiguration or controllability detecting the electron beam. This can be done by generating electron-hole pairs in a reverse biased PN junction [4], by charging the passivation layer over a floating-gate MOS transistor [5], or by charging the upper metal layer connected to the floating-gate MOS transistor [6]. It is necessary for a practical controlling circuit that it detects the electron beam at low energies (compatible with observation ranges of energy, < 2 kV), to be small in size to optimize silicon area occupation and as fast as possible to provide an acceptable testing waveform. To accomplish these conditions, the floating metal charging seems to be the most promising approach. In this work, the design, simulation, and some experimental results of two different detector circuits are presented: a floating-gate MOS transistor-based differential amplifier, and a parasitic floating-base bipolar transistor-based detector circuit.
2. FLOATING-GATE MOS TRANSISTOR-BASED DIFFERENTIAL AMPLIFIER
The floating gate of a MOS transistor is connected to the upper metal layer. When the beam is addressed to the metal, charging of the capacitance is produced. The charging can be positive or negative, depending on the secondary emission coefficient. A guard ring of metal is layed around the target metal. Depending on the voltage of the guard ring, the local field effect can be changed [7] and, in some degree the electron collection of the target metal. When the target voltage is positive and the guard ring is connected to ground the electric field will push the secondary electrons of lower energy back to the target.
2.1. &II design The detector circuit is a basic MOS differential amplifier, shown in Figure 1. The inverting and non-inverting input MOS transistors gates (M3 and M4 in Fig. 1) are virtually floating and biased to V&2 through the high impedance of an inverse PN junction (M5 and M6) [2]. The symmetrical differential amplifier is thus in equilibrium. Small differential voltage changes produced by the beam current in one of the floating gates will be amplified. A Schmitt Trigger buffer at the output restores the logic value and prevents the generation of false logic states due to some noise or input offset of the amplifier. Some variations of the cell have been designed and sent to manufacturing. In Figure 7, a microphotograph of the manufactured circuit is shown. The described cell is placed in the upper left side of the chip, and its logic output can be measured in the upper left pad. 2.2. Simulation For a first estimation, let us assume that 1 nA constant current can be collected from the beam by the target metal, and that its capacity to ground is of the order of 0.1
J. Madrenas,
467
J. Cabestany I E-beam detector devices for IC controllability VDD P
Fig. 1. Floating-gate
MOS E-beam
detecting
cell.
pF. Under these conditions, 10 microseconds are enough to generate a 100 mV voltage increment on the target metal. The basic cell of Figure 1 has been simulated, and the results are presented in Figure 2. When the beam current charges the target, slight changes in the voltage of the M3 gate are produced. The voltage difference with the M4 gate voltage is amplified and the logic state of V,,, changes. Observe the transitions of V, and V,,, when V, follows a sinusoidal waveform around the voltage of polarisation V&2. Taking into account the considerations of the former paragraph, an amplitude of 100 mV has been considered. The selected frequency is 100 kHz. From Fig. 2 it can be seen that a response of some microseconds is easily achieved provided the beam is able to produce the supposed voltage change. The transition of the output can be done by charging either one of the two targets, because of the symmetry of the design. In order to make sure the output will remain at a fixed logic state when the cell is not activated, a slight assimmetry in the transistors could be created. 23. Experimental results Up to now, the experimental work on the floating-gate transistor approach
Fig. 2. Differential amplifier response simulation.
cell
468
J. Madrenas, J. Cabestany 1 E-beam detector devices for IC controllability
consists on the charging of MOST gates using a 1 kV and 2 kV accelerating voltages, and beam currents of approximately 1 nA Waveforms in the order of 100 Hz have been generated. Even though it has not been possible yet to experiment with the differential cell, it seems reasonable to suppose that the circuit can easily improve in some orders of magnitude that frequency.
3. PARASITIC
FLOATING-BASE
BIPOLAR
TRANSISTOR
DETECTOR
The second approach is based on the capability of implementing bipolar transistors in a CMOS technology [8]. The main advantage that a bipolar transistor (BJT) presents in front of the MOS transistor is the smaller base capacitance which could lead to faster detection times. The functioning principle is based on the injection of current in the floating base, which is amplified by the device. Since the BJT acts as a current amplifier, it could ideally follow exactly the temporal variations of the electron beam. In practise the real device will have some limiting factors, as junction capacitances, base transit time, etc. Using this kind of device, modelling becomes a problem, since the manufacturer only provides the parameters of the supported active devices, namely, the NMOS and PMOS transistors for the CMOS technology. In that technology, vertical-type and lateral-type transistors are inherently available. The SPICE parameters of the vertical transistor have been extracted using a program which calculates electrical parameters from technology parameters. SPICE parameters of a minimum dimension parasitic PNP BJT in a 1.5micron n-well CMOS technology have been obtained and in some structures the forward current gain is higher than 10 at base currents of 1 nA. It should be noted that technological parameters can have large deviations and some margin of error is provided.
Guard r’“(
.__
Fig. 3. Floating-base
BJT detecting
cell.
J. Madrenas,
J. Cahestany i E-beam detector devices for IC controllability
469
3.1. Cell design The basic floating-base detector circuit is shown in Figure 3. The functioning principle is the following. The PNP switch is normally turned off, because no current flows through the floating base. Ml and M2 form a current mirror limited by the polarising resistor R. So M2 will discharge the gate of M4, V, will be 0 V and the output remains at a low logic state. When the beam current turns on the PNP switch, a current flows through M2, and V, will rise. If the current is enough to make V, > V, (threshold voltage) of the M4 transistor, it will eventually turn on and the logic value of the output will change to the high logic state. Note that PNP devices are used, since available technology was n-well type. Darlington configurations of 3 or 4 BJT transistors have been chosen to have enough current gain. For a good integration, the resistor is implemented using PMOS transistors. M3 and M4 form a pseudo-NMOS inverter [9], restoring the logic levels, and the pair M5-M6 form an inverting buffer. If beam current is amplified enough, the obtained current will drive the gate of a MOS transistor in some microseconds. As in the floating-gate case, different variations of the cell have been designed and manufactured. The chip microphotograph is shown in Figure 8.
*or)
3.2. Simulation The described circuit (Fig. 3) has 4 10 0 6 2 been simulated, and the voltage tie) waveforms obtained are presented in Fig. 4. Floating-base cell response and the intermediate Figure 4. VIN, V,,, simulation. voltages V, and V, are displayed. Vi, is the voltage that appears at the floating base when a sinusoidal beam current (amplitude: 0.2 nA, DC current: 0.2 nA) is injected at a frequency of 100 kHz. When the injected current is small (in Fig. 4, between 6 us and 9 us), Vi, is higher and V, is kept low, as well as V,,,. When the amplified beam current raises V, up to some value higher than 1 V, then the output switches to the high logic state. The peak voltage value of V,, near to 7.5 us is achieved when the injected current is 0. Note that the inverting stages M3-M4 and M5-M6 regenerate the voltage to achieve a well-defined logic value. Smaller values of current can turn on the switch and a better behavior than in the case of the floating-gate cell is obtained. However, the modelling of the BJT cannot be as reliable as the one for the MOST.
470
J. Madrenas.
J. Cabestany I E-beam detector devices for IC controllability
3.3. Experimental results The lower right cell of Fig. 8 is shown in more detail in Figure 5. The cell corresponds to the circuit of Fig. 3. In the center of the picture, the guard ring and the floating-base target can be observed. The output is brought to the lower right output pad, so the obtained waveform can be observed with an oscilloscope. The working conditions were V, = 1 kV I, = 3 nA As stated before, when the beam is not addressed to the target, the output remains to low logic state. When the beam is continuously injecting current to the target, the output is set to high logic state. So the functional static behavior of the circuit is correct. Some dynamic measurements have been done. The beam has been scanned in a region containing the target. When scanning lines out of the target, the output remains low. When the beam passes across the target, the output switches to the logic high state, and it remains high while scanning lines across the target, even if the beam is out of it.
Fig. 5. Parasitic floating-base BJT e-beam detector
cell.
Fig. 6. Floating-base cell switching.
This is, the output switches at an image frequency and not at a line frequency, because the response time is not fast enough to follow the line frequency. In Figure 6 a microphotograph of such a scanning is shown. Three horizontal bands are observed. The
J. Madrenas,
J. Cabestany
I E-beam
detector
devices
471
for IC controllability
middle band corresponding to the high logic state of the output, when the beam makes the switch turn on. The upper and lower bands correspond to the low state of the output. The states are distinguishable because of the effects that the voltage changes produce on the image. The observed bands correspond to the observed logic states in the oscilloscope. The guard ring is connected to ground for a better electron collection. Waveforms have been observed at a 50 Hz image frequency. Up to not been possible to do further experimental work, and determine operating frequency. Anyway, the response time of the circuit is worse as reason thought is that the behavior of the bipolar transistors differs from This can change the working conditions of the circuit.
Fig. 7. Floating-gate MOS E-Beam detector IC.
Fig. 8. Parasitic floating-base BJT E-Beam detector
the date, it has the maximum expected. The the modelling.
IC.
4. CONCLUSIONS
Electron-beam controllability of ICs at observation beam energies has been obtained. The beam can inject current in a floating Al metal, and thus, be detected to generate in-circuit logic states. Experimentally obtained frequencies are under the 100 Hz. Cells dimensions are smaller than 100 urn x 100 urn, a usual size for a pad.
472
J. Madrenas, J. Cahestany I E-beam detector devices for IC controllability
Two efficient e-beam detector circuits for e-beam IC controllability have been presented. The simulation calculations show that the response times will be in the microsecond range, which is an acceptable value for many test purposes and a promising figure towards an optimized detector circuit. The floating-gate MOS transistor is inherently slow due to its gate capacitance, so using it in the linear region improves its response since only small voltage changes are needed to detect the beam. The new use of the parasitic bipolar transistor that can be implemented in CMOS technology as a detector device has been reported. Electrical parameters of the BJT have been extracted and current gains higher than 10 can be expected. As a drawback, the modelling of the BJT cannot be so reliable as that for the MOST. The two designs have been manufactured, and some experimentation done. However, it has not been possible to provide final results for the presented cells. Present work is directed to further experimentation, and to the determination of the most performant approach, in terms of detection speed. The fact is that both are suitable to generate logic states at lower frequencies than expected.
5. ACKNOWLEDGMENT
support
The authors would like to thank for the experimental activities.
the TIM3
Laboratory
from
Grenoble
their
6. REFERENCES
1 Menzel E., Kubalek E., Scanning Electron Microsc., 305322, 1981. 2 Wolfgang E., “Electron Beam Testing”, Handbook of advanced semiconductor technology and computer systems, Van Nostrand Reinhold, 148-180, 1988. 3 Ura K., Fujioka H., “Electron Beam Testing”, Hawkes P.W., ed., Advances in electronics and electron physics, Vol. 73, New York, Academic Press, 233-317, 1989. 4 D. Micollet, “Etude de la controlabilite des circuits integres par faisceaux d’electrons”, Doctoral Thesis, INPG, France, 1988. 5 P. Girard et al., Microelec Eng, 12, 1990. 6 P. Nouet et al., Intl. Workshop on Defect and Fault Tolerance in VLSI Systems, Grenoble, France, 1990. 7 K. Nakamae et al., J. Phys. D, 14, 1981. 8 Haskard M.R., Analog VLSI Design, Prentice Hall, 1988. 9 Weste N., Eshraghian K., Principles of CMOS VLSI Design, Addison-Wesley Publishing Company, 1985.