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ECRL-based low power flip-flop design
Microelectronics Journal Microelectronics Journal 31 (2000) 365–370 www.elsevier.com/locate/mejo
ECRL-based low power flip-flop design K.W. Ng, K.T. Lau* Division of Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Block S1-B1 a-12, Singapore 639798, Singapore Accepted 17 December 1999
Abstract The efficient charge recovery logic (ECRL) is reported as a promising candidate for low-power applications. However, in the design of digital systems, essential building blocks such as the flip-flops cannot be neglected. In this paper, adiabatic switching or energy recovery technique is used in the design of low-power flip-flops. In particular, SR and JK flip-flop designs based on the ECRL architecture are proposed. From the HSPICE simulation results, these adiabatic flip-flops have shown significant improvement in terms of power consumption over their CMOS counterparts. In addition, the design of an adiabatic sequential circuit is illustrated using the example of a 4-bit binary counter. 䉷 2000 Elsevier Science Ltd. All rights reserved. Keywords: Efficient charge recovery logic; Adiabatic circuits; SR flip-flop; JK flip-flop
1. Introduction In the recent years, there has been a growing interest in low power VLSI design. Many low power design techniques have emerged from universities, research laboratories and the industry. One of the promising techniques in the design of low power digital circuits is to apply the concept of adiabatic switching or energy recovery. This approach is based on the second law of thermodynamics, which points the way of recycling switching energy. When adiabatic switching is used, energy that would otherwise be dissipated as heat is being recovered in order to reduce the power dissipation. Several adiabatic logic architectures have been reported. Most of these adiabatic logic families use either diodes for precharge [1–3], or a pair of cross-coupled PMOS transistors for both precharge and evaluation [4–6]. These circuits overcome the CV 2 f barrier faced by the conventional CMOS logic and achieve extremely low power consumption. While this technique has been shown to improve power efficiency at low frequencies, much more work is needed to make them useful for a wide range of applications. For instance, other than the combinational logic gates, basic sequential circuits such as the flip-flops are also essential in the design of digital systems. Recently, energy recovery flip-flops based on the improved adiabatic pseudo-domino logic (IAPDL) structure are proposed [7]. * Corresponding author. Tel: ⫹ 65-790-5420; fax: ⫹ 65-791-2687. E-mail address: [email protected] (K.T. Lau).
However, the voltage drop across the precharge diodes causes unavoidable energy loss. Still, as a whole, the power dissipation is less than that of the conventional CMOS logic. In this paper, the proposed energy recovery SR and JK flip-flops are designed based on the efficient charge recovery logic (ECRL) architecture [4]. The ECRL does not require any precharge diodes. It was reported in Ref. [4] that an ECRL inverter chain shows 10–20 times power gain over a conventional inverter chain, while a 16-bit ECRL pipelined carry-lookahead adder (CLA) shows 4–6 times power gain compared to a conventional CLA. Simulation studies with the proposed ECRL-based flip-flops show significant improvement in terms of power consumption, compared to the conventional flip-flops as well as the IAPDL-based flipflops. Subsequently, the design of an adiabatic sequential circuit is illustrated using the example of a 4-bit binary counter. 2. Modified structure for the ECRL circuit An ECRL circuit consists of PMOS loads and NMOS pull-down transistors (Fig. 1). The PMOS transistors are cross-coupled and are used for precharge and evaluation. The NMOS transistors, however, are used to tie one of the differential output nodes to ground when the inputs are in the hold phase. Four-phase power clocks are used for different cascading stages. But for the purpose of discussion here, the power clocks are represented by trapezoidal waveforms.
0026-2692/00/$ - see front matter 䉷 2000 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(00)00006-9
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K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 365–370
Fig. 1. ECRL buffer/inverter and its power clock supply.
Although the ECRL is said to be an adiabatic logic style, a small fraction of non-adiabatic energy dissipation still exists. To illustrate this point, assume that IN ‘1’ at the beginning of the clock cycle. During the precharge/evaluate phase, OUTB is tied to ground as the power clock VCLK ramps from 0 V to VDD. Initially, no significant current flows, since both PMOS transistors (P1 and P2) are turned off. But when VCLK reaches 兩VTP 兩; where VTP is the threshold voltage of the PMOS transistor, P2 turns on and the load capacitance at the output node (OUT) will begin to charge up. This causes an initial, non-adiabatic dissipation of 2 ; where CL is the load capacitance approximately 1=2CL VTP
Fig. 2. (a) ECRL-based SR flip-flop; and (b) simulated waveforms at 100 MHz.
K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 365–370
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Fig. 3. (a) ECRL-based JK flip-flop (consisting of a basic cell and a buffer/inverter chain); and (b) simulated waveforms at 100 MHz.
associated with the output nodes. But subsequently, the charging of CL, up to VDD, will be adiabatic. During the recovery phase, as the voltage of the power clock VCLK approaches 兩VTP 兩; the PMOS transistor P2 gets turned off and the recovery path to the power clock is disconnected. The charge left on the load capacitance at the end of the recovery phase will either leak away slowly through the turned-off devices, or discharge through N2, if INB changes value (from ‘0’ to ‘1’) for the next logic evaluation. Thus, the non-adiabatic dissipation during the recovery phase will 2 : Although the either be less than or equal to 1=2CL VTP energy dissipation due to such non-adiabatic switching is inevitable, it can, however, be minimized. Instead of
connecting the PMOS body to the VDD power line, it is possible to connect it to the VCLK power clock line to achieve better recovery through the parasitic diodes formed between the source/drain and the body of the PMOS transistors, as shown in Fig. 1. By doing so, the output voltage can be further recovered to Vd (⬃0.5 V), the forward voltage drop across the diode, even if the PMOS transistor is already switched off when VCLK decreases below 兩VTP 兩 during the recovery phase. Such a connection improves the energy recovery process and gives a substantial improvement in terms of power dissipation. However, this method only applies during the recovery phase, as the diodes are reverse biased during the precharge/evaluate phase. Subsequently,
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K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 365–370
Fig. 4. (a) 4-bit ECRL binary counter; and (b) simulated waveforms at 100 MHz.
in this paper, the proposed circuit designs will be based on this modified ECRL structure.
discharged to 0 V. With N1 and N2 turned off, QB will be charged up to VDD by P1. 3.2. Proposed JK flip-flop
3. Circuit designs 3.1. Proposed SR flip-flop The proposed SR flip-flop is as shown in Fig. 2(a). Besides the PMOS loads (P1, P2) and the NMOS pulldown transistors (N1–N4), there are two other NMOS transistors (N5, N6) along the feedback paths of the outputs Q and QB, respectively. The gates of N5 and N6 are connected to VCLK. During the precharge/evaluate phase, if the output node Q swings from 0 V to VDD (representing a logic ‘1’), the gate capacitance of N2 will be charged to VDD ⫺ VTN and it will remain at this voltage to turn on N2. At the same time, N4 will be turned off since its gate is connected to the output node QB (which is at logic ‘0’) via N6. On the next clock cycle, if S ‘1’ and R ‘0’ (SET), or S R ‘0’ (HOLD), QB will still be held at 0 V by N1 and/or N2, while Q is being evaluated as a logic ‘1’. But on the contrary, if S ‘0’ and R ‘1’ (RESET), Q will be held at 0 V instead, and the gate capacitance of N2 will be
The proposed JK flip-flop is designed using a different approach as shown in Fig. 3(a). It consists of a basic JK flipflop cell and a buffer/inverter chain. The NMOS evaluation trees (N1–N4, N5–N8) in the basic cell represent the true and complementary logics of the JK flip-flop. The buffer/ inverter chain is used to delay the outputs, Q and QB, by three clock phases and the signals, Q3 and QB3, are fed back to the basic cell as the previous state’s outputs. As a whole, the JK flip-flop requires all of the four power clocks (VCLK1, VCLK2, VCLK3, VCLK4) to operate. 3.3. 4-Bit binary counter Using the proposed JK flip-flop, a 4-bit binary counter is designed as shown in Fig. 4(a). For simplicity, the complementary inputs and outputs are omitted from this schematic. This example is used to illustrate the design of a simple adiabatic sequential circuit using four JK flip-flops and three AND/NAND logic gates. In order to synchronize the signals between the stages, the
K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 365–370
Fig. 5. Power consumption against operating frequency: (a) SR flip-flops; and (b) JK flip-flops.
signals, Q2 and QB2, from the buffer/inverter chain of the JK flip-flop are being used as inputs to the AND/NAND logic gates, instead of the usual output signals, Q and QB. By doing so, no additional buffer is required to synchronize the signals.
4. Simulation results and discussion The circuits are designed based on a 0.8 mm n-well CMOS technology VTN 0:8 V; VTP ⫺0:9 V and are simulated using HSPICE. Four-phase sinusoidal power clocks with peak-to-peak voltage of 5 V are used to power up the ECRL circuits. Simulated waveforms of the SR flipflop, the JK flip-flop and the 4-bit ECRL binary counter at 100 MHz power clock frequency are as shown in Figs. 2(b), 3(b) and 4(b), respectively. To evaluate the performance of the proposed flip-flops, CMOS transmission gate-based
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(CMOS TG) flip-flops and IAPDL-based flip-flops are also designed and simulated. In the simulations, the CMOS TG-based flip-flops are powered by a 5 V DC supply, while the IAPDL-based flip-flops are powered by a power clock supply with a maximum voltage of 5 V and a 4.5 V DC supply. Fig. 5(a) and (b) show the power consumption of the various circuits. The power reduction achieved by the ECRL-based SR flip-flop ranges from 87.1% at 50 MHz to 55.5% at 250 MHz, compared to its CMOS counterpart. As for the ECRL-based JK flip-flop, the power reduction ranges from 89.8% at 50 MHz to 64.8% at 250 MHz. Besides that, the ECRL-based flip-flops also achieved lower power consumption, compared to the IAPDL-based flip-flops. The 4-bit binary counter designed using the proposed JK flip-flops is simulated at 100 MHz. The total power consumed from the 4-phase power clocks is 95.5 mW. Compared to the CMOS-based counter which has a power consumption of 443.4 mW, a significant 78.5% power savings is achieved. In the simulations, the power clock supply for the ECRLbased flip-flops is also being scaled down to 2.5 V peak-topeak at 100 MHz. Fig. 6(a) and (b) illustrate the power consumption of the flip-flops against the various supply voltages. It was verified that the ECRL-based SR and JK flip-flops are still able to function with a 2.5 V peak-to-peak power clock supply and their power consumption are reduced to 5.12 and 9.36 mW, respectively. Compared to the CMOS TG-based flip-flops operating at 2.5 V DC, the ECRL-based flip-flops are still able to achieve more than two times power gain. Although the gaps between the CMOS TG-based flip-flops and the ECRL-based flip-flops narrowed as the supply voltage decreases, it can be seen from Fig. 6(a) and (b) that the ECRL-based flip-flops consumed less power even when the supply voltage of the CMOS TG-based flip-flops is scaled down to 2.0 V, which is the lowest possible operating voltage for the CMOS circuits.
5. Conclusions The ECRL is a low-power adiabatic logic family. In this paper, adiabatic/energy recovery flip-flops based on the ECRL architecture are proposed. From the simulations, these flip-flops have shown significant improvement in terms of power consumption, compared to the CMOS TGbased flip-flops and the IAPDL-based flip-flops. They are able to operate at up to 250 MHz while maintaining a reasonably low power consumption. In addition, a 4-bit binary counter is being used to illustrate the design of an adiabatic sequential circuit using the proposed flip-flops and a power reduction of 78.5% is achieved at 100 MHz operating frequency. In summary, the ECRL-based flip-flops provide useful building blocks in the design of adiabatic/ energy recovery systems.
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Fig. 6. Power consumption against supply voltage at 100 MHz operating frequency: (a) SR flip-flops; and (b) JK flip-flops.
References [1] A. Kramer, J.S. Denker, S.C. Avery, A.G. Dickinson, T.R. Wik, Adiabatic computing with the 2N–2N2D logic family, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 1994, pp. 25–26. [2] A.G. Dickinson, J.S. Denker, Adiabatic dynamic logic, IEEE Journal of Solid-State Circuits 30 (3) (1995) 311–315. [3] K.T. Lau, F. Liu, Improved adiabatic pseudo-domino logic family, Electronics Letters 33 (25) (1997) 2113–2114. [4] Y. Moon, D.K. Jeong, An efficient charge recovery logic circuit, IEEE Journal of Solid-State Circuits 31 (4) (1996) 514–522.
[5] D. Maksimovic, V.G. Oklobdzija, Clocked CMOS adiabatic logic with single AC power supply, in: Proceedings of the 21st European SolidState Circuits Conference, ESSCIRC’95, 1995, pp. 370–373. [6] A. Kramer, J.S. Denker, B. Flower, J. Moroney, Second order adiabatic computation with 2N–2P and 2N–2N2P logic circuits, in: Proceedings of the International Symposium on Low Power Design, 1995, pp. 191– 196. [7] K.W. Ng, K.A. Ng, K.T. Lau, Energy-recovery flip-flop design using IAPDL structure, Microelectronics Journal 30 (9) (1999) 851–854.
ECRL-based low power flip-flop design K.W. Ng, K.T. Lau* Division of Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Block S1-B1 a-12, Singapore 639798, Singapore Accepted 17 December 1999
Abstract The efficient charge recovery logic (ECRL) is reported as a promising candidate for low-power applications. However, in the design of digital systems, essential building blocks such as the flip-flops cannot be neglected. In this paper, adiabatic switching or energy recovery technique is used in the design of low-power flip-flops. In particular, SR and JK flip-flop designs based on the ECRL architecture are proposed. From the HSPICE simulation results, these adiabatic flip-flops have shown significant improvement in terms of power consumption over their CMOS counterparts. In addition, the design of an adiabatic sequential circuit is illustrated using the example of a 4-bit binary counter. 䉷 2000 Elsevier Science Ltd. All rights reserved. Keywords: Efficient charge recovery logic; Adiabatic circuits; SR flip-flop; JK flip-flop
1. Introduction In the recent years, there has been a growing interest in low power VLSI design. Many low power design techniques have emerged from universities, research laboratories and the industry. One of the promising techniques in the design of low power digital circuits is to apply the concept of adiabatic switching or energy recovery. This approach is based on the second law of thermodynamics, which points the way of recycling switching energy. When adiabatic switching is used, energy that would otherwise be dissipated as heat is being recovered in order to reduce the power dissipation. Several adiabatic logic architectures have been reported. Most of these adiabatic logic families use either diodes for precharge [1–3], or a pair of cross-coupled PMOS transistors for both precharge and evaluation [4–6]. These circuits overcome the CV 2 f barrier faced by the conventional CMOS logic and achieve extremely low power consumption. While this technique has been shown to improve power efficiency at low frequencies, much more work is needed to make them useful for a wide range of applications. For instance, other than the combinational logic gates, basic sequential circuits such as the flip-flops are also essential in the design of digital systems. Recently, energy recovery flip-flops based on the improved adiabatic pseudo-domino logic (IAPDL) structure are proposed [7]. * Corresponding author. Tel: ⫹ 65-790-5420; fax: ⫹ 65-791-2687. E-mail address: [email protected] (K.T. Lau).
However, the voltage drop across the precharge diodes causes unavoidable energy loss. Still, as a whole, the power dissipation is less than that of the conventional CMOS logic. In this paper, the proposed energy recovery SR and JK flip-flops are designed based on the efficient charge recovery logic (ECRL) architecture [4]. The ECRL does not require any precharge diodes. It was reported in Ref. [4] that an ECRL inverter chain shows 10–20 times power gain over a conventional inverter chain, while a 16-bit ECRL pipelined carry-lookahead adder (CLA) shows 4–6 times power gain compared to a conventional CLA. Simulation studies with the proposed ECRL-based flip-flops show significant improvement in terms of power consumption, compared to the conventional flip-flops as well as the IAPDL-based flipflops. Subsequently, the design of an adiabatic sequential circuit is illustrated using the example of a 4-bit binary counter. 2. Modified structure for the ECRL circuit An ECRL circuit consists of PMOS loads and NMOS pull-down transistors (Fig. 1). The PMOS transistors are cross-coupled and are used for precharge and evaluation. The NMOS transistors, however, are used to tie one of the differential output nodes to ground when the inputs are in the hold phase. Four-phase power clocks are used for different cascading stages. But for the purpose of discussion here, the power clocks are represented by trapezoidal waveforms.
0026-2692/00/$ - see front matter 䉷 2000 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(00)00006-9
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K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 365–370
Fig. 1. ECRL buffer/inverter and its power clock supply.
Although the ECRL is said to be an adiabatic logic style, a small fraction of non-adiabatic energy dissipation still exists. To illustrate this point, assume that IN ‘1’ at the beginning of the clock cycle. During the precharge/evaluate phase, OUTB is tied to ground as the power clock VCLK ramps from 0 V to VDD. Initially, no significant current flows, since both PMOS transistors (P1 and P2) are turned off. But when VCLK reaches 兩VTP 兩; where VTP is the threshold voltage of the PMOS transistor, P2 turns on and the load capacitance at the output node (OUT) will begin to charge up. This causes an initial, non-adiabatic dissipation of 2 ; where CL is the load capacitance approximately 1=2CL VTP
Fig. 2. (a) ECRL-based SR flip-flop; and (b) simulated waveforms at 100 MHz.
K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 365–370
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Fig. 3. (a) ECRL-based JK flip-flop (consisting of a basic cell and a buffer/inverter chain); and (b) simulated waveforms at 100 MHz.
associated with the output nodes. But subsequently, the charging of CL, up to VDD, will be adiabatic. During the recovery phase, as the voltage of the power clock VCLK approaches 兩VTP 兩; the PMOS transistor P2 gets turned off and the recovery path to the power clock is disconnected. The charge left on the load capacitance at the end of the recovery phase will either leak away slowly through the turned-off devices, or discharge through N2, if INB changes value (from ‘0’ to ‘1’) for the next logic evaluation. Thus, the non-adiabatic dissipation during the recovery phase will 2 : Although the either be less than or equal to 1=2CL VTP energy dissipation due to such non-adiabatic switching is inevitable, it can, however, be minimized. Instead of
connecting the PMOS body to the VDD power line, it is possible to connect it to the VCLK power clock line to achieve better recovery through the parasitic diodes formed between the source/drain and the body of the PMOS transistors, as shown in Fig. 1. By doing so, the output voltage can be further recovered to Vd (⬃0.5 V), the forward voltage drop across the diode, even if the PMOS transistor is already switched off when VCLK decreases below 兩VTP 兩 during the recovery phase. Such a connection improves the energy recovery process and gives a substantial improvement in terms of power dissipation. However, this method only applies during the recovery phase, as the diodes are reverse biased during the precharge/evaluate phase. Subsequently,
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Fig. 4. (a) 4-bit ECRL binary counter; and (b) simulated waveforms at 100 MHz.
in this paper, the proposed circuit designs will be based on this modified ECRL structure.
discharged to 0 V. With N1 and N2 turned off, QB will be charged up to VDD by P1. 3.2. Proposed JK flip-flop
3. Circuit designs 3.1. Proposed SR flip-flop The proposed SR flip-flop is as shown in Fig. 2(a). Besides the PMOS loads (P1, P2) and the NMOS pulldown transistors (N1–N4), there are two other NMOS transistors (N5, N6) along the feedback paths of the outputs Q and QB, respectively. The gates of N5 and N6 are connected to VCLK. During the precharge/evaluate phase, if the output node Q swings from 0 V to VDD (representing a logic ‘1’), the gate capacitance of N2 will be charged to VDD ⫺ VTN and it will remain at this voltage to turn on N2. At the same time, N4 will be turned off since its gate is connected to the output node QB (which is at logic ‘0’) via N6. On the next clock cycle, if S ‘1’ and R ‘0’ (SET), or S R ‘0’ (HOLD), QB will still be held at 0 V by N1 and/or N2, while Q is being evaluated as a logic ‘1’. But on the contrary, if S ‘0’ and R ‘1’ (RESET), Q will be held at 0 V instead, and the gate capacitance of N2 will be
The proposed JK flip-flop is designed using a different approach as shown in Fig. 3(a). It consists of a basic JK flipflop cell and a buffer/inverter chain. The NMOS evaluation trees (N1–N4, N5–N8) in the basic cell represent the true and complementary logics of the JK flip-flop. The buffer/ inverter chain is used to delay the outputs, Q and QB, by three clock phases and the signals, Q3 and QB3, are fed back to the basic cell as the previous state’s outputs. As a whole, the JK flip-flop requires all of the four power clocks (VCLK1, VCLK2, VCLK3, VCLK4) to operate. 3.3. 4-Bit binary counter Using the proposed JK flip-flop, a 4-bit binary counter is designed as shown in Fig. 4(a). For simplicity, the complementary inputs and outputs are omitted from this schematic. This example is used to illustrate the design of a simple adiabatic sequential circuit using four JK flip-flops and three AND/NAND logic gates. In order to synchronize the signals between the stages, the
K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 365–370
Fig. 5. Power consumption against operating frequency: (a) SR flip-flops; and (b) JK flip-flops.
signals, Q2 and QB2, from the buffer/inverter chain of the JK flip-flop are being used as inputs to the AND/NAND logic gates, instead of the usual output signals, Q and QB. By doing so, no additional buffer is required to synchronize the signals.
4. Simulation results and discussion The circuits are designed based on a 0.8 mm n-well CMOS technology VTN 0:8 V; VTP ⫺0:9 V and are simulated using HSPICE. Four-phase sinusoidal power clocks with peak-to-peak voltage of 5 V are used to power up the ECRL circuits. Simulated waveforms of the SR flipflop, the JK flip-flop and the 4-bit ECRL binary counter at 100 MHz power clock frequency are as shown in Figs. 2(b), 3(b) and 4(b), respectively. To evaluate the performance of the proposed flip-flops, CMOS transmission gate-based
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(CMOS TG) flip-flops and IAPDL-based flip-flops are also designed and simulated. In the simulations, the CMOS TG-based flip-flops are powered by a 5 V DC supply, while the IAPDL-based flip-flops are powered by a power clock supply with a maximum voltage of 5 V and a 4.5 V DC supply. Fig. 5(a) and (b) show the power consumption of the various circuits. The power reduction achieved by the ECRL-based SR flip-flop ranges from 87.1% at 50 MHz to 55.5% at 250 MHz, compared to its CMOS counterpart. As for the ECRL-based JK flip-flop, the power reduction ranges from 89.8% at 50 MHz to 64.8% at 250 MHz. Besides that, the ECRL-based flip-flops also achieved lower power consumption, compared to the IAPDL-based flip-flops. The 4-bit binary counter designed using the proposed JK flip-flops is simulated at 100 MHz. The total power consumed from the 4-phase power clocks is 95.5 mW. Compared to the CMOS-based counter which has a power consumption of 443.4 mW, a significant 78.5% power savings is achieved. In the simulations, the power clock supply for the ECRLbased flip-flops is also being scaled down to 2.5 V peak-topeak at 100 MHz. Fig. 6(a) and (b) illustrate the power consumption of the flip-flops against the various supply voltages. It was verified that the ECRL-based SR and JK flip-flops are still able to function with a 2.5 V peak-to-peak power clock supply and their power consumption are reduced to 5.12 and 9.36 mW, respectively. Compared to the CMOS TG-based flip-flops operating at 2.5 V DC, the ECRL-based flip-flops are still able to achieve more than two times power gain. Although the gaps between the CMOS TG-based flip-flops and the ECRL-based flip-flops narrowed as the supply voltage decreases, it can be seen from Fig. 6(a) and (b) that the ECRL-based flip-flops consumed less power even when the supply voltage of the CMOS TG-based flip-flops is scaled down to 2.0 V, which is the lowest possible operating voltage for the CMOS circuits.
5. Conclusions The ECRL is a low-power adiabatic logic family. In this paper, adiabatic/energy recovery flip-flops based on the ECRL architecture are proposed. From the simulations, these flip-flops have shown significant improvement in terms of power consumption, compared to the CMOS TGbased flip-flops and the IAPDL-based flip-flops. They are able to operate at up to 250 MHz while maintaining a reasonably low power consumption. In addition, a 4-bit binary counter is being used to illustrate the design of an adiabatic sequential circuit using the proposed flip-flops and a power reduction of 78.5% is achieved at 100 MHz operating frequency. In summary, the ECRL-based flip-flops provide useful building blocks in the design of adiabatic/ energy recovery systems.
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Fig. 6. Power consumption against supply voltage at 100 MHz operating frequency: (a) SR flip-flops; and (b) JK flip-flops.
References [1] A. Kramer, J.S. Denker, S.C. Avery, A.G. Dickinson, T.R. Wik, Adiabatic computing with the 2N–2N2D logic family, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 1994, pp. 25–26. [2] A.G. Dickinson, J.S. Denker, Adiabatic dynamic logic, IEEE Journal of Solid-State Circuits 30 (3) (1995) 311–315. [3] K.T. Lau, F. Liu, Improved adiabatic pseudo-domino logic family, Electronics Letters 33 (25) (1997) 2113–2114. [4] Y. Moon, D.K. Jeong, An efficient charge recovery logic circuit, IEEE Journal of Solid-State Circuits 31 (4) (1996) 514–522.
[5] D. Maksimovic, V.G. Oklobdzija, Clocked CMOS adiabatic logic with single AC power supply, in: Proceedings of the 21st European SolidState Circuits Conference, ESSCIRC’95, 1995, pp. 370–373. [6] A. Kramer, J.S. Denker, B. Flower, J. Moroney, Second order adiabatic computation with 2N–2P and 2N–2N2P logic circuits, in: Proceedings of the International Symposium on Low Power Design, 1995, pp. 191– 196. [7] K.W. Ng, K.A. Ng, K.T. Lau, Energy-recovery flip-flop design using IAPDL structure, Microelectronics Journal 30 (9) (1999) 851–854.