- Email: [email protected]
Low power flip-flop design based on PAL-2N structure
MEJ 669
Microelectronics Journal Microelectronics Journal 31 (2000) 113–116 www.elsevier.com/locate/mejo
Low power flip-flop design based on PAL-2N structure K.W. Ng, K.T. Lau* Division of Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798, Singapore Accepted 3 May 1999
Abstract Adiabatic or energy-recovery logic has gained much attention recently in the development of low-power digital logic. The previously proposed adiabatic logic families have focused mainly on combination logic. In this paper, we extend this principle to the design of flip-flops. SR and JK flip-flop designs based on the pass-transistor adiabatic logic with NMOS pull-down configuration (PAL-2N) are presented. Based on the simulation results, these adiabatic flip-flops outperform their CMOS counterparts in terms of power consumption. The operation of a 4-bit binary counter developed using the proposed JK flip-flop has also been simulated and verified. q 1999 Elsevier Science Ltd. All rights reserved. Keywords: Flip-flop; Pass-transistor adiabatic logic; Energy recovery
1. Introduction Pass-transistor adiabatic logic (PAL) [1] has a simple circuit structure and requires only one sinusoidal powerclock supply. It has been shown to outperform the 2N2N2D logic family [2] and the 2N-2N2P logic family [3,4], in terms of energy consumption. However, its performance is limited by its above-threshold logic ‘0’ due to its ‘tri-state’ output nodes. PAL with NMOS pull-down configuration (PAL-2N) [5] overcomes this problem by introducing an additional pair of NMOS pull-down transistors, thus providing a well-defined output logic ‘0’, and yet achieving an equivalent power consumption. In this paper, we extend the energy-recovery principle of PAL-2N logic family to the design of SR and JK flip-flops. Using the CMOS transmission gate-based (CMOS TG) SR flip-flop and JK master-slave flip-flop as comparison, PAL-2N flipflops show significant improvement in terms of power consumption. In addition, a 4-bit binary counter is designed using the JK flip-flops proposed in this paper. 2. Circuit description 2.1. Proposed SR flip-flip The circuit structure for the SR flip-flop is shown in Fig. * Corresponding author. Tel.: 1 65-790-5420; fax: 1 65-791-2687. E-mail address: [email protected] (K.T. Lau)
1(a). Its supply, VCLK, is a sinusoidal signal with a peak-topeak voltage, VDD, and dc offset, 12 V DD . The true or uncomplemented output evaluation tree consists of N3 and N4, with N7 placed along the feedback path of Q, while the complementary output evaluation tree consists of N5 and N6, with N8 placed along the feedback path of QB. The control signal for the feedback pass-transistors N7 and N8 is the power-clock supply, i.e. VCLK. During the evaluation phase, when VCLK increases beyond VTn, N7 and N8 will be turned on to charge up (or discharge) the gate capacitance of N4 and N6, depending on the logic of Q and QB. Consider the case when Q ‘1’ and QB ‘0’. The gate capacitance of N4 will be charged up to a voltage of VDD 2 VTn . When VCLK decreases during the recovery phase, the gate capacitance of N4 will only discharge partially through N7, while the remaining energy is dynamically stored at the gate after N7 is turned off. From hspice simulation, we find that the gate voltage is approximately 1 V for VDD 5 V. This value is sufficient to turn on N4 during the next evaluation phase, though its value may fluctuate slightly due to capacitive coupling resulting from VCLK. The same analysis applies for N6 when Q ‘0’ and QB ‘1’. Hence, the true output evaluation tree will be conducting when S ‘1’ and/or Q previous state ‘1’, while the complementary output evaluation tree will be conducting when R ‘1’ and/or QB previous state ‘1’, with the condition that S and R cannot be ‘1’ at the same time. However, there is a particular situation when S ‘1’ and QB previous state ‘1’ (or when R ‘1’ and
0026-2692/00/$ - see front matter q 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(99)00097-X
114
K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 113–116
Fig. 1. (a) PAL-2N SR flip-flop and its clock waveform; (b) simulated waveforms at 100 MHz.
Fig. 2. (a) PAL-2N JK flip-flop (consisting of a basic cell and a buffer/inverter cell) and its clock waveform; (b) simulated waveforms at 100 MHz.
K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 113–116
Fig. 3. Power consumption at different operating frequencies.
Q previous state ‘1’). In this case, during evaluation phase, both N3 and N6 (or N4 and N5) are turned on concurrently, but as N6 is weakly turned on compared to N3, the output node Q will be charged faster, and subsequently P1 will start conducting. The increasing voltage of Q will turn on N2 but prevent P2 from turning on. Thus, QB remains at 0 V. The simulated waveforms for the SR flip-flop are presented in Fig. 1(b). 2.2. Proposed JK flip-flop The design of JK flip-flop is shown in Fig. 2(a). Unlike the SR flip-flop, which uses feedback pass-transistors, the JK flip-flop has to be designed using the master-slave configuration. From its logic expression, Qn11 J·QBn 1 KB·Qn , where Qn represents the present state output and Qn11 represents the next state output, it is
115
noted that when J ‘1’ K, Qn11 QBn or QBn11 Qn . This is critical because in the case of conventional CMOS JK flip-flop, such conditions will result in oscillations when the clock is enabled. However, in our case, it implies that if the JK flip-flop is to be designed in the same manner as the SR flip-flop, then the charging of output node Q during the evaluation phase will cause the complementary output evaluation tree to conduct as well. This, in turn, will result in the charging of the output node QB. Hence, excessive power will be lost due to short circuit current flowing between VCLK and the ground. Therefore, the master–slave configuration is needed to eliminate this problem. Besides the basic JK flip-flop cell, an additional PAL-2N buffer/inverter cell is required to store and delay the outputs, Q and QB, of the basic cell. The outputs of the buffer cell, Q1 and QB1, are then used as inputs to the basic cell. These two cells are driven by two sinusoidal power-clock supplies of 1808 phase difference, VCLK1 and VCLK2. Fig. 2(b) illustrates the simulated waveforms of the JK flip-flop.
3. Simulation results and discussion The two flip-flop designs are simulated using hspice, which is based on 0.8 mm n-well CMOS process parameters. The sinusoidal power-clocks are 5 V peak-topeak, with 2.5 V dc offset. A nodal capacitance of 0.02 pF is placed at every output. The power consumed by the flipflops at operating frequencies ranging from 50 to 250 MHz are plotted as shown in Fig. 3. It shows that the proposed flip-flops outperform their CMOS counterparts significantly. At 100 MHz operating frequency, the power consumed by
Fig. 4. (a) PAL-2N 4-bit binary counter; (b) simulated waveforms at 100 MHz.
116
K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 113–116
the proposed SR and JK flip-flops are 8.896 and 26.31 mW, respectively. The JK flip-flop consumes relatively more power than the SR flip-flop due to its additional buffer/ inverter cell. Also, the input signals to the buffer/inverter cell (Q and QB), and the feedback signals to the basic cell (Q1 and QB1) are no longer square waves, but are sine pulses. As such, the voltages at these output nodes cannot be fully recovered to 0 V during the recovery phase, as previously explained in Ref. [5]. This also accounts for the slight kink in the output waveforms. However, when compared to CMOS transmission gate-based SR flip-flop and JK master–slave flip-flop at 100 MHz (whose power consumptions are 49.55 and 97.2 mW, respectively), the proposed SR flip-flop consumes 82% less power while the proposed JK flip-flop consumes 72.9% less power. hspice simulations also show that the proposed SR and JK flip-flops can operate up to 300 and 250 MHz clock frequency, respectively. A 4-bit binary counter as shown in Fig. 4(a) is designed using the proposed JK flip-flops and PAL-2N 3-input and/ nand gates. (For clarity, the complementary inputs and outputs are omitted from this schematic.) This counter is simulated at 100 MHz and the result shows that its power consumption is 276.9 mW, while that of its CMOS counterpart is 443.4 mW. Hence, it achieves a power reduction of 37.6%.
4. Conclusion In this paper, energy-recovery flip-flops based on PAL2N circuit structure are presented. These flip-flops have shown significant improvement in terms of power consumption. The operation of a 4-bit binary counter has also been simulated and verified. Flip-flops are the fundamental building blocks in sequential logic designs. Extending the principle of energy-recovery to the design of flip-flops will subsequently be useful in the design of energy-recovery systems. References [1] V.G. Oklobdzija, D. Maksimovic, F.C. Lin, Pass-transistor adiabatic logic using single power-clock supply, IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing 44 (10) (1997) 842–846. [2] A. Kramer, J.S. Denker, S.C. Avery, A.G. Dickinson, T. Wik, Adiabatic computing with the 2N-2N2D logic family, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, (1994) 25–26. [3] J.S. Denker, A review of adiabatic computing, IEEE Symposium on Low Power Electronics (1994) 94–97. [4] A. Kramer, J.S. Denker, B. Flower, J. Moroney, Second order adiabatic computation with 2N-2P and 2N-2N2P logic circuits, International Symposium on Low Power Design (1995) 191–196. [5] F. Liu, K.T. Lau, Pass-transistor adiabatic logic with NMOS pull-down configuration, Electronics Letters 34 (8) (1998) 739–741.
Microelectronics Journal Microelectronics Journal 31 (2000) 113–116 www.elsevier.com/locate/mejo
Low power flip-flop design based on PAL-2N structure K.W. Ng, K.T. Lau* Division of Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798, Singapore Accepted 3 May 1999
Abstract Adiabatic or energy-recovery logic has gained much attention recently in the development of low-power digital logic. The previously proposed adiabatic logic families have focused mainly on combination logic. In this paper, we extend this principle to the design of flip-flops. SR and JK flip-flop designs based on the pass-transistor adiabatic logic with NMOS pull-down configuration (PAL-2N) are presented. Based on the simulation results, these adiabatic flip-flops outperform their CMOS counterparts in terms of power consumption. The operation of a 4-bit binary counter developed using the proposed JK flip-flop has also been simulated and verified. q 1999 Elsevier Science Ltd. All rights reserved. Keywords: Flip-flop; Pass-transistor adiabatic logic; Energy recovery
1. Introduction Pass-transistor adiabatic logic (PAL) [1] has a simple circuit structure and requires only one sinusoidal powerclock supply. It has been shown to outperform the 2N2N2D logic family [2] and the 2N-2N2P logic family [3,4], in terms of energy consumption. However, its performance is limited by its above-threshold logic ‘0’ due to its ‘tri-state’ output nodes. PAL with NMOS pull-down configuration (PAL-2N) [5] overcomes this problem by introducing an additional pair of NMOS pull-down transistors, thus providing a well-defined output logic ‘0’, and yet achieving an equivalent power consumption. In this paper, we extend the energy-recovery principle of PAL-2N logic family to the design of SR and JK flip-flops. Using the CMOS transmission gate-based (CMOS TG) SR flip-flop and JK master-slave flip-flop as comparison, PAL-2N flipflops show significant improvement in terms of power consumption. In addition, a 4-bit binary counter is designed using the JK flip-flops proposed in this paper. 2. Circuit description 2.1. Proposed SR flip-flip The circuit structure for the SR flip-flop is shown in Fig. * Corresponding author. Tel.: 1 65-790-5420; fax: 1 65-791-2687. E-mail address: [email protected] (K.T. Lau)
1(a). Its supply, VCLK, is a sinusoidal signal with a peak-topeak voltage, VDD, and dc offset, 12 V DD . The true or uncomplemented output evaluation tree consists of N3 and N4, with N7 placed along the feedback path of Q, while the complementary output evaluation tree consists of N5 and N6, with N8 placed along the feedback path of QB. The control signal for the feedback pass-transistors N7 and N8 is the power-clock supply, i.e. VCLK. During the evaluation phase, when VCLK increases beyond VTn, N7 and N8 will be turned on to charge up (or discharge) the gate capacitance of N4 and N6, depending on the logic of Q and QB. Consider the case when Q ‘1’ and QB ‘0’. The gate capacitance of N4 will be charged up to a voltage of VDD 2 VTn . When VCLK decreases during the recovery phase, the gate capacitance of N4 will only discharge partially through N7, while the remaining energy is dynamically stored at the gate after N7 is turned off. From hspice simulation, we find that the gate voltage is approximately 1 V for VDD 5 V. This value is sufficient to turn on N4 during the next evaluation phase, though its value may fluctuate slightly due to capacitive coupling resulting from VCLK. The same analysis applies for N6 when Q ‘0’ and QB ‘1’. Hence, the true output evaluation tree will be conducting when S ‘1’ and/or Q previous state ‘1’, while the complementary output evaluation tree will be conducting when R ‘1’ and/or QB previous state ‘1’, with the condition that S and R cannot be ‘1’ at the same time. However, there is a particular situation when S ‘1’ and QB previous state ‘1’ (or when R ‘1’ and
0026-2692/00/$ - see front matter q 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(99)00097-X
114
K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 113–116
Fig. 1. (a) PAL-2N SR flip-flop and its clock waveform; (b) simulated waveforms at 100 MHz.
Fig. 2. (a) PAL-2N JK flip-flop (consisting of a basic cell and a buffer/inverter cell) and its clock waveform; (b) simulated waveforms at 100 MHz.
K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 113–116
Fig. 3. Power consumption at different operating frequencies.
Q previous state ‘1’). In this case, during evaluation phase, both N3 and N6 (or N4 and N5) are turned on concurrently, but as N6 is weakly turned on compared to N3, the output node Q will be charged faster, and subsequently P1 will start conducting. The increasing voltage of Q will turn on N2 but prevent P2 from turning on. Thus, QB remains at 0 V. The simulated waveforms for the SR flip-flop are presented in Fig. 1(b). 2.2. Proposed JK flip-flop The design of JK flip-flop is shown in Fig. 2(a). Unlike the SR flip-flop, which uses feedback pass-transistors, the JK flip-flop has to be designed using the master-slave configuration. From its logic expression, Qn11 J·QBn 1 KB·Qn , where Qn represents the present state output and Qn11 represents the next state output, it is
115
noted that when J ‘1’ K, Qn11 QBn or QBn11 Qn . This is critical because in the case of conventional CMOS JK flip-flop, such conditions will result in oscillations when the clock is enabled. However, in our case, it implies that if the JK flip-flop is to be designed in the same manner as the SR flip-flop, then the charging of output node Q during the evaluation phase will cause the complementary output evaluation tree to conduct as well. This, in turn, will result in the charging of the output node QB. Hence, excessive power will be lost due to short circuit current flowing between VCLK and the ground. Therefore, the master–slave configuration is needed to eliminate this problem. Besides the basic JK flip-flop cell, an additional PAL-2N buffer/inverter cell is required to store and delay the outputs, Q and QB, of the basic cell. The outputs of the buffer cell, Q1 and QB1, are then used as inputs to the basic cell. These two cells are driven by two sinusoidal power-clock supplies of 1808 phase difference, VCLK1 and VCLK2. Fig. 2(b) illustrates the simulated waveforms of the JK flip-flop.
3. Simulation results and discussion The two flip-flop designs are simulated using hspice, which is based on 0.8 mm n-well CMOS process parameters. The sinusoidal power-clocks are 5 V peak-topeak, with 2.5 V dc offset. A nodal capacitance of 0.02 pF is placed at every output. The power consumed by the flipflops at operating frequencies ranging from 50 to 250 MHz are plotted as shown in Fig. 3. It shows that the proposed flip-flops outperform their CMOS counterparts significantly. At 100 MHz operating frequency, the power consumed by
Fig. 4. (a) PAL-2N 4-bit binary counter; (b) simulated waveforms at 100 MHz.
116
K.W. Ng, K.T. Lau / Microelectronics Journal 31 (2000) 113–116
the proposed SR and JK flip-flops are 8.896 and 26.31 mW, respectively. The JK flip-flop consumes relatively more power than the SR flip-flop due to its additional buffer/ inverter cell. Also, the input signals to the buffer/inverter cell (Q and QB), and the feedback signals to the basic cell (Q1 and QB1) are no longer square waves, but are sine pulses. As such, the voltages at these output nodes cannot be fully recovered to 0 V during the recovery phase, as previously explained in Ref. [5]. This also accounts for the slight kink in the output waveforms. However, when compared to CMOS transmission gate-based SR flip-flop and JK master–slave flip-flop at 100 MHz (whose power consumptions are 49.55 and 97.2 mW, respectively), the proposed SR flip-flop consumes 82% less power while the proposed JK flip-flop consumes 72.9% less power. hspice simulations also show that the proposed SR and JK flip-flops can operate up to 300 and 250 MHz clock frequency, respectively. A 4-bit binary counter as shown in Fig. 4(a) is designed using the proposed JK flip-flops and PAL-2N 3-input and/ nand gates. (For clarity, the complementary inputs and outputs are omitted from this schematic.) This counter is simulated at 100 MHz and the result shows that its power consumption is 276.9 mW, while that of its CMOS counterpart is 443.4 mW. Hence, it achieves a power reduction of 37.6%.
4. Conclusion In this paper, energy-recovery flip-flops based on PAL2N circuit structure are presented. These flip-flops have shown significant improvement in terms of power consumption. The operation of a 4-bit binary counter has also been simulated and verified. Flip-flops are the fundamental building blocks in sequential logic designs. Extending the principle of energy-recovery to the design of flip-flops will subsequently be useful in the design of energy-recovery systems. References [1] V.G. Oklobdzija, D. Maksimovic, F.C. Lin, Pass-transistor adiabatic logic using single power-clock supply, IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing 44 (10) (1997) 842–846. [2] A. Kramer, J.S. Denker, S.C. Avery, A.G. Dickinson, T. Wik, Adiabatic computing with the 2N-2N2D logic family, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, (1994) 25–26. [3] J.S. Denker, A review of adiabatic computing, IEEE Symposium on Low Power Electronics (1994) 94–97. [4] A. Kramer, J.S. Denker, B. Flower, J. Moroney, Second order adiabatic computation with 2N-2P and 2N-2N2P logic circuits, International Symposium on Low Power Design (1995) 191–196. [5] F. Liu, K.T. Lau, Pass-transistor adiabatic logic with NMOS pull-down configuration, Electronics Letters 34 (8) (1998) 739–741.