Edge effects on polyoxide capacitors

Microelectronics Journal, 24 (1993) 427-433

Edge effects on polyoxide capacitors L. Haspeslagh, G. Vanhorebeek and L. Deferm IMEC, Kapddreef 75, B-300I Leuven, Belgium

A comparison between overlapping and non-overlapping polyoxidecapacitorsshowsthat the overlappingedge results in hightunnellingcurrentsat moderateelectricfields.Calculations of the localelectricfield distributionshowthat the shape of the polysih'con top comer is very important. Sharp top comers result in high electric field peaks. Shaping of this corner, by slopingand/or rounding,has been shownto reducethe peak to an acceptableheight.Thispaperpresentsa practicalimplementation of this shaping, using an isotropic NF3 plasma etch and resulting in an appreciablecurrent reduction. Next to this top comer, some electricfield calculationsin the bottom region of the edge have also been performed,showingthe importanceof the polysiliconshape.

process optimizations for interpoly dielectrics on the edge tunnelling current is investigated. In order to investigate the cause of this increase and to fred a solution for this phenomenon, the electric field distribution at these edges is calculated for different shapes of the top comer of the polysilicon layer. It will be shown that a slight sloping of this comer, together with a rounding of the sharp edges, results in a structure which strongly reduces the local electric field and hence the tunnelling current at the edges. Finally, some results obtained on capacitors with rounded edges will be shown.

1. Introduction I nterpoly capacitors are widely used in non-volatile memory and analogue processes. Two types of dielectric are generally available for fabrication of these capacitors: polyoxide and oxide-nitride-oxide multilayer (ONO). O N O is known to have a better performance, but the use of polyoxide results in a simpler process due to the simultaneous processing of a gate oxide and an interpoly dielectric. However, the suitability of polyoxide as interpoly dielectric for submicron non-volatile memory processes is limited. One of the major factors of this limitation is the increase oftunneUing current which is mainly observed at the edges of patterned polysilicon layers [1]. In this work, the influence of

2. Process optimizations reducing asperity enhancement It is generally accepted that asperities in polysilicon layers have a strong influence on the tunnelling

current of inte poly oxides [2]. Daring thermal oxidation of a polysilicon layer an asperity growth mechanism is occurring. This mechanism is influenced by the oxidation temperature; there is a reduction of stress in the oxide layer at higher oxidation temperatures. This is illustrated in Fig. 1, which shows tunnelling current curves for 30 nm polyoxide capacitors grown at different temperatures, where the top polysilicon layer does not overlap the bottom layer so that the influence of the edge is not present. These current curves were obtained by applying a

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427

L Haspeslagh et al./Edge effects on po/yoxide capacitors

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Fig. 1. Influence of oxidation temperature on tunnelling current density measured on non-overhpping polyoxide capacitors,

Fig. 2. Influence of oxidation temperature on tunnelling current density measured on overhpping polyoxide capacitors.

positive voltage to the top electrode so that electrons tunnelled through the barrier formed by the top of the bottom polysilicon layer and the polyoxide. When the oxidation temperature is increased, the polysilicon surface roughness decreases, resulting in a lower current for the same voltage [3]. However, when the second poly is overlapping the bottom poly structure, an increase in the oxidation temperature no longer results in a strong current reduction, as shown in Fig. 2. In this situation the influence of the asperity growth mechanism is masked by edge effects. These effects cause an increase in the tunnelling current by 2-4 orders of magnitude. In addition, the dependence of the tunnelling current on the oxidation temperature is found to be very low.

current flowing through the oxide results in trapped charge which influences the field distribution [4]. Most of this charge is trapped in the regions where the largest current is flowing, thus reducing the existing field enhancement. Calagations of unstressed capacitors are acceptable because the aim of this study is to obtain a polyoxide layer through which electrical conduction is avoided.

3. Electric field

calculations

In order to explain the poly edge effects, and to fred an appropriate solution resulting in an appreciable reduction of tunnelling current, the local electric field distribution has been calculated. This has been done by solving the two-dimensional Poisson equation with the polysilicon-polyoxide interfaces as boundary conditions. These calculations show the situation of unstressed polyoxide capacitors, since

428

A first result of such a field calculation is shown in Fig. 3 for a capacitor with a sharp top comer. This type of comer (or even a sharper one) is obtained when no special precautions are taken [5], and results in a very high and narrow electric field peak. Since the tunnelling current, to a first approximation, exponentially depends on the electric field at the injecting interface [6], a large tunnelling current density will flow at these edges, which explains the strong increase in tunnelling current for overlapping structures. To obtain a polyoxide layer with a better performance, it is clear that the shape of this comer has to be changed. A fast possible change of shape is a rounding of the comer. By changing the radius of curvature, the peak electric field is found to be

Microelectronics Journal, VoL 24

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Radius of cur~sture of top corner [nm] Fig. 5. Normalizedheight of electric field peak vs radius of curvature of the top comer for different oxide thicknesses.

The dependence of the height of the field peak on the radius is shown in Fig. 5 for different oxide thicknesses. Top comer radii larger than 10 nm result in an electric field reduction by more than a factor of 2. In fact it is found that the determining factor for electric field enhancement is the ratio between the radius and the oxide thickness, since all curves coincide when this parameter is used instead of the radius itself.

split of the electric field peak into two distinct peaks with a lower amplitude, as shown in Fig. 6. Increasing the length of the sloped region decreases the amplitude of the peaks until the tails of the peaks no longer overlap. A further lengthening of the sloped region does not result in a decrease of the field peaks. The eventual height of the electric field peaks is almost half of the original peak value (Fig. 7).

A second possible change for the corner shape is a sloping of the polysilicon comer. This results in a

Splitting into two identical field peaks happens only ffthe angle of the slope is 45 °. For other angles, the

Fig. 4. Electric field dim-ibution in the neighbourhoodof a rounded top comer.

Fig. 6. Electric field distribution in the neighbourhood of a sloped top comer.

429

L Haspeslagh et al./Edge effects on polyoxide capacitors

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ratio of the field peaks will be equal to the ratio of the angles. Also, a straight line is required between both angles. A convex profile will result in a widening and lowering of the field peaks, comparable to a rounding of the edge. A concave profile will have the opposite result: higher and narrower peaks. A combination of sloping and rounding of the polysilicon comer is shown in Fig. 8. This is seen to be a very effective way of reducing the edge effects. A first reduction is obtained by splitting the field peak; the rounding of both comers reduces the

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Fig. 9. Normalized height of electric field peak vs radius of curvature on a doped polysilicon corner. The depth of the sloping is varied between 5 and 50 nm.

electric field further. As shown in Fig. 9 for a sloped depth large enough for both field peaks not to overlap (50 run), low field enhancement factors can be obtained for only a very slight rounding of the comers. For a very small sloped region, the same field enhancement is obtained as for rounded comers. For sloped depths between I and 3 times the radius of curvature, a transition is seen between the curves for rounded comers and the curve for large sloping.

4. Top corner rounding If the shape of the comer can be adjusted as described above, the enhanced dectrical conduction due to this comer will disappear. By adjusting the polysilicon etch process, a slope can be obtained in much the same way as is done for contact window etches. An isotropic-ankotropic polysilicon etch results in a polysilicon profile with a doped top comer and straight sidewalls. The sloped comer will reduce the field enhancement, while the straight sidewalls are necessary for linewidth control and for the sidewall spacer formation on submicron CMOS devices.

Fig. 8. Electric field distribution in the neighbourhood of a sloped and rounded polysilicon top corner.

430

A possible way of obtaining rounded corners on the polysilicon profde has been suggested in the past.

Microelectronics Journal, Vol. 24

When an oxidation is performed on a very highly doped (>5 x 102°/cm3) polysilicon layer, all sharp peaks in the profile are smoothed [7]. However, this method has some drawbacks. The high level of the doping results in a large spread in the oxide thickness obtained, which makes control difficult. Also, this high level doping is not always compatible with the rest of the process. An alternative way of increasing the radius is to'use an isotropic NF3 polysilicon etching, which is done after the normal polysilicon dry etch and resist strip. This etch removes a tiny layer of polysilicon (a few nm) from the surface and sidewalls of the patterned layer. As a result, a slightly rounded corner is obtained. Figure 10 shows tunnelling currents measured on overlapping capacitors with rounded polysilicon corners. Compared to non-overlapping and standard. overlapping capacitors, a reduction of tunnelling current by more than I decade is observed, allowing for an increase of 25% in the applied voltage without any excessive current flow (100nA/cm2). The

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Fig. 11. Influence of oxidation temperature on tunnelling current density measured on overlapping polyoxide capacitors which have received a rounding etch. influence of the edge effects is, however, not fully removed. This is in agreement with the calculations since the radius obtained with a 20 nm etch (which must be smaller than 20 ran) still results in a field enhancement equal to or larger than 2. Figure 11 shows the influence of the oxidation temperature o n the tunnelling current, measured on capacitors which received a corner rounding etch. The measured tunnelling current is, in all cases, lower than for standard overlapping capacitors but higher with respect to non-overlapping capacitors, which means that tunnelling at the edge is still dominant. However, the fact that a temperature effect is seen mews that the shape of the polysilicon corner is influenced by the oxidation temperature, resulting in sharper corners at lower oxidation temperatures. An oxidation at low temperature is thus seen to reduce the effect of the corner rounding etch.

5. Bottom part of the edge Besides the importance of the top corner, the shape of the bottom corner of the overlapping edge also influences the current. The shape of this corner is

431

L Haspeslagh et aL/Edge effects on polyoxide capacitors

influenced by different effects. First, not only are the polysilicon sidewalls oxidized but there is also an oxidation under the polysilicon. Ks a result, a kind of bird's beak is formed, lifting the bottom surface of the polysilicon layer. In addition, asperity enhancement of the oxidation process sharpens the corner, resulting in a thinner oxide in this region. In order to calculate the local electric field distribution in the region of this bottom corner without neglecting these effects, the structure has been simplified as shown in Fig. 12. The overhpping edge has been assumed to lie in an active area so that both polysilicon layers are isolated from the silicon substrate by a thin oxide layer. The electric field has been calculated for this structure for a positive voltage applied to the top polysilicon layer, while the bottom polysilicon layer and the substrate are grounded. The result is shown in Fig. 13. No high electric field peak can be seen near the surface of the bottom polysilicon layer, which means that no excessive tunnelling current will flow between both polysilicon layers. However, a high field peak is present at the opposite interface near the corner of the top polysilicon layer. This field peak can be the cause of reliability problems. When a negative voltage is applied to the top layer, it will cause a high tunnelling current. Further work is rg

Poly 1

Fig. 13. Electric field distribution in the bottom part of the overlappingedge. required to optimize the polysilicon shape in this region.

6. Conclusion

In this work it is shown that process optimi~ations which reduce the polysilicon asperity field enhancement on non-overhpping polyoxide capacitors have almost no influence on the tunnelling current in the case of an overlapping polyoxide capacitor, due to edge effects. Calculations have shown how the tunnelling current is affected by the exact shape of the corner of the overhpping edge, and how this shape has to be changed in order to obtain a better result. It has been shown that a slight sloping and rounding of the top corner results in an appreciable reduction of the local electric field. Also, the influence of the shape of the bottom corner has been shown. FinaUy, the desired rounding of the corners has been shown to be realizable by using a short isotropic N F 3 plasma, resulting in tunnelling current reduction by 1 decade. Acknowledgement

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Pig. 12. Schematic representation of the structure used to calculate the electric field distribution in the region of the bottom of the overlapping edge.

432

This work has been supported by the Commission of the European Communities under ESPRIT project 2093, 'Advanced Prom Building Blocks'.

Microelectronics Journal, Vol. 24

References [1] S. Moil et al., IEEE Trans. Electron Dev., ED-38 (1991) 270-277. [2] M. Hendricks and C. Mavero, J. Electrochem. Sot., 138 (1991) 1466-1474. [3] I~ Ohyu etal., J. Electrochem. Sot., 137 (1990) 22612265.

[4] G. Groeseneken and H. Maes, IEEE Trans. Electron D~., ED-33 (1986) 1028-1041. [5] R. B. Marcus and T. T. Sheng, J. Electrochem. Sot., 129 (1982) 1278-1282. [6] A. Roy, F. IL Libsh andM. H. ~Tkite, Solid State Electron., 32 (1989) 655-659. [7] K. Shinado et al., Abstract of the Electrochem. Soc. Fall Meeting, 1983, pp. 354-355.

433

Microelectronics Journal, 24 (1993) 4 3 5 - 4 4 4

Dielectric properties of polyoxides for EEPROM G. Fernholz and H.-Th. Benz Eurosil Electronic GmbH, Erfurterstr. 16, 8057 Eching, Germany

Polyoxides for nonvohtile memories have been grown in a tetrachloroethane atmosphere at temperatures in the range 900-1000°C, and subsequently electricallycharacterized. A comparison between poly-doping by POC13 and phosphorus implantation is made. Implantannealsare performedby rapid thermal annealing(RTA)or in a furnaceprocessat 900°C and 1000°C. The effect of polydeposition temperature and phosphorusconcentrationon polyoxidequalitywasinvestigated. Breakdownfieldsincreasewithincreasingoxidationtemperature, and an improvementof I-V behaviour is seen. A reduction of polysiliconsurfaceroughnesswith increasingtemperatureand a simultaneousreductionof field-enhancedleakagecurrentshave been found.The damageintroducedby implantationchargingis shown.

1. Introduction he breakdown and leakage currents of polyoxides determine the reliability and data retention of double poly memories. Besides oxidenitride-oxide (ONO), polyoxide is still of interest for electrical erasable programmable read only memories (EEPROMs), fulfilling the electrical demands and offering the advantages of simpler fabrication [1, 2].

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The electrical characteristics of polyoxide depend not only on the oxidation process itself, but also on poly-deposition and doping as well as on etching

0026-2692/93/$6.00

residues. Post-oxidation implants may introduce contamination or damage to oxides by charging, and cause early breakdown. In this paper we present the results of our investigations on the influence of the process parameter on polyoxide quality, as used in a floating gate tunnel oxide (FLOTOX) EEPROM fabrication. Overlapping double-poly capacitors are used for the floating gate and partly in the high voltage generators. Figure 1 shows the cross-sections of the FLOTOX cell and of the capacitors with different polyl to poly2 overlap. The deposition conditions of polysilicon, as well as the poly doping and the oxidation conditions, determine breakdown fields and current transport [3-8], since these processes influence the surface roughness and the shaping of the poly comers. As a consequence of poly surface asperities where the electrical field locally increases, early breakdown and enhanced current leakage occur. Recently, a lower oxidation rate on silicon surface asperities and comers due to the local field has been explained by an ionic oxidation model [9]. In accordance with this theory, polyoxide growth uniformities depend on polysurface smoothness and dopant segregation.

© 1993, Elsevier Science Publishers Ltd.

435

G. Fernholz and H.-Th. Benz/Polyoxides for EEPROM

CONTROLGATE GAi O X I O E / I \

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before and after current stress can be attributed to the presence of oxide traps [11].

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2. Experimental Investigations covered by the present work comprise the influence of polyoxidation temperature, the addition of TCA (trichloroethane) to the oxidation, and doping by phosphorus implantation in comparison to pOC13 on polyoxide characteristics. In the fabrication process sequence, source-drain implants follow poly oxidation. The evidence of early breakdown due to charging is found by an experiment in which flood gun setting and poly oxidation temperature were varied. Poly was deposited by the standard 620°C process and at 570°C for investigating its contribution to surface roughness. The influence of TCA was investigated by varying the content from 0.5 to 1% in a dry oxidation atmosphere at temperatures of 900 and 1000°C. Breakdown behaviour and J-E characteristics (current density vs field strength) were studied for temperatures ranging from 900 to 1000°C. The slope of the J-E curves gives information on the poly-oxide interface roughness [10], whereas the difference of the current densityJ at a given field E

436

The characterization ofpolyoxide was performed on plate and overlapping capacitors, using ramped voltage until breakdown and I-V measurements. The test capacitors have various areas and area-toedge ratios. The I-V measurements were carried o u t u s i n g an HP4145A parameter analyser with guard technique at a medium integration time (20 ms). The error caused by setup leakage and parasitic capacitor loading currents was minimized by applying the vokage to the polyl plate; the current was measured at 0 V on the poly2 plate. In this way only the 'leakage' and loading cawcentof the test capacitor are measured. For ramped voltage measurements an automatic mapping equipment was used. The oxide thickness needed for field strength calculation was determined with a capacitance meter at 1 MHz. Evaluation with RS/1 statistical software [12] produces the results in a boxplot graphics representation.

3. Results and discussion For oxides on crystalline silicon, the use of TCA during oxidation offers the advantages of neutralizing mobile charge at high temperature oxidation and an increase in breakdown fields for low temperature oxidation [13]. None of these facts holds for polyoxides. Figure 2 shows the boxplots of breakdown field distribution of plate capacitors for polyoxides grown on POCl3-doped poly with TCA variation. No improvement of breakdown field due to the introduction of TCA at low oxidation temperatures (900°C) is achieved. The same conclusion is also valid for overlapping edges. The dielectric characteristics of polyoxides are mainly determined by the poly surface roughness

Microelectronics Journal, VoL 24

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[10, 11, 13].J-E curves with a negatively biased first poly layer show, for all TCA contents, the same shape and value of current density. The fieldenhanced current density at 2 MV c m -1 is 1 x 10 -9 A c m -2.

The measurement of J-E curves after current stress application gives a measure for oxide traps [10, 11]. For this purpose, the difference betweenJ-E before and after stressing has to be evaluated. Neither the difference in current density nor the slope o f t h e J - E curve show a dependence on TCA introduction. Therefore we conclude that TCA has no influence on trap levels. An improvement in polyoxide quality is achieved

only by increasing the oxidation temperate (Fig. 2), which increases the breakdown fields, reduces the slope ofJ-E characteristics and trapping in the oxide. A smoothing of poly surface roughness results from higher oxidation temperature.

A similar result is obtained from an experiment with temperature variation in several steps from 900 to 1000°C. The increase of breakdown fields for both plate and overlapping capacitors can be seen in Figs. 3a and b.

inter alia, on the doping level and the doping_ technique. For a phosphorus content above 5 x 10~' c m -3, breakdown fields > 4 MV cm -2 have been reported [4]. Moreover, high phosphorus concentrations promote the corner rounding ofpoly edges [4]. Therefore, in addition, the interaction of oxidation conditions with poly doping was investigated. Phosphorus was implanted with high doses, above 5 x 10 is cm -2 at 50 keV. No implant oxide was used, as previous experiments had showed no advantage in using it. The implant was annealed by RTA and in a conventional furnace process, using different temperatures. The comparison of Fig. 4a and b demonstrates that doping by implantation (compared with POC13 doping, Fig. 2), and the addition of TCA to the Polysilicon surface roughness depends,

437

G. Fernholz and H.-Th. Benz/Polyoxides for EEPROM

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Fig. 3. Polyoxide breakdown of plate capacitors (top) and overlapping capacitors (bottom), with polyoxidation temperature 900-1000°C, POCI 3 doping.

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Microelectronics Journal, Vol. 24

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439

G. Fernholz and H.-Th. Benz/Polyoxides for EEPROM

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Fig. 5. Polyoxidebreakdownofphtecapacitors for varied o~ddationtemperature, polydopingbyimphnt, annealedat900°C (top) and 1000°C (bottom).

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Microelectronics Journal, Vol. 24

oxidation at 900°C, offer no advantage with regard to the breakdown fields of plate capacitors. In contradiction to ref. 4, lower doping results in higher breakdown fields. This observation holds also for the overlapping capacitors where the first poly layer is doped by implantation. Even in this case, no improvement with higher doping is seen at 900°C oxidation. An improvement of breakdown fields of overlapping capacitors is only obtained for higher doping at higher oxidation temperatures (1000°C). Surface smoothing and corner rounding seem to occur when using both high temperature and high doping. Figures 5a and b show the improvement of the breakdown field with higher oxidation temperature o n 1"5 X 1016 c m -2 phosphorus implanted and furnace annealed plate capacitors. Comparing the

J-E characteristics of the different implant doses for highly implanted and high temperature oxidized interpoly, no fleld-enhanced currents or trapping in the oxide are seen for plates or overlapping capacitors. This again demonstrates a smooth interface and no humps at poly edges. Figure 6 shows the evolution of theJ-E characteristic with increasing oxidation temperature (doping 1"5 X 10 Is c m -2, 1 0 0 0 ° C amlc~). From 900 to 1000°C the leakage current decreases (see curves for virgin interpoly) due to decreasing surface roughness and the trap density decreases as well, as is seen from the difference between the J-E curves before and after current stress. The deposition of amorphous silicon offers the advantage of a smoother surface when doped by implantation [6, 7]. In this work polysilicon was

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441

G. Fernhoiz and H.-Th. Benz/Polyoxides for EEPROM

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POCL 5 3.36519 0.272283

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0

0

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15

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0 5e15 6 4.249304 0.246952

le16 6 3.569737 0.151943

2e16 8 2.90103 0.862139

POCL 5 3.451813 0.569533

Fig. 7. Polyoxide breakdown ofphte capacitors (top) and overlapping capacitors (bottom) for poly deposited at 570°C, doped with POC13and phosphorus implant. Polyoxidation was carried out at 900 and 1000°C.

442

Microelectronics Journal, VoL 24

deposited, closely to the amorphous state at 570°C. For doping, POC13 and 5 x 101s-2 x 1016 c r n - 2 50 keV phosphorus implant was used. Figure 7 shows the measured breakdown field at different doping concentrations together with a comparison of900°C and 1000°C polyoxidation processes. The lowest doped samples show the highest values of breakdown. Overlapping capacitors show higher breakdown fields than plates. The area of the plate capacitors used in this evaluation was three times higher than the area of the overlapping capacitors. An explanation for the unusual breakdown behaviour was found by looking at the J-E characteristics and using a scanning electron microscope (SEM). The current through the oxide was typically caused by field enhancement. The SEM shows a very rough interface in all cases. We conclude, therefore, that very accurate control of polydeposition conditions is needed for surface smoothing.

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Our final observationsconcern the processesfollowing polyoxidation. Self-aligned source-drain technology needs a high dose implant after polyoxidation. Implants introduce damage to thin oxides by charging, which depends on implanter settings and photoresist coverage [15]. Figure 8 shows the influence of the flood gun current setting on interpoly-oxide breakdown fields. The effect is a lower breakdown field for the implanted samples, independent of the implanted species (5 x 10is cm-2 50 keV boron, 6 x 10is cm-2 90 keV phosphorus). Polyoxides grown over edges are even more sensitive to implant damage. The damage on 900°C polyoxides is very pronounced. When higher oxidation temperatures are introduced, breakdown fields are shifted towards higher values (as previously shown), whereas the sensitivity towards post-oxidation implants is partially diminished (see Fig. 9). The introduction of high oxidation temperatures and an optimization of source-drain implants shifts the written and erased Vt-valuesof the EEPROM cells to a symmetrical EEPROM threshold window and a higher breakdown yield. Although the tunnel oxide is also influenced by the higher temperature, the cells

Q 651

O ~t= Mean

ZQR

601 3.351522e+08 4.19918e÷07

~ 2,59038e÷08 1.33489e÷08

2.?10537e+O8 1.171206e+08

6o 269 2.694721e÷08 1.236932e+08

Fig. 8. Breakdownfieldsof plate capacitorsfor variedflood gun current. At '0' no implantswere effected. still meet the demand of >10 s programming cycles. 4. Conclusion We have shown an improvementin breakdown fields of polyoxides, both for plate and overlapping capacitors, using oxidation at 1000°C. No influence of TCA has been seen. Comparing doping by POC13 and phosphorus implantation, no advantage of implant has been found with regard to breakdown fields. The damage by source-drain implants on 900°C polyoxides has been demonstrated. Acknowledgement The authors thank E. Bielefeld and H. Henschel for sample preparation and Th. Neukel for performing

443

G. Fernholz and H.-Th. Benz/Po/yoxides for EEPROM

4.5

..----I1¢""'" o

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da

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i 80 F:IooO

gun

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Polyox

+Edges

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.--,,=.--Plate

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.--v~.--EcIges

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Polyox Polyox

Fig. 9. Breakdown fields of plate and overhpping capacitors for varied flood gun current, 900°C and 1000°C, poly oxidation. the electrical measurements. W e are indebted to D r S. H/iseler for encouraging this w o r k and critically reading the manuscript.

This work was part of the APBB 2039 ESPRIT project.

References [1] S. Mori et al., IEEE Trans. Electron Dev., 38 (1991) 270. [2] S. Mori et al., IEEE Trans. Electron Dev., 38 (1991) 386. [3] T. Kamins, PoIFTystalline Silicon for Integrated Circuit App//cat/ons, Kluwer Academic, Boston, MA, 1988. [4] T. Ono et al., IEDM Tech. Dig. (1985) 380. [5] Y. Wang et aL, J. Electrochem. Soc., 138 (1991) 214.

444

[6] M. Hendriks and C. Mavero, J. Electrochem. Soc., 138 (1991) 1466. [7] M. Hendriks and C. Mavero, J. Electrochem. Soc., 138 (1991) 1470. [8] L. Farone, R. D. Vibronek andJ. T. McGinn, IEEE Trans. Electron Dev., ED-32 (1985) 577. [9] D. R. Wolters and A. T. A. Zegers-van Duijnhoven, Microelectron. J., 24(4) (1993) 333. [10] L. Farone and G. Harbeke, J. Electcochem. Soc., 133 (1986) 1410. [11] G. Groeseneken, IEEE Trans. Electron Dev., ED-33 (1986) 1028. [12] RS/1 BBN Software Products, Div. of Bok Bernek and Newman Inc. [13] E.J. Jansens and G. J. Deklerck, J. Electrochem. Soc., 125 (1978). [14] P.A. Heimann, S. P. Muraka and T. T. Sheng, J. Appl. Phys., 53 (1982) 6240. [15] H. Mutoetal., Conf. Solid State Dev. Mat., Sendai, 1990, p. 179.

Microelectronics Journal, 24 (1993) 4 4 5 - 4 5 1

Influence of series resistance in oxide parameter extraction from accelerated tests data F. Pio, L. Ravazzi and C. Riva SGS-Thomson Microelectronics, Central R&D, Via Olivetti 2, 1-20041 Agrate, Italy

Accelerated reliability tests on thin oxide capacitors can be affectedby series resistanceeffects at high stressconditions.The purpose of this work is to point out such problems, which concern both measurements and simulations. It is shown that breakdown electric field is overestimated. Due to the resulting non-uniform stress, charge density at breakdown is underestimated if the test structure layout is not accurately designed. In any case, the series resistance effects can have an undesirable impact on the reliability evaluation of thin dielectrics.

1. Introduction he reliability o f thin dielectrics is one o f the most important issues in the generation o f new devices and plays a primary role in the wafer-level reliability approach. This is mainly related to increased circuit complexity and memory capacity [1]. Accelerated tests are proposed in order to evaluate the appropriate parameter o f merit: charge density at breakdown (QBD) or breakdown electric field (EBD). Usually an exponential ramp current stress (ERCS) [2, 3] or a constant current stress (CCS) are preferred in the former case, while a

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linear ramp voltage stress (LRVS) is chosen in the latter; projection algorithms for EBD data to forecast time-dependent dielectric breakdown at constant voltage have also been proposed [4, 5]. Often the scientific debate concerns the validity o f the hypotheses and the approximations introduced in the interpretation o f the statistical distribution o f measured data. In this work we focus on the problems that are possibly encountered in measuring EnD or QBD" The correct determination o f these quantifies can be influenced by intrinsic physical phenomena, such as inversion layer formation in a lightly doped capacitor electrode [6], or by effects related to process and layout. We give particular emphasis to the layoutrelated effect o f series resistance on the collection o f correct raw data. This can constitute a serious problem in the case o f test structures for oxide reliability; in fact, capacitors o f larger and larger area must be used in order to obtain statistically meaningful information as the device gate area increases.

© 1993, Elsevier Science Publishers Ltd.

445

F. Pio et aL/Series resistance effects on test data

2. Results and discussion

I

E

In the accelerated test, either an LRVS or an ERCS is applied to the capacitor under test. From the physical point of view, in either case, a current injection is forced through the oxide, following the FowlerNordheim law, until breakdown occurs. It is evident that the cause of intrinsic breakdown has to be the same, independently of the method used to stress the oxide. In real capacitors a series resistance R~ is associated with the electrodes (doped polysilicon, polycide or substrate), also depending on the capacitor layout. The effect of such a resistance becomes more and more important as the injected current increases. Part of the externally applied voltage (Vex,) drops across R~, and the field in the oxide is therefore reduced with respect to V,,JTox. It follows that the measured I-Vcurve departs from the theoretical one. In Fig. 1 we show the J-V characteristics in both polarities, measured on capacitors of different area. The test structures were square capacitors with 9-10 O / N POC13-doped poly-gate, 1.7-2-5 fl cm p-substrate; oxide thickness was 12 nm. The larger the capacitor area, the larger is the current at the same level of stress, and therefore the effect of the series resistance becomes relevant at lower current densities. The deviation from the ideal characteristic is a function not only of the FowlerNordheim current flowing through the oxide, but also of the R, value, depending on the capacitor layout and the technological process.

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Fig. 1. Current density vs gate voltage characteristics for 9-10 f~/[-I P O C I 3 doped poly capacitors on 1-7-2.5 N.cm p-substrate. Capacitor area: (a) 1 mm 2, (b) 4 mm 2, (c) 10 mm 2.

Oxide thickness: 12 nm. Top: Vg> 0; bottom: Vg< 0.

A simple model, taking into account the series resistance effect on an ideal capacitor, is illustrated by the equivalent circuit shown in the inset of Fig. 2. If we assume the capacitor, of area ac and oxide thickness Tox, to exhibit pure Fowler-Nordheim behaviour (without degradation due to charge trapping), the Im-Ve~ characteristic can be calculated by solving the set of equations:

446

V.x,(I~) = ~'IFN + E "Tox where AFN and Bm are the F-N parameters and the electric field E is given by VFN/Tox, VFNbeing the voltage drop across the capacitor.

Microelectronics Journal, VoL 24

10 0

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the derivative o f the experimental I - V characteristic can be considererd. In Fig. 3 the derivative curve, indicating the overwhelming role of R, at high injection levels, approaches a value of about 100 N. If the effect of R, is low, or is comparable to trapping phenomena, oxide breakdown usually occurs before the Im-Ve,~ characteristic has reached a constant slope. In these cases it is difficult to exuract a direct measurement of R, became the derivative d / m / d V ~ does not yet behave asymptotically, and a comparison with the theoretical I - V curve is needed.

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,

15

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Gate voltage IV] Fig. 2. SimulatedI-V characteristicsof: (a) 100 N resistance; t h i c k o x i d e capacitor; (c) series of capacitor and resistance (electriccircuit shown in the inset).

(b) 1 0 - 3 (:In 2 i d e a l 1 0 n m

The result is shown in Fig. 2, together with the I - V curves o f the ideal capacitor and the series resistance.

In order to make explicit the series resistance effect, the ERCS measurement has been performed in accumulation on a 10-3 cm 2 area capacitor with 12 am

To obtain a direct evaluation o f the influence o f R,,

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area: 4 mm2, oxide thickness: 12 nm; Vg> 0.

447

F. Pio et aL/Series resistance effects on test data

thick tunnel oxide and heavy-doped substrate and polysilicon. This structure can be assumed to be exempt from R, effects due either to layout or to process. In Fig. 4 we show the J-V characteristics with an external series resistance R , ranging from 0 to 500 N, as a parameter. In Table 1 we report the average electric field Em necessary to force 10-s A/cm 2, the average QBD value, and the average breakdown electric field EBb (Ve=/To,,) on a statistical population o f about 100 samples. As expected, the value o f Era is not affected by the external R , but that of EBD is. The table also shows the corrected breakdown electric field, obtained taking into account the voltage drop evaluated at the breakdown current ( A V = RChD). ,

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In Fig. 5 (left) the measured electric field distributions for P~ = 0 and /L = 500 fl are shown. Figure 5 (right) shows the results of the correction. It must be emphasized that any error in the determination of EBD has a strong impact on lifetime prediction according to any o f the projection algorithms [4, 5]. In the case presented, the forecast lifetime is overestimated by several orders of magnitude. The uniformity of current injection is not altered in the case of an external series resistance, and therefore the Q~D value does not change in this case. On the other hand, it must be noted that & can introduce some problems in QBD measurements if the capacitor cannot be considered ideal (i.e., the series resistance is unevenly distributed on the electrodes). This implies that the voltage on the electrodes is a function of position, and therefore the current is not uniformly injected through the oxide. The results of an HFIELDS [7] simulation confu'ms this hypothesis. Figure 6 shows the position-dependent voltage at the Si/SiOz interface of a metal-gate capacitor on a p-substrate with an n + ring for three externally applied positive gate bias conditions. A sketch of the structure considered is shown in the inset. It is evident that in this case the border region of the capacitor undergoes a much stronger local current density stress because of the higher effective field, as shown in Fig. 7.

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Fig. 4. Current densityvs voltage from ERCS measurement with different externalresistancesR,. 2-3N/r'l poc13-doped poly-gate capacitor on n+ subslxate. Capacitor area: 10-3 cm2; oxide thickness: 12 nm; Vg> 0.

The same problem arises for negative gate bias conditions. As shown in the inset of Fig. 8, the current flowing through the polysilicon layer induces a voltage drop which is responsible for an

TABLE 1 Dependenceof initial and breakdownelectric fields and breakdown charge density on external series resistance

448

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Microelectronics Journal, VoL 24

N t e r Correction for Rs

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although the potential at the contact increases by 2 V, the potential at the opposite edge ranges within a 400 mV interval. It is therefore expected that breakdown will preferentially occur at the side close to the contact. In any case, t h e / L could affect the estimations o f both EBb and QBD.

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Fig. 6. HFIELD simulation showing the Si/SiO 2 interface potential as functionof distancefrom the ground n+ ring in a 10 nm thick oxide metal gate capacitor. The capacitor crosssectionis alsoshown.Gateappliedvoltage:(a) 11.75V; (b) 12 V; (c) 12.25 V. uneven gate current distribution. In Fig. 8 the potential of a 2" 5 ldl/I-I polysilicon layer is plotted against the distance from the contact, on the right side o f the capacitor, for a 10 nm oxide thickness;

The results presented so far point out the influence of a series resistance on correct parameter determination in thin oxide reliability test structures. This is particularly evident in EBb measurement and consequently in TDDB projection. Moreover, due to the current clampingeffect of the series resistance, problems can also arise in the accurate determination of breakdown when an automatic parametric system is used. To avoid the undersirable effect o f R , great attention must be paid to the layout and the technical characteristics of the capacitor. In particular, even greater attention is necessary for high periphery capacitors if long resistive strips are present. In general, at low injection levels, the defective tails of the distributions of large area capacitors are not affected by the R~. Hence, defectivity problems can be analysed on large-area capacitors, provided that low enough injection currents are flowing in the

449

F. Pio et al./Series resistance effects on test data

Current

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X [cm] Fig. 8. The potential V(x) along a polysilicon layer, with a contact on the right side, is plotted against the distance from the contact according to the equation shown. The behaviour of the potential leads to an uneven distribution of the FowlerNordheim current demityJF N. The sheet resistance is 2.5 kN/Q and the oxide thickness is 10 nm.

450

The role of series resistance in MOS capacitors for thin oxide reliability evaluation has been studied. A relevant effect o n EBD determination has been pointed out in large-area capacitors. Moreover, a non-uniform current injection stress occurs whenever the series resistance is not negligible. As the capacitors for thin oxide defectivity evaluation get larger and larger, more attention must be paid to the test structure design in order to minimize the series resistance.

Acknowledgements We are grateful to A. Saini for his support in the measurements. This work has been partially supported

Microelectronics Journal, Vol. 24

by the ESPRIT project under Contract ('Advanced P R O M Building Block').

References [1] R. Fair, Proc. IEEE, 78 (1990) 1687. [2] D. Crook, Proc. 29th IRPS, 1991, p. 337.

2039

[3] P. CappeRetti et al., Proc. ICMTS91, 1991, Vol. 4, p. 81. [4] A. Berman, Proc. 19th IRPS, p. 204. [5] J. Lee et ai., IEEE Trans. Electron Dev., 35 (1991) 2268. [6] S. Wang et al., IEEE Electron Dev. Lett., 12 (1991) 617. [7] G. Baccarani et al., Proc. N A S E C O D E IV, Dublin, 1985, J. H. Miller (ed.), p. 3.

451

Microelectronics Journal, 2 4 (1993) 4 5 3 - 4 5 8

Thin oxide nitridation in N,O by RTP for nonvolatile m e m o r i e s 2

N. Bellafiore, F. Pio and C. Riva SGS-Thorason Microelectronics, Central R&D, Via Olivetti 2, 1-20041 Agrate, ltalT

6-15 nm thick runnel dielectrics obtained by rapid thermal processing are considered. The growth kinetics of silicon oxidation in O z and oxynitridation in NzO are reported. Chemical-physical analyses, performed by Auger electron spectrometry, show evidence of nitrogen piling up at the Si/dielectric interface on nitrided films. The potential barrier height is unchanged with respect to that of Si/SiO2. Electrical characterizationof the thin layers was performed on polysilicon-gate N* area capacitors, measuring FowlerNordheim conduction,breakdown electric field (EBb), charge density at breakdown (QBD) and charge trapping under acceleratingstressconditions.Oxynitrideddielectricsexhibitan improvementin F~D,their Qs, is increasedby a factor of about two with respect to control oxide, and less negative charge trapping is observed. The endurance of EEPROM (electrical erasable programmableread only memory) cells has also been measured for up to 107 cycles.

1. Introduction continuous research effort is being made to improve the characteristics of the dielectrics needed in VLSI and ULSI devices [1], especially the tunnel oxides used in EEPROM (electrical erasable programmable read only memory) and flashEEPROM memory applications [2]. Rapid thermal processing (RTP) oxynitridation in a nitrous oxide (N20) atmosphere seems to be a promising technology, thanks to its process simplicity, good thickness control and low thermal budget [2, 3].

The use of nitrogen to improve the quality of ultrathin oxides started at the beginning of the 1980s. The most studied process has been nitridation in NH3 ambient using the RTP technique [4]. In such a process the nitrogen atoms accumulate both at the polysilicon/dielectric surface and at the silicon/ dielectric interface, acting as a barrier against the diffusion of gate doping species (e.g. boron) and improving the resistance of the oxide against hot electron degradation. Unfortunately the use of ammonia as the nitriding species produces an increase of bulk electron traps (due to a high residual density of hydrogen atoms in the film), an increase of fixed charges and an increase of interfacial state density; in order to minimiT~e these negative effects, successive reoxidation and/or annealing treatments are required, making the whole process less attractive.

A

0026-2692/93/$6.00

The use of N20 gas as the nitriding species instead of N H 3 eliminates the hydrogen-related problems. In early works [3, 5], as well as in very recent applications [6, 7], it is reported that good quality dielectric thin films can be obtained by rapid thermal oxidation followed by RTP nitridation in an N20 atmosphere. The observed characteristics are: good barrier against the diffusion of boron from BF2 doped gates, a decrease in interracial state generation

© 1993, Elsevier Science Publishers Ltd.

453

N. Bellafiore et aL/Thin oxide nitridation in N20

and electron trapping during charge injection, and a considerable increase of QBD with respect to RTP control oxide.

degradation during the endurance measurement. Typical write/erase conditions were: 14 V programming voltage, 2 ms pulse duration with 1 ms

rising time. The improved quality of the nitrided oxides would be the consequence of nitrogen accumulation at the interface with the silicon substrate, resulting in a release of the mechanical stress, the saturation of dangling bonds and a stronger structure, due to the higher energy of the N-Si bond with respect to the O-Si one [5]. 2. Experimental details

The thin films were grown on 6" (152 mm) wafers in the temperature range 1000-1100°C, using the AG 4100 system. Thicknesses were measured by both the ellipsometric and the capacitance-voltage characteristic methods; the refraction index and dielectric constant used were those of amorphous silicon dioxide (n -- 1"46, eo~---3-9) [8]. As will be discussed in the next section, this can be considered correct in relation to the small fraction of nitrogen atoms incorporated. The electrical characterization of the thin layers was performed on POC13 polysilicon-gate N + capacitors on phosphorus-doped substrate (~2 x 1019 cm -3) with an area in the range 10-s-10 -3 cm 2. Two types of electrical stress were employed: exponential ramp current stress (ERCS) [9] and constant current stress (CCS). In the ERCS tests, an exponentially increasing current density (10-6-10 A/cm z) was forced through capacitors of area 10-3 cm2; QB, and breakdown electric field (E,D) statistical data were obtained. In the CCS tests, a constant current (0" 1 A/cm 2) flowed through the dielectric; the capacitors used in these tests had an area of 10-5 cruZ; from these measurements Qel) and voltage shift during stress (AVm) were recorded.

3. Results

In Fig. 1 (top) we report the growth kinetic of the silicon dioxide obtained by the RTP technique in an O2 atmosphere at three temperatures. Figure 1 (bottom) shows the variation of oxynitride thickness vs time during an RTP treatment at 1100°C in NzO ambient. The nitridation rate was found to be independent of the temperature at which the oxide had been grown. Figure 2 illustrates the Auger electron energy spectrum of an oxynitride in the energy range of O, Si and N. In the Si band it is possible to observe the peak energy shift related to the transition from the Si-O bound state (in the oxide) to the Si-Si bound state (in the substrate). The integral in each energy band is proportional to the concentration of the corresponding species for any given sputtering cycle

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T I M E (s) Single poly EEPROM cells made in 0-8pro technology with oxide and oxynitride tunnel dielectrics were built and subjected to write/erase cycles in order to investigate the window threshold

454

Fig. 1. Top: rapid thermal oxidation kinetics at three different temperatures, bottom: rapid thermal m'tridation in N 2 0 of 7 nm thick oxide as function of time (ellipsometric measurement performed with refractive index n = 1-46).

Microelectronics Journal, Vol. 24

•

480

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53050 110 340 K / N r ; l l C ENERGY (eV)

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Fig. 2. AES spectrum in the energy range of elements O, Si and N vs sputtering time (proportional to depth).

(i.e. depth from the surface). From the data illustrated in Fig. 2 it is therefore possible t o extract the concentration profale ofO, Si and N, as shown in Fig. 3 for a typical nitrided oxide. All the oxynitrides featured an evident nitrogen accumulation at the Si/dielectric interface, estimated to be 2% atomic. To compare the characteristics of RTO oxide and nitrided samples we chose 1050°C as oxidation temperature and 1100°C for the nitridation phase. A comparison between the Fowler-Nordheim curves of the SiO2 and SiOxN7 samples (Fig. 4) shows that no significant difference exists; it follows that the dielectric bulk properties are essentially the same (this also justifies the assumption of equal refraction index) and, in particular, the potential barrier height does not vary. The Ean distribution from the ERCS test is shown in Fig. 5, where both gate polarities are taken into consideration. The data show the better quality of the oxynitrides; in fact, the average oxymtride EBDis higher than that of the oxide. The improvement is also confLrmed by CCS measurements, in which the relevant parameter of merit is

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455

N. Bellafiore et al./Thin oxide nitridation in N20

We ascribe these improvements to the aforementioned nitrogen accumulation at the Si/dielectric interface; in fact, annealing pure oxide in an inert atmosphere does not provide such improvements. The nitrogen would reduce the number of defects in the inteffacial region and would strengthen the structure by means of Si-N bonds which are stronger than the Si-O bonds [5].

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oxynitride QBD is about twice as high as for the corresponding oxide, independently o£ the stress polarity, and in the former case less negative charge trapping occurs during stress.

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Write/erase endurance of single polysilicon EEPROM cells in 0"8/am technology with either oxynitride or oxide as tunnel dielectric are compared in Fig. 7. This displays the window threshold degradation versus the programming injected charge for both oxide (]3) and oxynitride (A), showing that there are no remarkable differences between them in respect of this parameter. The inset of Fig. 7 shows the high and low threshold evolution as a function of the number of write/erase cycles (up to 107) for the ceU

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456

Microelectronics Journal, Vol. 24

2.e

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AES analyses on all the oxynitrided samples demonstrated that the nitrogen atoms pile up only at the dielectric/substrate interface with an atomic concentration of about 2%. This is believed to be the reason for the better behaviour of oxynitride.

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The bulk properties of the oxynitrided film are identical to those of the oxide films; in partio,hr, the oxynitridc barrier height is the same as in the Si/SiO2 case, as inferred from Fowler-Nordheim characteristics. The density of charge at breakdown in oxynitrided films improves by a factor of two with respect to the RTP oxide films and, in addition, electron trapping is reduced.

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. . . . . .

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The intrinsic behaviour of the single EEPROM cell has been investigated. Cells with both oxide and oxynitride were subjected to write/erase programming endurance up to 107 cycles, revealing a slight improvement in the case of oxynitride in respect of the degradation of the threshold window.

-4

The results of our experiments confirm the superiority of oxynitrided dielectrics with respect to pure RTP SiO2, suggesting that such dielectric f~-as could play a relevant role in EEPROM and Flash-EEPROM devices of future generations.

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4. Conclusions The growth kinetic of thin film oxides and oxynitrides obtained by means of the RTP technique has been determined.

We are very grateful to A. Losavio for his support in preparing the samples, and to G. Que/rolo for the Auger measurements. This work has been partially supported by the ESPRIT project under Contract 2039 (APBB). References [1] R.B. Fair, Challengesto manufacturingsubmicronultralarge scale integrated circuits, Proc. IEEE, 78 (1990) 1687. [2] H. Fukuda,M. Yasuda,T. Iwabuchiand S. Ohno, Novel N20-oxym'tfidation technology for forming highly reliable EEPROMtunnel oxide films,IEEE Electron. Dev. Lett., 12 (1991) 587.

457

N. Bellafiore et al./Thin oxide nitridation in N20

[3] H. Hwang, W. Ting, D. KwongandJ. Lee, Electricaland reliability characteristics of ultrathin oxynitride gate dielectric prepared by rapid thermal processing in N20, Proc. IEDM 90, 1990, p. 421. [4] A. B. Joshi, G. Q. Lo, D. K. Shih and D. L. Kwong, Performance and reliability of uhrathin nitrided oxides fabricated by rapid thermal processing, SPIE, 1393 (1990) 122. [5] H. Fuhada, T. Arakawa and S. Ohno, Highly reliable thin nitrided SiC)2 film formed by rapid thermal processing in an N20 ambient, Jap. J. Aft, l. Phys., 29 (1990) L2333. [6] Z. IJu, H. Wann, P. Ko, C. Hu and Y. Cheng, Improvement of charge trapping characteristics of N20

458

annealed and reoxided N20 annealed tunnel oxides, IEEE Electron. Deu. Lett., 13 (1992) 519. [7] A. Ditali, V. Mathews and P. Fasan, Hot carriers induced degradation of gate dielectrics grown in nitrous oxide under accelerated aging, IEEE Electron. Dev. Lett., 13

(1992) 538.

[8] M. Moslehi and C. Sarawat, Thin SiO2insulator grown by rapid thermal oxidation of silicon, A ~ . Phys. /arU., 49 (1985) 1353. [9] P. Cappeiletti, P. Ghezfi, F. Pio and C. Riva, Accelerated current test for fast tunnel oxide evaluation, Proc. IEEE ICMTS 91, 1991, Vol. 4, p. 81.

Microelectronics Journal, VoL 24, No. 4

ContinuedJ?om page 332 The chips produced under the C H A M E L E O N programme will have more than ten million transistors - - the T9000 has 3.3 million, the original transputer had 200 000. Currently this complexity is out of reach, but by 1996 STM will have the necessary advanced manufacturing and process technology. The C H A M E L E O N programme has backing from the EEC's Open Microprocessor systems Initiative project (OMI), and Inmos is already in discussion with a number of prospective European partners. To date, over one million transputers have been shipped and STM plans to double that figure in two years. In 1992, STM sold some 285 000 transputers, which brought in US$40 million in revenues.

Contact: Francesca Pick, Inmos, tel~fax: [44] (0)454 616616 / 617910.

IMEC/GENUS COLLABORATE ON CVD RESEARCH The Inter-university Microelectronics Centre (IMEC) at the University of Leuven, Belgium, and Genus Inc. of Sunnyvale, California, have announced a joint research project on tungsten-based chemical vapour deposition (CVD) technology used in manufacturing advanced semiconductor circuits. A Genus 8700 system will be used for basic interfacial studies and for research on impurities in tungsten silicide. Results will be used to optimize CVD processes and to develop new technologies for use in next-generation equipment.

European Contacts: Michel Ouaknine, Genus Europa SARL (France), tel~fax: [33] 1 60 86 37 09/35 57. Anthony Fletcher, Genus Europa (UK), tel~fax: [44] (0)763 262433/262261.

NEW WAFER INSPECTION SYSTEM KLA Instruments, based in San Jose, California, USA, has begun shipments of a wafer inspection system that uses a scanning electron beam microscope to evaluate and detect faults in new semiconductor production processes, including those processes for

the next generation 64 M b i t and 256 Mbit memories. The devices will have features that are too small to be inspected using conventional optical techniques. The KLA 2710 Sempspec wafer inspection system also has the advantage of being about 1000 times faster than current scanning electron microscopes.

SHALLOW ION IMPLANTATION SYSTEM Researchers at Kyoto University in Japan have developed a gas cluster system which allows very shallow ion implantation. The clusters are formed from gases such as argon, and these gases alter the atomic energy and scatter angle influencing the atoms implanted into the substrate. A gas pressurized to several atmospheres is jetted out of a 0.1 mm diameter nozzle and converted into atoms and molecules which are then ionized by an electron beam. The beam is further accelerated with a voltage and irradiated against the silicon substrate. As a result, the researchers claim it is possible to perform shallow implantation of less than 0.1 ~tm.

METAL ETCHER FOR 256 MBIT DRAMS Lam Research, based in the USA, has unveiled its T C P 9600 metal etcher w h i c h is aimed at manufacturers of 16, 64 and 256 Mbit DRAMs. Low pressure is required to maintain critical control, decrease particle contribution and etch both dense and open spaces. The 9600 operates at 1-20 mTorr and uses a high density, planar plasma to etch at rates of 7000-10 000 183/min, depending on the film. This is the second machine in the T C P (transformer coupled plasma) series - - the first was the 9400 polysilicon etcher.

ALTERA/CYPRESS JOINT DEVELOPMENT OF EPLD TECHNOLOGY Altera and Cypress Semiconductor have announced a new agreement to redesign the entire MAX 5000

459

(Cypress CY7C34X) EPLD family to provide speed improvements and reduce manufacturing costs. This agreement is an extension of a five-year technology and product partnership that has resulted in establishing the MAX 5000 EPLD architecture as the dominant high density EPLD family. The new agreement between the two US groups calls for producing the MAX (Multiple Array Matrix) 5000A family using the industry's most advanced EPLD technology. The entire MAX 5000 family is being redesigned by Altera on Cypress' 0.65 ~tm CMOS process. The products will be exclusively manufactured in the Cypress wafer manufacturing plant in Round Rock, Texas, in which Altera holds an 18% interest. The MAX 5000A family rollout is planned to begin in the second half of 1993, and products are expected to be available concurrently from both companies.

Contact: Nigel Toon, Altera Europe, tel: [44] (0)628 488800.

ATMEL PLANS SRAM-BASED FPGAS Atmel, the US manufacturer of EPROM-based programmable logic devices (PLDs), is to produce SRAM-based field programmable gate arrays (FPGAs) during 1993. Atmel's move follows the recent industry trend in which the PLD company Altera added FPGAs to their line and FPGA pioneers Xilinx bought PLD specialists Pluslogic. Another trend is to add manufacturing capability. Altera has bought 18% of Cypress Semiconductor's new 0.65 lim US wafer fab in Round Rock, Texas, and Atmel is adding a China wafer fab to its facility in Colorado Springs, USA. Atmel claims it will have FPGAs with up to 10 000 usable gates before the end of 1993. Atmel has finalized its merger with FPGA house Concurrent Logic and is currently redesigning the Concurrent parts to fit the Atmel foundry. Atmel's China fab has been built and equipped by the Chinese government but Atmel gets all the output from it in return for establishing the process.

460

-

By the end of 1994 Atmel states it will need another fab to supply North America and Europe, and is currently discussing its plans with potential partners governments and corporations. -

PHILIPS AND ES2 OFFER JOINT-SOURCE SERVICE Philips Semiconductors and European Silicon Structures have agreed to offer a joint-source service which will enable their customers to use either of the two suppliers during the life cycle of a design. The new joint venture will give customers a greater choice for optimizing production economics and low requalification costs when their requirements shift from a fast time-to-market approach to high-volume production.

XILINX UNVEILS ITS FIRST EPROM PLD X i l i n x , the US i n v e n t o r o f S R A M - b a s e d programmable logic, has recendy announced its first EPROM-based programmable logic devices. E P R O M - b a s e d programmable logic chips are planned for early 1994, and Xilinx may also be investigating a f o u r t h p r o g r a m m a b l e logic technology - - anti-fuse. The EPROM-based programmable logic chips are a result of the company's takeover of EPROM-based programmable logic specialists PlusLogic. The first chip, the XC73108 which replaces 12 22V10 PAL equivalents, is currently available; in the second quarter a six PAL replacement, the XC7354, will be launched; in the third quarter two chips, the XC7336 and XC7372, will be launched which respectively replace four and eight PALs; in the fourth quarter comes the 16 PAL replacement - - the XC73144. The XC7300s are made on 0.8 l.tm technology allowing 80 MHz clock rates and pin-to-pin speed of 12 ns. Xilinx expects to migrate the family to 0.6 ~tm in the fourth quarter of 1993.