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Investigation of gate edge effect on interface trap density in 3C–SiC MOS capacitors
Materials Science and Engineering B 177 (2012) 1327–1330
Contents lists available at SciVerse ScienceDirect
Materials Science and Engineering B journal homepage: www.elsevier.com/locate/mseb
Short communication
Investigation of gate edge effect on interface trap density in 3C–SiC MOS capacitors T. Gutt a,∗ , T. Małachowski a , H.M. Przewłocki a , O. Engström a , M. Bakowski b , R. Esteve b a b
Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw, Poland Acreo AB, Electrum 236, SE-164 40 Kista, Sweden
a r t i c l e
i n f o
Article history: Received 21 September 2011 Received in revised form 21 February 2012 Accepted 3 March 2012 Available online 18 March 2012 Keywords: Silicon carbide Interface traps Metal-oxide-semiconductor structures Mechanical stress Edge effect
a b s t r a c t This paper reports on investigation of the gate edge effect on the interface trap density characteristics of 3C–SiC MOS capacitors fabricated using four different gate materials and two SiO2 oxide preparation methods. Non-uniform distribution of interface trap densities under the gate was demonstrated by the presence of the gate edge effect, i.e. the dependence of Dit (E) on the ratio of gate perimeter to its area. The strength of the gate effect in different gate/oxide material combinations was studied and it was found that it depends on gate thermal expansion coefficient and adhesion of the gate layer to the oxide layer. The Dit behaviour at shallow energy levels (0.25 eV) was attributed to the reaction of Pb -centres to mechanical stress. The behaviour of Dit at deeper levels was documented but could not be explained in this study. © 2012 Elsevier B.V. All rights reserved.
1. Introduction Spatial distribution of electrical parameter values over the gate area of MOS devices is essential for understanding the effects on device operation of the shrinking device dimensions and application of new materials and/or new processing procedures. As it was demonstrated in [1,2], such MOS device parameters as flat-band voltage VFB , effective contact potential difference MS , or potential barrier height at gate-dielectric interface EBG are not uniformly distributed within the gate area. Using a photoelectric measurement technique with a UV light beam of a 0.3 mm diameter, which was much smaller than the investigated MOS capacitor gate dimensions, it was possible to scan the gate and determine the MS and EBG local values. It was shown that the spatial distributions of those parameters had a dome-like shape with the maximum in the centre of the gate. The difference between parameter values in the centre and at the edges of the structure was considerably large, hence it was called the gate edge effect. The results presented in that study also showed that the most significant manifestation of the edge effect was found in devices with aluminium gates, while it was not detected in case of poly-Si gates [1,2]. The edge effect can also be observed on electrically measured parameters. When flat-band voltage VFB is measured on a series of neighbouring capacitors having different sizes, the measured
∗ Corresponding author. Tel.: +48 22 5487857; mobile: +48 694748104. E-mail address: [email protected] (T. Gutt). 0921-5107/$ – see front matter © 2012 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2012.03.007
VFB values differ depending on the gate size. The detailed analysis proved that the measured VFB depends on a geometrical parameter R which is the ratio of the gate perimeter to the gate area. The R parameter can be understood as a measure of edge region contribution to the whole area of the device [1,2]. In order to determine the factors causing the gate edge effect the distribution of mechanical stress in a MOS structure was investigated. It was demonstrated in [3] using micro-Raman shift measurements, that a compressive stress is present in the gate oxide under the gate, but that stress is relieved locally at the edge of the gate, where it can even change its sign to tensile. The distributions measured in that study were explained in the following way. The metal layer deposited on top of the oxide contracts as it is cooled down and stresses the underlying oxide due to a large difference in thermal expansion coefficients of both materials. During patterning process in which the gate features are defined, the metal layer is discontinued and the compressive stress in the oxide decreases in the places where discontinuity occurs. All those facts prove that the spacial distribution of important MOS electrical parameters under the gate caused by the distribution of mechanical stress in the gate insulator cannot be neglected. Consequently, it is interesting to investigate the influence of the mechanical stress distribution on other electrical characteristics of the MOS system. Interface traps are one of the most important factors determining the quality of the MOS devices. Traps are the major cause of carrier mobility degradation in SiC MOSFETs. The density of traps in SiC is much higher than in silicon due to much more complicated interface physics and chemistry promoting a variety of
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Fig. 1. Schematic picture of the gate stack and the test structure with gate contact sizes.
defects. Although the nature of those defects and their charge trapping properties are widely documented in the literature, mostly with regard to oxygen vacancies, Pb -centres (dangling bonds) or carbon clusters [4–8], little is known about their spacial distributions and dependency on mechanical stress. The goal of this study was to find out whether the gate edge effect influences interface trap density characteristics in 3C–SiC:SiO2 capacitors, and whether the thermal stress distribution in the area of the gate modifies trap properties at semiconductor–insulator interface. 2. Experimental details The investigation was carried out using 3C–SiC MOS capacitors with four different gate materials and two different technological variants of gate SiO2 layers. Two different methods of SiO2 deposition were used by ACREO AB: wet thermal oxidation (in 1 h at 1150 ◦ C) and PECVD (plasma enhanced chemical vapour deposition) followed by annealing in wet oxygen at 950 ◦ C for 3 h, on two identical 3 in. wafers with 10 m n-type (2–3 × 1015 cm−3 ) 3C–SiC (0 0 1) epi-layer provided by Hoya. The thickness of each oxide was 60 nm. Then, both wafers were sawed into 4 quadrants each and MOS capacitors with gate contacts made of nickel, aluminium, gold and poly-silicon (+TiW), were fabricated on each quadrant respectively. The diameters of the circular gate contacts used in this experiment were 0.7 mm (denoted as LL), 0.6 mm (denoted as L), 0.5 mm (denoted as M), 0.4 mm (denoted as S), and 0.3 mm (denoted as SS). The samples are referred to in the paper as PECVD/Ni, Au, Al, polySi, and WET/Ni, Au, Al, polySi, respectively. The schematic picture of the investigated gate stack, showing the structural concept and the materials used is shown in Fig. 1. The electrical measurements were done at the Institute of Electron Technology, using Agilent 4294A impedance analyzer. The relevant gate voltage range and surface potential mapping were established using C–V measurements at room temperature based on the comparison of the experimental and theoretical C–V characteristics. The bulk doping concentration ND used for theoretical C–V calculation was established from C−2 –V characteristics. The conductance method was used to calculate trap density vs. energy distributions Dit (Et ) in the way described in [9]. The procedure consisted in measuring MOS capacitor admittance spectra Y(VG , ω) = G(VG , ω) + jωC(VG , ω) in frequency range f = /2 = 100 Hz to 1 MHz and calculating interface conductance characteristics Gp / − from the measured G(VG , ) characteristics.
Fig. 2. Dit energy distributions measured on PECVD-SiO2 /Ni sample for different gate contact sizes.
diameter (i.e. increasing R – the ratio of gate perimeter to the area of the contact) and increases at deeper states (Ec − Et > 0.5 eV). The dependence of the shape of the Dit distributions vs. R is the clear evidence of the gate edge effect in this sample. In contrast with the distributions measured on poly-Si gates over the PECVD oxide, presented in Fig. 3, the dependence of Dit on the gate size or the coefficient R is considerably weaker at shallow energy levels and increasing at deeper states. It is interesting that the dependence of Dit on R in WET oxide/nickel gate samples is very similar to that of the PECVD/nickel gate, with respect to the direction of Dit changes with coefficient R, as can be seen in Fig. 4. In case of WET/poly-silicon gate samples the Dit distributions presented in Fig. 5 change with R in the opposite direction compared with PECVD/poly-Si samples shown in Fig. 3. The Dit distributions measured on capacitors with Al gates on both oxide types are similar to those with Nickel gates and strongly depend on R. Interestingly, the Dit distributions measured on capacitors with Au gates very weakly depend on R in which they are similar to those measured on poly-Si gate devices. There are two issues which have to be addressed with regard to the results presented above: the origin of traps responsible for the dependence of Dit on R, as shown in Figs. 2 and 4; and the factors inhibiting the edge effect in shallow traps in case of gates made from some materials, as shown in Figs. 3 and 5. As it was discussed in Section 1, the thermal stress in the gate oxide is locally relieved at the gate edge, creating a spacial distribution of stress under the gate. The influence of mechanical stress on interface defects was widely investigated with regard
3. Results and discussion The presence of the gate edge effect in the interface traps energy distributions Dit (E) is an indicator of the influence of the thermal stress distribution at the gate-SiO2 interface and it will be discussed first. The Dit energy distributions measured on nickel gates over the PECVD oxide are shown in Fig. 2. It can be easily noticed that the Dit decreases at shallow states (Ec − Et < 0.5 eV) with decreasing gate
Fig. 3. Dit energy distributions measured on PECVD-SiO2 /polySi sample for different gate contact sizes.
T. Gutt et al. / Materials Science and Engineering B 177 (2012) 1327–1330
Fig. 4. Dit energy distributions measured on WET-SiO2 /Ni sample for different gate contact sizes.
to Si:SiO2 system, where the dominant type of defects were dangling bonds (Pb centres). It was demonstrated in many reports that compressive mechanical stress increases the density of Pb centres [10–12]. It was also observed, that increasing compressive mechanical stress exerted by the metal gates of different thickness increases the density of interface traps [13]. The samples investigated in this work were prepared on SiC, where Pb -centres are only one of several defects responsible for trap distribution. It is known from ab-initio calculations that broken Si and C bonds on the SiO2 and (1 1 1)beta-SiC or (0 0 0 1)alpha-SiC interfaces resemble the classical Pb -centres [8]. Both defects are amphoteric, creating known energy states at 0.25–0.3 eV above EV in the lower part of the band-gap, but not showing off in the upper part where they are dominated by distributions of carbon clusters. As it was noticed in Figs. 2 and 4, Dit decreases with increasing R (corresponding to the decreasing average compressive stress) at Et = 0.25–0.35 eV, which is the energy level where the Pb -centres in the upper part of the band-gap should be looked for. That is consistent with the reports on Pb -centre behaviour versus compressive stress. That effect can be better demonstrated in Fig. 6 where the points at the upper lines represent trap densities at Ec −0.25 eV versus R. The decrease in average stress, relevant to the change in R from 57 to 133, decreases the Dit from approximately 9 × 1011 to 2 × 1011 eV−1 cm−2 . It is more difficult to understand the increase of Dit at energy levels Et = 0.65 eV. It is known that in 3C–SiC large graphitic clusters create continuous distribution of traps at deeper energy levels [8,18]. However, little is known about the influence of mechanical stress on behaviour of those clusters. It can be concluded from Fig. 6,
Fig. 5. Dit energy distributions measured on WET/polySi sample for different gate contact sizes.
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Fig. 6. Dependence of Dit on R at two energy levels: Ec −0.25 eV (triangles) and Ec −0.65 V (squares) in PECVD-SiO2 /Ni sample (filled) and WET-SiO2 /Ni sample (empty).
where the points on the lower pair of lines represent trap densities at 0.65 eV, that increasing R, or in other words decreasing average mechanical stress, increases the Dit . The strength of the influence depends on the type of the oxide and it is much stronger in case of the WET oxide, where the Dit rises in the range of R by an order of magnitude, from 1 × 1010 to 2 × 1011 eV−1 cm−2 , than on PECVD oxide, where it increases only from 1 × 1011 to 2 × 1011 eV−1 cm−2 . It is known that mechanical stress influences atomic bond lengths, changing bond vibration frequency [10]. We may then expect as the result, the change in entropy of the trapping site, resulting in modification of the energy distributions of measured traps [14], but more experimental work is required to explain the mechanisms of the influence of mechanical stress on graphitic clusters regarding respective trap distributions. Another interesting observation is that the edge effect can be very weak or nonexistent in case of gates made from some materials. It can be explained by the mechanical properties of the gate materials versus underlying SiO2 . It was noted that the gate edge effect is weak in case of poly-silicon gates (see Fig. 7). It is known that thermal stresses depend on thermal expansion coefficients, and that the stress in a structure consisting of two different materials is proportional to the difference of thermal coefficients in each layer, assumed ideal adhesion at the interface. In case of nickel the thermal coefficient ˛Ni equals 12.5 × 10−6 K−1 [15], while in case of
Fig. 7. Dependence of Dit on R at two energy levels: Ec −0.25 eV (triangles) and Ec −0.65 V (squares) in PECVD-SiO2 /poly-Si sample (filled) and WET-SiO2 /poly-Si sample (empty).
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poly-silicon ˛poly-Si it is at least three times lower than in Ni and typically ranges between 0.5 × 10−6 K−1 and 4.1 × 10−6 K−1 [16]. Then, as the stress from the poly-silicon gate is more than three times lower than that from nickel and seven times from aluminium, the edge effect caused by poly-Si gates is much weaker than in case of those two metals. The dependence of Dit at 0.25 eV (upper lines) and at 0.65 eV (lower lines) on coefficient R in poly-Si gate samples and both SiO2 fabrication methods, shown in Fig. 7, is not as clear as in case of Ni and Al gates. With increasing R, the Dit is almost constant in case of both oxides at energy level of Pb -centres, what probably means that the change of stress relevant to the range of R is too weak to modify the density of those particular traps. The dependence of Dit on R at 0.65 eV is different for the PECVD and the WET oxides. In case of the PECVD oxide it is similar to what was observed on the Ni sample, while in case of the WET oxide that relationship is opposite. More experimental effort is needed to explain that behaviour in terms of internal stress distribution and trap properties. The lack of gate edge effect in case of Au samples can be explained by very poor adhesion of that metal to SiO2 . As it was demonstrated in [17], the films of gold deposited on Si:SiO2 structures and annealed at temperatures below 600 ◦ C have poor adhesion regardless of the annealing time. The film annealed at 600 ◦ C begin to show improved adhesion after 60 min anneal and can be rated as having good adhesion after 120 min. In our experiment Gold was not specially treated to improve adhesion. Since thermal stress in a two-layer structure is proportional to thermal expansion coefficients provided the layers do not slide one over another, the stress induced by Gold in SiO2 is much lower than it would result from the thermal expansion coefficients alone. 4. Conclusions Exploration of spacial distributions of density of traps under MOS capacitor gate was the main interest of this study. The gate edge effect, i.e. the dependence of Dit on R as the indication of difference in trap density at the centre of the gate and at its edges, was found. Interface trap energy distributions measured on capacitors having different ratio R, with different gate materials and two different methods of gate oxide preparation on SiC, demonstrated that the gate edge effect is strong in case of gate materials with high thermal expansion coefficient and good adhesion between gate and oxide layers, which was the case of Ni and Al on both PECVD and WET gate oxides. It was also shown that in case of gate materials with low expansion coefficient (poly-Si) or poor adhesion (Au) the dependence of Dit on R is weak or ambiguous. Based on assumption that the gate edge effect is caused by relieved compressive stress in the gate oxide at the edges of the gate, the decrease of Dit with increasing R could be attributed to the decrease of Pb -centres density due to decreasing average compressive stress. The change in the density of traps from graphitic clusters (deeper traps) resulting from the decrease of compressive stress
was also recorded. It was not possible, however, to explain that change in this study. Acknowledgement This work was partially supported by grant number N N515 244337 by the Polish Ministry of Science and Higher Education. References [1] A. Kudla, H.M. Przewlocki, L. Borowicz, D. Brzezinska, W. Rzodkiewicz, Photoelectrical measurements of the local value of the contact potential difference in the metal–insulator semiconductor (MIS) structures, Thin Solid Films 450/1 (2004) 203–206. [2] H.M. Przewlocki, A. Kudla, K. Piskorski, D. Brzezinska, Distributions of barrier heights, difference of effective contact potential, and local values of flat-band voltage in Al–SiO2 –Si and poly–Si–SiO2 –Si structures, Thin Solid Films 516/12 (2008) 4184–4189. [3] W. Rzodkiewicz, Elipsometric and Raman investigation of mechanical stress in dielectric and semiconductor substrate of an MOS structure, XLI Congress of Physicists, 4–9 September, Lublin, Poland, 2012, in press. [4] S. Dimitrijev, P. Jamet, Advances in SiC power MOSFET technology, Microelncs Reliab. 43 (2003) 225–233. [5] Y. Hijikata, et al., Composition analysis of SiO2 /SiC interfaces by electron spectroscopic measurements using slope-shaped oxide films, Appl. Surf. Sci. 184 (2001) 161–166. [6] I. Kodigala Subba Ramaiah, T.P. Bhat, J.K. Chow, E.F. Kim, D. Schubert, S. Johnstone, J. Akarca-Biyikli, Growth and characterization of SiC epitaxial layers on Si- and C-face 4H SiC substrates by chemical-vapor deposition, Appl. Phys. 98 (2005) 106–108. [7] C.W. Litton, D. Johnstone, S. Akarca-Biyikli, K.S. Ramaiah, I. Bhat, T.P. Chow, J.K. Kim, E.F. Schubert, Effect of C/Si ratio on deep levels in epitaxial 4H–SiC, Appl. Phys. Lett. 88 (2006) 121914. [8] V.V. Afanas’ev, F. Ciobanu, G. Pensl, A. Stesmans, in: W.J. Choyke, H. Matsunami, G. Pensl (Eds.), Silicon Carbide, Recent Major Results, Springer, Berlin, 2004. [9] E.H. Nicollian, J.R. Brews, MOS Physics and Technology, Wiley, New York, 1982. [10] C.H. Bjorkman, J.T. Fitch, G. Lucovsky, Correlation between midgap interface state density and thickness averaged oxide stress and strain at Si/SiO2 interfaces formed by thermal oxidation of Si, Appl. Phys. Lett. 56/20 (1990) 1983–1985. [11] D. Pierreux, A. Stesmans, R.J. Jaccodine, M.-T. Lin, T.J. Delph, Electron spin resonance study of the effect of applied stress during thermal oxidation of (1 1 1)Si on inherent Pb interface defects, Microelectron. Eng. 72 (2004) 76–80. [12] Chia-Nan Lin, Yi-Lin Yang, Wei-Ting Chen, Shang-Chih Lin, Kai-Chieh Chuang, Jenn-Gwo Hwu, Effect of strain–temperature stress on MOS structure with ultra-thin gate oxide, Microelectron. Eng. 85 (2008) 1915–1919. [13] Sang Ho Bae, Seung-Chul Song, KiSik Choi, G. Bersuker, G.A. Brown, Dim-Lee Kwong, Hun Lee Byoung, Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric, Microelectron. Eng. 83 (2006) 460–462. [14] B. Raeissi, J. Piscator, O. Engström, S. Hall, O. Buiu, M.C. Lemme, H.D.B. Gottlob, P.K. Hurley, K. Cherkaoui, H.J. Osten, High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy, Solid State Electron. 52 (2008) 1274–1279. [15] Y. Yang, H. Qiu, X. Chen, M. Yu, Characteristics of Ni films deposited on SiO2 /Si (1 0 0) and MgO (0 0 1) by direct current magnetron sputtering system with the oblique target, Appl. Surf. Sci. 255 (2009) 6226–6231. [16] H. Tada, A.E. Kumpel, R.E. Lathrop, J.B. Slanina, Thermal expansion coefficient of polycrystalline silicon and silicon dioxide thin films at high temperatures, J. Appl. Phys. 87/9 (2000) 4189–4193. [17] M.A. George, Q.C. Bao, I.W. Sorensen, W.S. Glaunsinger, Thermally induced changes in the resistance, microstructure, and adhesion of thin gold films on Si/SiO2 substrates, J. Vac. Sci. Technol. A 8/3 (1990) 1491–1497. [18] P. Borowicz, T. Gutt, T. Małachowski, M. Latek, Carbonic inclusions on SiC/SiO2 interface investigated with Raman Scattering, Diamond Relat. Mater. 20 (2011) 665–674.
Contents lists available at SciVerse ScienceDirect
Materials Science and Engineering B journal homepage: www.elsevier.com/locate/mseb
Short communication
Investigation of gate edge effect on interface trap density in 3C–SiC MOS capacitors T. Gutt a,∗ , T. Małachowski a , H.M. Przewłocki a , O. Engström a , M. Bakowski b , R. Esteve b a b
Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw, Poland Acreo AB, Electrum 236, SE-164 40 Kista, Sweden
a r t i c l e
i n f o
Article history: Received 21 September 2011 Received in revised form 21 February 2012 Accepted 3 March 2012 Available online 18 March 2012 Keywords: Silicon carbide Interface traps Metal-oxide-semiconductor structures Mechanical stress Edge effect
a b s t r a c t This paper reports on investigation of the gate edge effect on the interface trap density characteristics of 3C–SiC MOS capacitors fabricated using four different gate materials and two SiO2 oxide preparation methods. Non-uniform distribution of interface trap densities under the gate was demonstrated by the presence of the gate edge effect, i.e. the dependence of Dit (E) on the ratio of gate perimeter to its area. The strength of the gate effect in different gate/oxide material combinations was studied and it was found that it depends on gate thermal expansion coefficient and adhesion of the gate layer to the oxide layer. The Dit behaviour at shallow energy levels (0.25 eV) was attributed to the reaction of Pb -centres to mechanical stress. The behaviour of Dit at deeper levels was documented but could not be explained in this study. © 2012 Elsevier B.V. All rights reserved.
1. Introduction Spatial distribution of electrical parameter values over the gate area of MOS devices is essential for understanding the effects on device operation of the shrinking device dimensions and application of new materials and/or new processing procedures. As it was demonstrated in [1,2], such MOS device parameters as flat-band voltage VFB , effective contact potential difference MS , or potential barrier height at gate-dielectric interface EBG are not uniformly distributed within the gate area. Using a photoelectric measurement technique with a UV light beam of a 0.3 mm diameter, which was much smaller than the investigated MOS capacitor gate dimensions, it was possible to scan the gate and determine the MS and EBG local values. It was shown that the spatial distributions of those parameters had a dome-like shape with the maximum in the centre of the gate. The difference between parameter values in the centre and at the edges of the structure was considerably large, hence it was called the gate edge effect. The results presented in that study also showed that the most significant manifestation of the edge effect was found in devices with aluminium gates, while it was not detected in case of poly-Si gates [1,2]. The edge effect can also be observed on electrically measured parameters. When flat-band voltage VFB is measured on a series of neighbouring capacitors having different sizes, the measured
∗ Corresponding author. Tel.: +48 22 5487857; mobile: +48 694748104. E-mail address: [email protected] (T. Gutt). 0921-5107/$ – see front matter © 2012 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2012.03.007
VFB values differ depending on the gate size. The detailed analysis proved that the measured VFB depends on a geometrical parameter R which is the ratio of the gate perimeter to the gate area. The R parameter can be understood as a measure of edge region contribution to the whole area of the device [1,2]. In order to determine the factors causing the gate edge effect the distribution of mechanical stress in a MOS structure was investigated. It was demonstrated in [3] using micro-Raman shift measurements, that a compressive stress is present in the gate oxide under the gate, but that stress is relieved locally at the edge of the gate, where it can even change its sign to tensile. The distributions measured in that study were explained in the following way. The metal layer deposited on top of the oxide contracts as it is cooled down and stresses the underlying oxide due to a large difference in thermal expansion coefficients of both materials. During patterning process in which the gate features are defined, the metal layer is discontinued and the compressive stress in the oxide decreases in the places where discontinuity occurs. All those facts prove that the spacial distribution of important MOS electrical parameters under the gate caused by the distribution of mechanical stress in the gate insulator cannot be neglected. Consequently, it is interesting to investigate the influence of the mechanical stress distribution on other electrical characteristics of the MOS system. Interface traps are one of the most important factors determining the quality of the MOS devices. Traps are the major cause of carrier mobility degradation in SiC MOSFETs. The density of traps in SiC is much higher than in silicon due to much more complicated interface physics and chemistry promoting a variety of
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Fig. 1. Schematic picture of the gate stack and the test structure with gate contact sizes.
defects. Although the nature of those defects and their charge trapping properties are widely documented in the literature, mostly with regard to oxygen vacancies, Pb -centres (dangling bonds) or carbon clusters [4–8], little is known about their spacial distributions and dependency on mechanical stress. The goal of this study was to find out whether the gate edge effect influences interface trap density characteristics in 3C–SiC:SiO2 capacitors, and whether the thermal stress distribution in the area of the gate modifies trap properties at semiconductor–insulator interface. 2. Experimental details The investigation was carried out using 3C–SiC MOS capacitors with four different gate materials and two different technological variants of gate SiO2 layers. Two different methods of SiO2 deposition were used by ACREO AB: wet thermal oxidation (in 1 h at 1150 ◦ C) and PECVD (plasma enhanced chemical vapour deposition) followed by annealing in wet oxygen at 950 ◦ C for 3 h, on two identical 3 in. wafers with 10 m n-type (2–3 × 1015 cm−3 ) 3C–SiC (0 0 1) epi-layer provided by Hoya. The thickness of each oxide was 60 nm. Then, both wafers were sawed into 4 quadrants each and MOS capacitors with gate contacts made of nickel, aluminium, gold and poly-silicon (+TiW), were fabricated on each quadrant respectively. The diameters of the circular gate contacts used in this experiment were 0.7 mm (denoted as LL), 0.6 mm (denoted as L), 0.5 mm (denoted as M), 0.4 mm (denoted as S), and 0.3 mm (denoted as SS). The samples are referred to in the paper as PECVD/Ni, Au, Al, polySi, and WET/Ni, Au, Al, polySi, respectively. The schematic picture of the investigated gate stack, showing the structural concept and the materials used is shown in Fig. 1. The electrical measurements were done at the Institute of Electron Technology, using Agilent 4294A impedance analyzer. The relevant gate voltage range and surface potential mapping were established using C–V measurements at room temperature based on the comparison of the experimental and theoretical C–V characteristics. The bulk doping concentration ND used for theoretical C–V calculation was established from C−2 –V characteristics. The conductance method was used to calculate trap density vs. energy distributions Dit (Et ) in the way described in [9]. The procedure consisted in measuring MOS capacitor admittance spectra Y(VG , ω) = G(VG , ω) + jωC(VG , ω) in frequency range f = /2 = 100 Hz to 1 MHz and calculating interface conductance characteristics Gp / − from the measured G(VG , ) characteristics.
Fig. 2. Dit energy distributions measured on PECVD-SiO2 /Ni sample for different gate contact sizes.
diameter (i.e. increasing R – the ratio of gate perimeter to the area of the contact) and increases at deeper states (Ec − Et > 0.5 eV). The dependence of the shape of the Dit distributions vs. R is the clear evidence of the gate edge effect in this sample. In contrast with the distributions measured on poly-Si gates over the PECVD oxide, presented in Fig. 3, the dependence of Dit on the gate size or the coefficient R is considerably weaker at shallow energy levels and increasing at deeper states. It is interesting that the dependence of Dit on R in WET oxide/nickel gate samples is very similar to that of the PECVD/nickel gate, with respect to the direction of Dit changes with coefficient R, as can be seen in Fig. 4. In case of WET/poly-silicon gate samples the Dit distributions presented in Fig. 5 change with R in the opposite direction compared with PECVD/poly-Si samples shown in Fig. 3. The Dit distributions measured on capacitors with Al gates on both oxide types are similar to those with Nickel gates and strongly depend on R. Interestingly, the Dit distributions measured on capacitors with Au gates very weakly depend on R in which they are similar to those measured on poly-Si gate devices. There are two issues which have to be addressed with regard to the results presented above: the origin of traps responsible for the dependence of Dit on R, as shown in Figs. 2 and 4; and the factors inhibiting the edge effect in shallow traps in case of gates made from some materials, as shown in Figs. 3 and 5. As it was discussed in Section 1, the thermal stress in the gate oxide is locally relieved at the gate edge, creating a spacial distribution of stress under the gate. The influence of mechanical stress on interface defects was widely investigated with regard
3. Results and discussion The presence of the gate edge effect in the interface traps energy distributions Dit (E) is an indicator of the influence of the thermal stress distribution at the gate-SiO2 interface and it will be discussed first. The Dit energy distributions measured on nickel gates over the PECVD oxide are shown in Fig. 2. It can be easily noticed that the Dit decreases at shallow states (Ec − Et < 0.5 eV) with decreasing gate
Fig. 3. Dit energy distributions measured on PECVD-SiO2 /polySi sample for different gate contact sizes.
T. Gutt et al. / Materials Science and Engineering B 177 (2012) 1327–1330
Fig. 4. Dit energy distributions measured on WET-SiO2 /Ni sample for different gate contact sizes.
to Si:SiO2 system, where the dominant type of defects were dangling bonds (Pb centres). It was demonstrated in many reports that compressive mechanical stress increases the density of Pb centres [10–12]. It was also observed, that increasing compressive mechanical stress exerted by the metal gates of different thickness increases the density of interface traps [13]. The samples investigated in this work were prepared on SiC, where Pb -centres are only one of several defects responsible for trap distribution. It is known from ab-initio calculations that broken Si and C bonds on the SiO2 and (1 1 1)beta-SiC or (0 0 0 1)alpha-SiC interfaces resemble the classical Pb -centres [8]. Both defects are amphoteric, creating known energy states at 0.25–0.3 eV above EV in the lower part of the band-gap, but not showing off in the upper part where they are dominated by distributions of carbon clusters. As it was noticed in Figs. 2 and 4, Dit decreases with increasing R (corresponding to the decreasing average compressive stress) at Et = 0.25–0.35 eV, which is the energy level where the Pb -centres in the upper part of the band-gap should be looked for. That is consistent with the reports on Pb -centre behaviour versus compressive stress. That effect can be better demonstrated in Fig. 6 where the points at the upper lines represent trap densities at Ec −0.25 eV versus R. The decrease in average stress, relevant to the change in R from 57 to 133, decreases the Dit from approximately 9 × 1011 to 2 × 1011 eV−1 cm−2 . It is more difficult to understand the increase of Dit at energy levels Et = 0.65 eV. It is known that in 3C–SiC large graphitic clusters create continuous distribution of traps at deeper energy levels [8,18]. However, little is known about the influence of mechanical stress on behaviour of those clusters. It can be concluded from Fig. 6,
Fig. 5. Dit energy distributions measured on WET/polySi sample for different gate contact sizes.
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Fig. 6. Dependence of Dit on R at two energy levels: Ec −0.25 eV (triangles) and Ec −0.65 V (squares) in PECVD-SiO2 /Ni sample (filled) and WET-SiO2 /Ni sample (empty).
where the points on the lower pair of lines represent trap densities at 0.65 eV, that increasing R, or in other words decreasing average mechanical stress, increases the Dit . The strength of the influence depends on the type of the oxide and it is much stronger in case of the WET oxide, where the Dit rises in the range of R by an order of magnitude, from 1 × 1010 to 2 × 1011 eV−1 cm−2 , than on PECVD oxide, where it increases only from 1 × 1011 to 2 × 1011 eV−1 cm−2 . It is known that mechanical stress influences atomic bond lengths, changing bond vibration frequency [10]. We may then expect as the result, the change in entropy of the trapping site, resulting in modification of the energy distributions of measured traps [14], but more experimental work is required to explain the mechanisms of the influence of mechanical stress on graphitic clusters regarding respective trap distributions. Another interesting observation is that the edge effect can be very weak or nonexistent in case of gates made from some materials. It can be explained by the mechanical properties of the gate materials versus underlying SiO2 . It was noted that the gate edge effect is weak in case of poly-silicon gates (see Fig. 7). It is known that thermal stresses depend on thermal expansion coefficients, and that the stress in a structure consisting of two different materials is proportional to the difference of thermal coefficients in each layer, assumed ideal adhesion at the interface. In case of nickel the thermal coefficient ˛Ni equals 12.5 × 10−6 K−1 [15], while in case of
Fig. 7. Dependence of Dit on R at two energy levels: Ec −0.25 eV (triangles) and Ec −0.65 V (squares) in PECVD-SiO2 /poly-Si sample (filled) and WET-SiO2 /poly-Si sample (empty).
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poly-silicon ˛poly-Si it is at least three times lower than in Ni and typically ranges between 0.5 × 10−6 K−1 and 4.1 × 10−6 K−1 [16]. Then, as the stress from the poly-silicon gate is more than three times lower than that from nickel and seven times from aluminium, the edge effect caused by poly-Si gates is much weaker than in case of those two metals. The dependence of Dit at 0.25 eV (upper lines) and at 0.65 eV (lower lines) on coefficient R in poly-Si gate samples and both SiO2 fabrication methods, shown in Fig. 7, is not as clear as in case of Ni and Al gates. With increasing R, the Dit is almost constant in case of both oxides at energy level of Pb -centres, what probably means that the change of stress relevant to the range of R is too weak to modify the density of those particular traps. The dependence of Dit on R at 0.65 eV is different for the PECVD and the WET oxides. In case of the PECVD oxide it is similar to what was observed on the Ni sample, while in case of the WET oxide that relationship is opposite. More experimental effort is needed to explain that behaviour in terms of internal stress distribution and trap properties. The lack of gate edge effect in case of Au samples can be explained by very poor adhesion of that metal to SiO2 . As it was demonstrated in [17], the films of gold deposited on Si:SiO2 structures and annealed at temperatures below 600 ◦ C have poor adhesion regardless of the annealing time. The film annealed at 600 ◦ C begin to show improved adhesion after 60 min anneal and can be rated as having good adhesion after 120 min. In our experiment Gold was not specially treated to improve adhesion. Since thermal stress in a two-layer structure is proportional to thermal expansion coefficients provided the layers do not slide one over another, the stress induced by Gold in SiO2 is much lower than it would result from the thermal expansion coefficients alone. 4. Conclusions Exploration of spacial distributions of density of traps under MOS capacitor gate was the main interest of this study. The gate edge effect, i.e. the dependence of Dit on R as the indication of difference in trap density at the centre of the gate and at its edges, was found. Interface trap energy distributions measured on capacitors having different ratio R, with different gate materials and two different methods of gate oxide preparation on SiC, demonstrated that the gate edge effect is strong in case of gate materials with high thermal expansion coefficient and good adhesion between gate and oxide layers, which was the case of Ni and Al on both PECVD and WET gate oxides. It was also shown that in case of gate materials with low expansion coefficient (poly-Si) or poor adhesion (Au) the dependence of Dit on R is weak or ambiguous. Based on assumption that the gate edge effect is caused by relieved compressive stress in the gate oxide at the edges of the gate, the decrease of Dit with increasing R could be attributed to the decrease of Pb -centres density due to decreasing average compressive stress. The change in the density of traps from graphitic clusters (deeper traps) resulting from the decrease of compressive stress
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