- Email: [email protected]
SILC in MOS capacitors with poly-Si and poly-Si0.7Ge0.3 gate material
Micr~l~troni~
Enginee~ng 48 ( 1999) 4 15-4 18 www.elsevier.nl/locate/mee
SILC in MOS Capacitors with Poly-Si and Poly-Sb.TGeo.3Gate Material V.E. Houtsmaa, J. Hollemana, C. Salma and P. H. Woerleeavb aMESA Research Institute,
University of Twente, P.O.Box 217, 7500 AE Ens&de,
bPhilips research Laboratories,
The Netherlands.
Prof. Holstlaan 4, Eindhoven, The Netherl~~.
In this paper the DC-SILC characteristics of n+ and p+ poly-Si and poly-SiGe MOS capacitors are studied for substrate(+V,) and gate-injection(-V,) conditions. P+ and n+-gates with poly silicon (poly-Si) and poly Silicon-Germanium fpoly Si-o.tGeo.3) were used to study the influence of the gate workfunction on gate current and SILC currents. For n+ poly-SiGe, reduced poly depletion and no sign&ant difference in SILC characteristics compared to n+ poly-Si gate devices is observed. For p+ gate devices asymmetric SILC and reduced SILC for poly-SiGe is observed.
1. Introduction
Stress Induced Leakage Current (SILC) limits the scaling of the gate oxide thickness for nonvolatile memories. SILC was studied mainly for n-doped poly silicon (poly-Si) gate materid up till now [1,2]. Recently, for p+-gate devices a diierent conduction mechanism under gate injection conditions (-V,) [3-51, asymmetric SILC (gate bias polarity) and reduced SILC for p+ polySb.7Geo.s was observed [S]. However, the impact of poly-Sil-,Ge, on the SILC characteristics of n+-gate devices has not been studied yet. In this paper the DC-SILC characteristics of n+ and p+ poly-Si and poly-SiCe MOS capacitors are studied for substrate{+V~) and ga~inj~tion(-V~) conditions and a detailed comparison is made. 2. Experimental
Procedures
PMOS and NMOS capacitors were fabricated on 10 &cm n-type and p-type silicon substrates, respectively. A high quality gate oxide with 5.6 nm thickness (ellipsometric) was grown in diluted dry oxygen. Undoped poly-Si and polySio.TGw.3 layers (200 nm thick) were deposited using a LPCVD system. Gate doping was done by a 20 keV, 2.5-10” crnb2 BF: or 40 keV, 5.0.1015 cmw2 As+ implant followed by an anneal at 850°C for 30 minutes (p+-gate) or a rapid thermal anneal (RTA) at 1OOO’Cfor 20 seconds in Nz ambient (nf-gate). Electrical stress 0167-93~7/99/$
has been applied on A=~4.0&10-~cmq2 (p+-gate) and A=3.53=10w3 cmm2 (n+-gate) MOS capacitors using constant current stress conditions of -fO.l mA/cm2. DC-SILC was measured J .¶treaain a similar way as in [l]. The oxide electric field was determined by integration of the quasi-static capacitance-voltage curves as in
3. Experimental
results
Quasi-Static C-V curves for capacitors with p+-poly Si and poly-SiGe gate are shown in Fig. 1. A shift of the flatband voltage from 0.82V (poly-Si) to 0.6OV (poly-SiGe) agrees well with previous data [3,6]. It is caused by a shift in valence band position [S]. Note that the gate depletion is acceptable for both devices. Fig. 2 shows the C-V curves for capacitors with n+-poly Si and poly-SiGe gate material. Note that since for n+ gate devices the workfunction difference is negligible between poly-Si and poly-SiGe, the flatband voltage is the same (-0.98V). Also it is evident that the gate depletion of the poly-SiGe devices is significantly reduced compared to the poly-Si reference devices, as was also found in [7]. Fig. 3 shows the J-E,, characteristics of unstressed poly-Si and poly-SiGe capacitors for substrate- (+V,) and gate-injection (-V,) conditions. For nf-gate devices the J-E,, characteristics are symmetric with -V, and +V, injection conditions. However, for p+-gate devices,
- see front matter 0 1999 Elsevier Science B.V All rights reserved.
V. Houtsma et al. / Microelectronic Engineering 48 (1999) 415-418
416
60O
6OO
~
A" 500 E ~400
300 2OO 100
Vfb,Si-=0.82 V Vfb,SiGe--0.60 V
I I
p+ Poly-Si
I
------ p+ Poly-SiGe -3
400 Vfb,Si= -0.98 V Vtb'SiGe= -0.98 V
.~ 300 L; 200
I / ~
0
-2
500
-l 0 1 Gate Voltage [V]
n+ Poly-Si - - - - n+ Poly-SiGe
100 2
3
-3
-2
I -1 0 Gate Voltage [V]
2
3
Figure 1. Quasi-static C-V curves for p+-poly Si and p+- poly SiGe MOS capacitors. Dashed line poly-SiGe, solid line poly-Si.
Figure 2. Quasi-static C-V curves for n+-poly Si and n +- poly SiGe MOS capacitors. Dashed line poly-SiGe, solid line poly-Si.
the onset of conduction for -Vg occurs at significantly higher oxide field (~1.5x) than for +Vg condition. Note the difference for p+-gate devices between poly-Si and poly-SiGe at -Vg. For +Vg the J-Eox curve can be fitted with the standard Fowler-Nordheim (FN) expression with barrier height of 3.2 eV. For -Vg a fit with a FN expression for p+-gate devices can not be obtained, unless unphysical fit parameters are used. The gate, substrate and diode currents measured on gate-controlled diodes are shown in Fig. 4. For -Vg conditions the substrate and diode currents are larger than the gate current (right axis Fig 4, I,ub > 2x Igate). The larger substrate current indicates that an avalanche process is taking place. This is not expected when hole tunneling from the substrate dominates the gate current. It appears that gate current at -Vg for p+ gate devices is caused by electron injection from the gate. There are two possible mechanisms for electron injection from the gate. Firstly, tunneling of minority carriers(MCT) from the conduction band could occur for low active gate doping, since gate depletion increases the electron surface concentration. A second possibility is valence band tunneling (VBT). Gate currents are either influenced by the workfunction for valence band tunneling or
the bandgap of the gate material for MCT mechanism. This will influence the SILC characteristics, stress experiments are discussed below. In Fig. 5 the J-Eoz characteristics of n + polySi and poly-SiGe gate devices are shown for -Vg and +Vg after various stress intervals. From this it can be observed that no significant difference between n + poly-Si and poly-SiGe gate devices is observed for +Vg and -Vg injection conditions. Both SILC currents can be described well by a FN expression with an effective barrier of 0.9 eV [1,2]. In Fig. 6 the J-Eoz characteristics of p+ poly-Si and poly-SiGe gate devices are shown after various stress intervals. For -Vg injection the SILC becomes apparent at much higher Eoz, furthermore the field dependence is different from that at +Vg. At comparable oxide field the SILC is orders of magnitude smaller for -Vg stress than for +Vg stress. Hence there is a strong asymmetry of the SILC currents for p+ gate devices with stress polarity. This is different from n +poly gate devices where SILC is almost symmetric with gate polarity. For +Vg the SILC current after stress follows a FN dependence with effective barrier height of 0.9 eV, which is similar to the n+-poly devices. For gate injection SILC can not be described by an FN expression with fixed bar-
417
V. Houtsma et al. I Microelectronic Engineering 48 (1999) 415-418 I0-3
&-- 10-2 E
I P°Iy'Si I [.......... Poly-SiGe[
~ 10.4
~ 10~
'-.\ \-'
/
/ n+-polye_.~ p+-poly/
<
Igau: > 0 Idiode < 0
[u - -
.\,
.............
....
Iga~ < 0 Idiotic< 0
/
..........
•~ lO-7 ,
=
'
< .~ 10-s
4 ]
• \
. L__/l'ubsl:rate
;
2 "o
"
|,~'~=
10-u
i . ~-~ll+-poly
';odo
/,
,,....
1043
10-to
-10
-8
-6 -4 -2 0 2 4 6 Oxide Field Strength [MV/cm]
8
lO
12 10 8
6
4 2 0 -2 -4 -6 - 8 - 1 0 - 1 2 Gate Voltage [V]
Figure 3. J-Eoz measurements of unstressed polySi and poly-SiGe gate MOS capacitors. Dashed line poly-SiGe, solid line poly-Si.
Figure 4. Gate, substrate and diode currents of p+-poly Si gate-controlled diodes with 7nm oxide thickness as a function of gate voltage.
rier height, variations in shape occur with stress time. An (unphysical) FN fit of the SILC current results in a barrier height around 2 eV indicating a much stronger field dependence. It has been observed that SILC is proportional to the neutral trap density created during stress [1,2] and models based on inelastic trap-assisted-tunneling (TAT) are used to describe SILC [8]. The observed bias asymmetry in SILC for p+-gate devices could be related to a larger tunneling barrier height for TAT or different position of the traps for -V a stress conditions. For +V 0 conditions the SILC current for p+ poly-SiGe gates is strongly reduced compared to the p+ poly-Si reference devices. The reduced SILC of poly-SiGe devices for +Va stress could be the result of a reduced Boron incorporation in the gate oxide. A larger solid solubility and smaller diffusivety of Boron in poly-SiGe lead to a reduced incorporation of Boron in the dielectric [3]. Hence a lower neutral trap density and reduced SILC for poly-SiGe gates is expected [1,2,9].
injection(-Va) conditions. For n + poly-SiGe no significant difference in SILC characteristics compared to n + poly-Si is observed. For p+ gate devices, both the workfunction of the gate material and Boron penetration into the gate oxide strongly influence the SILC effect. Boron-doped poly-SiGe may be a very interesting gate material due to low SILC at +Va and better gate oxide quality.
4. Conclusions In summary, the DC-SILC characteristics of n + and p+ poly-Si and poly-SiGe MOS capacitors were studied under substrate(+V o) and gate-
REFERENCES 1. J. De Blauwe et al. "A new quantitative model to predict SILC-related disturb characteristics in Flash E2pROM devices", IEDM Tech.Digest, 1996 pp. 343-346. 2. D . J . DiMaria et aL, "Mechanism for stressinduced leakage currents in thin silicon dioxide films", J. Appl. Phys., no. 6(78) 1995 pp. 3883-3894. 3. C. Salm et al. " G a t e Current and Oxide Reliability in p+ Poly MOS Capacitors with PolySi and Poly-Ge0.aSi0.7 Gate Material", Electron Dev. Lett. vol 19(7) 1998 pp. 213-215. 4. J. -L. Ogier et al. " O n the Polarity Dependence of Oxide Breakdown in MOS-Devices with n + and p+ Polysilicon Gate", Proc. ESSDERC'96, 1996 pp. 763-766.
4t8
V. Houtsma et al. I Microelectronic Engineering 48 (1999) 4 1 5 - 4 1 8 10.6
10-6
- Jstress
+ Jstress
~' \'\.,
initial IV - - - - 100 P'C/cm2 ----- I mCtcm2 . . . . 10 mC/cm2
~'~ 10-8
\ ~', t"..."\':,,
...... lOOmC/cm2 ..... 0.5C/cm2
--tin 10.9
~'x
/f/ l ,//" ."l /"/ " t /I ......,4
'~.
10-7
x .. \,~'\ ......",\
/i /7
~
/i/
....... I C/cm2
lO.S
~X~
initial IV I - - - - tO0 laC']cm2: - - - lmC/cm2
+ Jstress
I . . . . tO mC/cm2 I .......... I00 mC/cm2
¢ .~~ '
I.....
/
:.!;~
o.5 C / c m 2
I,......
/ /
,..;.*(.I
~::.\ ........~>"?~.%.. p+ Poly-Si .~/',/:...''i~]x.../
lO-lO
/,,'J/;7
10-11 -7
-6
-5
-4
lO-6
- Jstress
¢~ 10-8
~k
10-9
10-ii
10-7
10-7
i7
~;"," '7t\5\---'-+ n Poly-S-"----T.(/:).{" ,4
lO-iO
- Jstre.~,s \
-3
-2 2 3 Eox [MV/cm]
--
initial IV
\
I- -
~. ~\
----- 1 mC/cm2 .... 10 mC/cm2 100 mC/cm2
~t "~\.
~" --~a 10"9
~~'xx:',.
4
5
6
7
+ Jstress
i ./
l°°uc/cm2
]/
10-6
-6
-5 3 4 Eox [MWcm]
initial IV 1oo ~,C/cm2 I mC,/cm2 . . . . 10 mC/cm2 .......... 100 mC/cm2 . . . . 0.5 C,)cm2 '...x\. ...... 1 C/cm2
--ao 10-9 ,-.n
I C/cm2
-7
tress
lO.S
//(:" / ,// • j /)' . / t~\',x X ......"\~,~\ n +Poly-SiGe 1!/,' : / /] / -..,:, /I/
1040
-8
10-7
// /7 If'l
I .... 0"5 C/cm2
I', "."x/, ',, ix '
-9
+
.
p Voly-SiGe
10"10
'~
5
6
+ Jstress
/ /
/ / ] .1 ([
/';, ~.:~/
: : " ~
10-11
10,-li -7
-6
-5
-4
-3
-2 2 3 Eox [MV/cm]
4
5
6
7
-9
-8
-7
-6
-5 3 4 Eox [MY/era]
5
6
7
Figure 5. J-Eo~ curves before and after stress (100#C/cm 2 to 1C/cm 2) for n + poly-Si and polySiGe gate material
Figure 6. J-Eox curves before and after stress (100#C/cm 2 to 1C/cm 2) for p+ poly-Si and polySiGe gate material
5. V.E. Houtsma et al. "Stress-Induced Leakage Current in p+ Poly MOS Capacitors with Poly-Si and Poly-Sio.TGe0.3 Gate Material", accepted for publication in Electron Dev. Lett. 6. T. -J. King et al. "A PolycrystallineSil_xGex-Gate CMOS Technology", IEDM Tech.Digest, 1990 pp. 253-256. 7. W. -C. Lee et al. "Observation of Reduced Poly-Gate Depletion Effect for PolySio.8Ge0.2-Gated NMOS Devices", Elec. and Solid-State Lett. vol 1(1) 1998 pp. 558-59. 8. A.I. Chou et al. "Modeling of stress-induced leakage current in ultrathin oxides with the
trap-assisted tunneling mechanism", Appl. Phys. Lett vol 70(25) 1997 pp. 3407-3409. . C. Jahan et al. "Investigation of StressInduced Leakage Current in CMOS Structures with Ultra-Thin Gate Dielectrics", Microelec. Reliab. vol 37(10/11) 1997 pp. 15291532.
Enginee~ng 48 ( 1999) 4 15-4 18 www.elsevier.nl/locate/mee
SILC in MOS Capacitors with Poly-Si and Poly-Sb.TGeo.3Gate Material V.E. Houtsmaa, J. Hollemana, C. Salma and P. H. Woerleeavb aMESA Research Institute,
University of Twente, P.O.Box 217, 7500 AE Ens&de,
bPhilips research Laboratories,
The Netherlands.
Prof. Holstlaan 4, Eindhoven, The Netherl~~.
In this paper the DC-SILC characteristics of n+ and p+ poly-Si and poly-SiGe MOS capacitors are studied for substrate(+V,) and gate-injection(-V,) conditions. P+ and n+-gates with poly silicon (poly-Si) and poly Silicon-Germanium fpoly Si-o.tGeo.3) were used to study the influence of the gate workfunction on gate current and SILC currents. For n+ poly-SiGe, reduced poly depletion and no sign&ant difference in SILC characteristics compared to n+ poly-Si gate devices is observed. For p+ gate devices asymmetric SILC and reduced SILC for poly-SiGe is observed.
1. Introduction
Stress Induced Leakage Current (SILC) limits the scaling of the gate oxide thickness for nonvolatile memories. SILC was studied mainly for n-doped poly silicon (poly-Si) gate materid up till now [1,2]. Recently, for p+-gate devices a diierent conduction mechanism under gate injection conditions (-V,) [3-51, asymmetric SILC (gate bias polarity) and reduced SILC for p+ polySb.7Geo.s was observed [S]. However, the impact of poly-Sil-,Ge, on the SILC characteristics of n+-gate devices has not been studied yet. In this paper the DC-SILC characteristics of n+ and p+ poly-Si and poly-SiCe MOS capacitors are studied for substrate{+V~) and ga~inj~tion(-V~) conditions and a detailed comparison is made. 2. Experimental
Procedures
PMOS and NMOS capacitors were fabricated on 10 &cm n-type and p-type silicon substrates, respectively. A high quality gate oxide with 5.6 nm thickness (ellipsometric) was grown in diluted dry oxygen. Undoped poly-Si and polySio.TGw.3 layers (200 nm thick) were deposited using a LPCVD system. Gate doping was done by a 20 keV, 2.5-10” crnb2 BF: or 40 keV, 5.0.1015 cmw2 As+ implant followed by an anneal at 850°C for 30 minutes (p+-gate) or a rapid thermal anneal (RTA) at 1OOO’Cfor 20 seconds in Nz ambient (nf-gate). Electrical stress 0167-93~7/99/$
has been applied on A=~4.0&10-~cmq2 (p+-gate) and A=3.53=10w3 cmm2 (n+-gate) MOS capacitors using constant current stress conditions of -fO.l mA/cm2. DC-SILC was measured J .¶treaain a similar way as in [l]. The oxide electric field was determined by integration of the quasi-static capacitance-voltage curves as in
3. Experimental
results
Quasi-Static C-V curves for capacitors with p+-poly Si and poly-SiGe gate are shown in Fig. 1. A shift of the flatband voltage from 0.82V (poly-Si) to 0.6OV (poly-SiGe) agrees well with previous data [3,6]. It is caused by a shift in valence band position [S]. Note that the gate depletion is acceptable for both devices. Fig. 2 shows the C-V curves for capacitors with n+-poly Si and poly-SiGe gate material. Note that since for n+ gate devices the workfunction difference is negligible between poly-Si and poly-SiGe, the flatband voltage is the same (-0.98V). Also it is evident that the gate depletion of the poly-SiGe devices is significantly reduced compared to the poly-Si reference devices, as was also found in [7]. Fig. 3 shows the J-E,, characteristics of unstressed poly-Si and poly-SiGe capacitors for substrate- (+V,) and gate-injection (-V,) conditions. For nf-gate devices the J-E,, characteristics are symmetric with -V, and +V, injection conditions. However, for p+-gate devices,
- see front matter 0 1999 Elsevier Science B.V All rights reserved.
V. Houtsma et al. / Microelectronic Engineering 48 (1999) 415-418
416
60O
6OO
~
A" 500 E ~400
300 2OO 100
Vfb,Si-=0.82 V Vfb,SiGe--0.60 V
I I
p+ Poly-Si
I
------ p+ Poly-SiGe -3
400 Vfb,Si= -0.98 V Vtb'SiGe= -0.98 V
.~ 300 L; 200
I / ~
0
-2
500
-l 0 1 Gate Voltage [V]
n+ Poly-Si - - - - n+ Poly-SiGe
100 2
3
-3
-2
I -1 0 Gate Voltage [V]
2
3
Figure 1. Quasi-static C-V curves for p+-poly Si and p+- poly SiGe MOS capacitors. Dashed line poly-SiGe, solid line poly-Si.
Figure 2. Quasi-static C-V curves for n+-poly Si and n +- poly SiGe MOS capacitors. Dashed line poly-SiGe, solid line poly-Si.
the onset of conduction for -Vg occurs at significantly higher oxide field (~1.5x) than for +Vg condition. Note the difference for p+-gate devices between poly-Si and poly-SiGe at -Vg. For +Vg the J-Eox curve can be fitted with the standard Fowler-Nordheim (FN) expression with barrier height of 3.2 eV. For -Vg a fit with a FN expression for p+-gate devices can not be obtained, unless unphysical fit parameters are used. The gate, substrate and diode currents measured on gate-controlled diodes are shown in Fig. 4. For -Vg conditions the substrate and diode currents are larger than the gate current (right axis Fig 4, I,ub > 2x Igate). The larger substrate current indicates that an avalanche process is taking place. This is not expected when hole tunneling from the substrate dominates the gate current. It appears that gate current at -Vg for p+ gate devices is caused by electron injection from the gate. There are two possible mechanisms for electron injection from the gate. Firstly, tunneling of minority carriers(MCT) from the conduction band could occur for low active gate doping, since gate depletion increases the electron surface concentration. A second possibility is valence band tunneling (VBT). Gate currents are either influenced by the workfunction for valence band tunneling or
the bandgap of the gate material for MCT mechanism. This will influence the SILC characteristics, stress experiments are discussed below. In Fig. 5 the J-Eoz characteristics of n + polySi and poly-SiGe gate devices are shown for -Vg and +Vg after various stress intervals. From this it can be observed that no significant difference between n + poly-Si and poly-SiGe gate devices is observed for +Vg and -Vg injection conditions. Both SILC currents can be described well by a FN expression with an effective barrier of 0.9 eV [1,2]. In Fig. 6 the J-Eoz characteristics of p+ poly-Si and poly-SiGe gate devices are shown after various stress intervals. For -Vg injection the SILC becomes apparent at much higher Eoz, furthermore the field dependence is different from that at +Vg. At comparable oxide field the SILC is orders of magnitude smaller for -Vg stress than for +Vg stress. Hence there is a strong asymmetry of the SILC currents for p+ gate devices with stress polarity. This is different from n +poly gate devices where SILC is almost symmetric with gate polarity. For +Vg the SILC current after stress follows a FN dependence with effective barrier height of 0.9 eV, which is similar to the n+-poly devices. For gate injection SILC can not be described by an FN expression with fixed bar-
417
V. Houtsma et al. I Microelectronic Engineering 48 (1999) 415-418 I0-3
&-- 10-2 E
I P°Iy'Si I [.......... Poly-SiGe[
~ 10.4
~ 10~
'-.\ \-'
/
/ n+-polye_.~ p+-poly/
<
Igau: > 0 Idiode < 0
[u - -
.\,
.............
....
Iga~ < 0 Idiotic< 0
/
..........
•~ lO-7 ,
=
'
< .~ 10-s
4 ]
• \
. L__/l'ubsl:rate
;
2 "o
"
|,~'~=
10-u
i . ~-~ll+-poly
';odo
/,
,,....
1043
10-to
-10
-8
-6 -4 -2 0 2 4 6 Oxide Field Strength [MV/cm]
8
lO
12 10 8
6
4 2 0 -2 -4 -6 - 8 - 1 0 - 1 2 Gate Voltage [V]
Figure 3. J-Eoz measurements of unstressed polySi and poly-SiGe gate MOS capacitors. Dashed line poly-SiGe, solid line poly-Si.
Figure 4. Gate, substrate and diode currents of p+-poly Si gate-controlled diodes with 7nm oxide thickness as a function of gate voltage.
rier height, variations in shape occur with stress time. An (unphysical) FN fit of the SILC current results in a barrier height around 2 eV indicating a much stronger field dependence. It has been observed that SILC is proportional to the neutral trap density created during stress [1,2] and models based on inelastic trap-assisted-tunneling (TAT) are used to describe SILC [8]. The observed bias asymmetry in SILC for p+-gate devices could be related to a larger tunneling barrier height for TAT or different position of the traps for -V a stress conditions. For +V 0 conditions the SILC current for p+ poly-SiGe gates is strongly reduced compared to the p+ poly-Si reference devices. The reduced SILC of poly-SiGe devices for +Va stress could be the result of a reduced Boron incorporation in the gate oxide. A larger solid solubility and smaller diffusivety of Boron in poly-SiGe lead to a reduced incorporation of Boron in the dielectric [3]. Hence a lower neutral trap density and reduced SILC for poly-SiGe gates is expected [1,2,9].
injection(-Va) conditions. For n + poly-SiGe no significant difference in SILC characteristics compared to n + poly-Si is observed. For p+ gate devices, both the workfunction of the gate material and Boron penetration into the gate oxide strongly influence the SILC effect. Boron-doped poly-SiGe may be a very interesting gate material due to low SILC at +Va and better gate oxide quality.
4. Conclusions In summary, the DC-SILC characteristics of n + and p+ poly-Si and poly-SiGe MOS capacitors were studied under substrate(+V o) and gate-
REFERENCES 1. J. De Blauwe et al. "A new quantitative model to predict SILC-related disturb characteristics in Flash E2pROM devices", IEDM Tech.Digest, 1996 pp. 343-346. 2. D . J . DiMaria et aL, "Mechanism for stressinduced leakage currents in thin silicon dioxide films", J. Appl. Phys., no. 6(78) 1995 pp. 3883-3894. 3. C. Salm et al. " G a t e Current and Oxide Reliability in p+ Poly MOS Capacitors with PolySi and Poly-Ge0.aSi0.7 Gate Material", Electron Dev. Lett. vol 19(7) 1998 pp. 213-215. 4. J. -L. Ogier et al. " O n the Polarity Dependence of Oxide Breakdown in MOS-Devices with n + and p+ Polysilicon Gate", Proc. ESSDERC'96, 1996 pp. 763-766.
4t8
V. Houtsma et al. I Microelectronic Engineering 48 (1999) 4 1 5 - 4 1 8 10.6
10-6
- Jstress
+ Jstress
~' \'\.,
initial IV - - - - 100 P'C/cm2 ----- I mCtcm2 . . . . 10 mC/cm2
~'~ 10-8
\ ~', t"..."\':,,
...... lOOmC/cm2 ..... 0.5C/cm2
--tin 10.9
~'x
/f/ l ,//" ."l /"/ " t /I ......,4
'~.
10-7
x .. \,~'\ ......",\
/i /7
~
/i/
....... I C/cm2
lO.S
~X~
initial IV I - - - - tO0 laC']cm2: - - - lmC/cm2
+ Jstress
I . . . . tO mC/cm2 I .......... I00 mC/cm2
¢ .~~ '
I.....
/
:.!;~
o.5 C / c m 2
I,......
/ /
,..;.*(.I
~::.\ ........~>"?~.%.. p+ Poly-Si .~/',/:...''i~]x.../
lO-lO
/,,'J/;7
10-11 -7
-6
-5
-4
lO-6
- Jstress
¢~ 10-8
~k
10-9
10-ii
10-7
10-7
i7
~;"," '7t\5\---'-+ n Poly-S-"----T.(/:).{" ,4
lO-iO
- Jstre.~,s \
-3
-2 2 3 Eox [MV/cm]
--
initial IV
\
I- -
~. ~\
----- 1 mC/cm2 .... 10 mC/cm2 100 mC/cm2
~t "~\.
~" --~a 10"9
~~'xx:',.
4
5
6
7
+ Jstress
i ./
l°°uc/cm2
]/
10-6
-6
-5 3 4 Eox [MWcm]
initial IV 1oo ~,C/cm2 I mC,/cm2 . . . . 10 mC/cm2 .......... 100 mC/cm2 . . . . 0.5 C,)cm2 '...x\. ...... 1 C/cm2
--ao 10-9 ,-.n
I C/cm2
-7
tress
lO.S
//(:" / ,// • j /)' . / t~\',x X ......"\~,~\ n +Poly-SiGe 1!/,' : / /] / -..,:, /I/
1040
-8
10-7
// /7 If'l
I .... 0"5 C/cm2
I', "."x/, ',, ix '
-9
+
.
p Voly-SiGe
10"10
'~
5
6
+ Jstress
/ /
/ / ] .1 ([
/';, ~.:~/
: : " ~
10-11
10,-li -7
-6
-5
-4
-3
-2 2 3 Eox [MV/cm]
4
5
6
7
-9
-8
-7
-6
-5 3 4 Eox [MY/era]
5
6
7
Figure 5. J-Eo~ curves before and after stress (100#C/cm 2 to 1C/cm 2) for n + poly-Si and polySiGe gate material
Figure 6. J-Eox curves before and after stress (100#C/cm 2 to 1C/cm 2) for p+ poly-Si and polySiGe gate material
5. V.E. Houtsma et al. "Stress-Induced Leakage Current in p+ Poly MOS Capacitors with Poly-Si and Poly-Sio.TGe0.3 Gate Material", accepted for publication in Electron Dev. Lett. 6. T. -J. King et al. "A PolycrystallineSil_xGex-Gate CMOS Technology", IEDM Tech.Digest, 1990 pp. 253-256. 7. W. -C. Lee et al. "Observation of Reduced Poly-Gate Depletion Effect for PolySio.8Ge0.2-Gated NMOS Devices", Elec. and Solid-State Lett. vol 1(1) 1998 pp. 558-59. 8. A.I. Chou et al. "Modeling of stress-induced leakage current in ultrathin oxides with the
trap-assisted tunneling mechanism", Appl. Phys. Lett vol 70(25) 1997 pp. 3407-3409. . C. Jahan et al. "Investigation of StressInduced Leakage Current in CMOS Structures with Ultra-Thin Gate Dielectrics", Microelec. Reliab. vol 37(10/11) 1997 pp. 15291532.