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Effect of channel length on the threshold voltage degradation of hydrogenated amorphous silicon TFTs due to the drain bias stress
Journal of Non-Crystalline Solids 352 (2006) 1708–1710 www.elsevier.com/locate/jnoncrysol
Effect of channel length on the threshold voltage degradation of hydrogenated amorphous silicon TFTs due to the drain bias stress Kwang-Sub Shin *, Jae-Hoon Lee, Sang-Myeon Han, In-Hyuk Song, Min-Koo Han School of Electrical Engineering, Seoul National University, San 56-1, Shillim-dong, Kwanak-ku, Seoul 151-742, Republic of Korea Available online 18 April 2006
Abstract The threshold voltage (VT) degradation of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) with various channel lengths of 2–100 lm has been investigated. In the presence of a drain bias, the VT degradation of a short channel a-Si:H TFT was less than that of a long channel TFT. After 30 000 s DC bias stressing, the VT shift of a short channel TFT (2 lm) was 0.35 V, while that of a long channel TFT (10 lm) was 0.6 V. The short channel effect on the VT degradation under the drain bias was negligible when the channel length exceeded 10 lm. The less VT degradation in a short channel a-Si:H TFT can be explained by the defect creation model that the VT shift is proportional to the number of carriers induced in the channel. In the presence of a drain bias, a short channel a-Si:H TFT has the smaller carrier concentration than a long channel TFT, so that a short channel a-Si:H TFT creates less defect states than a long channel TFT. The experiment with different channel widths of 100–500 lm showed no remarkable difference as observed in the case of channel length variation. Ó 2006 Elsevier B.V. All rights reserved. PACS: 85.30.De Keyword: Thin film transistors
1. Introduction Hydrogenated amorphous silicon (a-Si:H) TFTs have been used as pixel elements for low cost, large-size AMLCD panels, due to their uniformity with respect to poly-Si TFTs and well-established manufacturing base. Recently, a-Si:H TFTs are being employed as a current source as well as a switching transistor in AMOLED applications. The transistors used as a current source in AMOLED pixel arrays have a bias at the drain terminal in addition to the gate, and have to occupy a very small area for high brightness and resolution. The short channel a-Si:H TFT can be an attractive device for the high resolution AMOLED displays. However studies on the reliability of short channel a-Si:H TFTs under drain bias have not been reported. *
Corresponding author. Tel.: +82 2 880 7992; fax: +82 2 871 7992. E-mail addresses: [email protected], [email protected] (K.-S. Shin).
0022-3093/$ - see front matter Ó 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.jnoncrysol.2005.10.068
In this letter, we report the short channel reliability of a-Si:H TFT under drain bias stress condition. In the absence of a bias at the TFT drain terminal, VT shift after 30 000 s stressing did not vary remarkably with channel length. However, in the presence of drain bias, threshold voltage (VT) shift decreased as the channel length reduced. In the same experiment carried out for a-Si:H TFTs with different channel widths, the VT shift showed no considerable difference as it was for different lengths. 2. Experiment Inverted staggered bottom gate type thin film transistors with different channel lengths of 2–100 lm were fabricated (W = 200 lm). The Mo/AlNd double layer was deposited on Corning 1737 glass by DC sputtering for the gate elec˚ ), a-Si:H (2000 A ˚ ), n+ trode. Triple layer of SiNx (4500 A ˚ a-Si:H (500 A) was deposited on the gate by using plasma-enhanced chemical vapor deposition (PECVD).
K.-S. Shin et al. / Journal of Non-Crystalline Solids 352 (2006) 1708–1710
1709
For the source and drain regions, the Mo/AlNd/Mo triple ˚ ) was deposited on the n+ a-Si:H layer. After layer (4500 A patterning the source and drain electrode, the n+ a-Si layer between the source and drain electrode was removed by dry etching to make an etch back type channel structure. ˚ thick SiNx was deposited as the passivation Finally, 3000 A layer. To reduce the contact resistance, the overlap lengths between the source/drain electrode and gate electrode were designed to be 10 lm, respectively. The TFTs with different channel widths but the same length (L = 4 lm) were also prepared to verify the effect of channel width on the threshold voltage (VT) shift. The test devices were annealed at 180 °C for 1 h before they were subjected to the bias stress experiment. After 30 000 s ofpDC ffiffiffiffiffi bias stressing at the room temperature of 25–27 °C, I D –V G curve was measured by using the semiconductor parameter analyzer (HP4156B) to extract VT. The gate and drain electrode were connected to place the devices in the saturation mode, and the VGS and VDS were swept from 0 to 20 V with a step size of 0.2 V. VT is defined as the intercept at which the extended slope between VG p ffiffiffiffiffi= 8 V, 16 V passes through the VG-axis in the I D –V G curve. The threshold voltages of a-Si:H TFTs before bias stressing ranged from 2.8 to 2.9 V.
drain bias. As the drain bias increases, the carrier concentration in the channel decreases [1]. Since the portion of the depleted charges over total charges increases with reducing channel length, the short channel TFTs have the smaller carrier concentration than the long channel TFTs. Consequently, the VT degradation in short channel TFTs would be smaller than that of long channel TFTs under the same drain bias condition. Our experiment showed that the short channel a-Si:H TFT of 2 lm have smaller VT shift of 0.35 V than the 10 lm channel a-Si:H TFT with VT shift of 0.6 V, under the same bias stress condition (at VG = 15 V, VD = 20 V). In the TFTs with over 10 lm channel length, the VT shift was almost the same as that of 10 lm channel length TFT, even though the channel length increased.
3. Results
DV T ðtÞ ¼ AðV ST V Ti Þtb ;
The threshold voltage shifts after 30 000 s DC bias stressing at the room temperature are shown in Fig. 1. In the absence of a bias at the TFT drain terminal (VG = 15 V, VD = 0 V), VT shift did not vary significantly with channel length, but in the presence of drain bias (VG = 15 V, VD = 10 V), VT shift decreased as the channel length reduced. VT shift decreased more significantly in the higher drain bias condition (VG = 15 V, VD = 20 V). Smaller VT shift in the short channel TFTs can be explained by the concentration of the channel charge varying with the
where A and b are temperature-dependent parameters, VST is the gate bias stress voltage, VTi is the VT of the TFT before bias stress is applied, and t is the bias stress time duration. When a bias is applied to the drain terminal, the carrier concentration in the channel decreases and consequently, less defect states are created so that the VT shift decreases if the drain bias exists. Therefore, Eq. (1) can be modified as follows [1]: QG DV T ðtÞ ¼ ð2Þ AðV GS V Ti Þtb . QG0
2.5 VG = 15V, VD = 0V VG = 15V, VD = 10V VG = 15V, VD = 20V
VT Shift (V)
2.0 1.5 1.0 0.5
VT shift decreased as the channel length reduced.
0.0 0
20
40
60
100
Channel Length (μm) Fig. 1. Threshold voltage shift versus channel length for different applied voltages (W = 200 lm). The stress time is 30 000 s.
4. Discussion a-Si:H TFTs exhibit a bias-induced metastability phenomenon that causes the threshold voltage shift over time in the presence of a gate bias [2]. a-Si:H TFTs under gate bias stress may degrade by two mechanisms. Defect state creation dominates at lower positive bias voltages, while charge trapping in the gate insulator becomes significant at higher gate voltages [3–5]. Defect state creation can be characterized by a power law dependence of DVT over time, and DVT can be represented as follows [6,7]: ð1Þ
Here, QG0 is the maximum channel charge (at VGS = VGD), QG is the gate and drain bias-dependent channel charge, and QG/QG0 is the normalized channel charge. VST has been replaced by VGS, and again, A and b are temperature-dependent parameters. The charge concentration plots along the channel, calculated by a two dimensional simulation, are shown in Fig. 2(a). In the absence of a drain bias (VG = 15 V, VD = 0 V), the concentration plots for 2, 4, 10, 20 lm channel length TFTs are almost the same regardless of channel length variation, but in the presence of drain bias (VG = 15 V, VD = 20 V), the charge concentration near the drain decreases, and the amount of depleted charges increases as the channel length is reduced. Fig. 2(b) shows the normalized channel charge (QG/ QG0) as a function of channel length. QG, QG0 were
1710
K.-S. Shin et al. / Journal of Non-Crystalline Solids 352 (2006) 1708–1710 16
2.5
3x10
4 μm VG=15V VD=20V
2μm 16
1x10
VG=15V, VD=20V
2.0
VG=15V VD= 0V
VT Shift (V)
16
2x10
20μm 10μm
1.5
No significant change of VT according to channel width.
1.0
-
-3
e conc. (cm )
2, 4, 10, 20μm
0.5 0
0.0 0.0
0.2
0.4
0.6
0.8
1.0
100
y/L
300
400
500
Channel Width (μm)
Fig. 2(a). Charge concentration along the channel for different channel lengths (calculated by two dimensional device simulator). The y coordinate represents the channel position from source toward drain.
Normalized channel charge (QG/QG0)
200
Fig. 3. Threshold voltage shift versus channel width under drain bias stress (L = 4 lm). The stress time is 30 000 s.
though the channel width is varied, the carrier concentration in the channel would not change.
1.6
VG = 15V, VD = 0V VG = 15V, VD = 10V VG = 15V, VD = 20V
1.4 1.2
5. Conclusion
1.0 0.8 0.6 0.4 0.2 0
10
20
30
40
50
60
100
Channel Length (μm) Fig. 2(b). Normalized channel charge (QG/QG0) as a function of channel length (W = 200 lm). QG, QG0 were calculated from Fig. 2(a).
calculated by integrating the curves in the Fig. 2(a). The normalized channel charge decreases with reducing channel length when the drain bias is applied, and it drops more significantly as the drain bias increases. The reduction of the normalized channel charge in the short channel TFTs may help explain their smaller DVT compared to the DVT of the long channel TFTs by using Eq. (2). The experimental data in Fig. 1 is in good agreement with the simulation result, and this can be explained by the DVT model in Eq. (2). Fig. 3 shows the dependence of VT shift on channel width under drain bias stress. The bias stress condition was VG = 15 V, VD = 20 V, and the channel length was fixed to 4 lm. The VT shift according to width varied from 100–500 lm showed no remarkable difference, as it was according to length. Since the charge depletion caused by a drain bias is merely affected by the channel length, even
We investigated the effect of channel length and width on the threshold voltage degradation of a-Si:H TFTs under drain bias stress. Our experimental results showed that a short channel a-Si:H TFT exhibited less degradation than a long channel TFT when the drain bias is applied. The less carrier concentration in a short channel TFT under drain bias creates less defect states, so that a short channel TFT exhibits less VT degradation than a long channel TFT. This can be an advantage of the a-Si:H TFT over the poly-Si TFT which can degrade more significantly when the channel length is reduced. We also simulated the carrier concentration in the channel for various channel length TFTs. It was in good agreement with our experimental result, and this can be explained by the defect creation model under drain bias. Our experiment indicates that a short channel a-Si:H TFT can be a reliable device for high resolution AMOLED display. References [1] K.S. Karim, A. Nathan, M. Hack, W.I. Milne, IEEE Electron Device Lett. 25 (2004) 188. [2] M.J. Powell, C. van Berkel, I.D. French, D.H. Nicholls, Appl. Phys. Lett. 51 (1987) 1242. [3] M.J. Powell, Appl. Phys. Lett. 43 (1983) 15. [4] F.R. Libsch, J. Kanicki, Appl. Phys. Lett. 62 (1993) 1286. [5] M.J. Powell, C.V. Berkel, A.R. Franklin, S.C. Deane, W.I. Milne, Am. Phys. Soc. Phys. Rev. B 45 (1992) 4160. [6] C.-S. Chiang, J. Kanicki, K. Takechi, Jpn. J. Appl. Phys. 37 (1998) 4704. [7] N. Ibaraki, M. Kigoshi, K. Fukuda, J. Kobayashi, J. Non-Cryst. Solids 115 (1989) 138.
Effect of channel length on the threshold voltage degradation of hydrogenated amorphous silicon TFTs due to the drain bias stress Kwang-Sub Shin *, Jae-Hoon Lee, Sang-Myeon Han, In-Hyuk Song, Min-Koo Han School of Electrical Engineering, Seoul National University, San 56-1, Shillim-dong, Kwanak-ku, Seoul 151-742, Republic of Korea Available online 18 April 2006
Abstract The threshold voltage (VT) degradation of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) with various channel lengths of 2–100 lm has been investigated. In the presence of a drain bias, the VT degradation of a short channel a-Si:H TFT was less than that of a long channel TFT. After 30 000 s DC bias stressing, the VT shift of a short channel TFT (2 lm) was 0.35 V, while that of a long channel TFT (10 lm) was 0.6 V. The short channel effect on the VT degradation under the drain bias was negligible when the channel length exceeded 10 lm. The less VT degradation in a short channel a-Si:H TFT can be explained by the defect creation model that the VT shift is proportional to the number of carriers induced in the channel. In the presence of a drain bias, a short channel a-Si:H TFT has the smaller carrier concentration than a long channel TFT, so that a short channel a-Si:H TFT creates less defect states than a long channel TFT. The experiment with different channel widths of 100–500 lm showed no remarkable difference as observed in the case of channel length variation. Ó 2006 Elsevier B.V. All rights reserved. PACS: 85.30.De Keyword: Thin film transistors
1. Introduction Hydrogenated amorphous silicon (a-Si:H) TFTs have been used as pixel elements for low cost, large-size AMLCD panels, due to their uniformity with respect to poly-Si TFTs and well-established manufacturing base. Recently, a-Si:H TFTs are being employed as a current source as well as a switching transistor in AMOLED applications. The transistors used as a current source in AMOLED pixel arrays have a bias at the drain terminal in addition to the gate, and have to occupy a very small area for high brightness and resolution. The short channel a-Si:H TFT can be an attractive device for the high resolution AMOLED displays. However studies on the reliability of short channel a-Si:H TFTs under drain bias have not been reported. *
Corresponding author. Tel.: +82 2 880 7992; fax: +82 2 871 7992. E-mail addresses: [email protected], [email protected] (K.-S. Shin).
0022-3093/$ - see front matter Ó 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.jnoncrysol.2005.10.068
In this letter, we report the short channel reliability of a-Si:H TFT under drain bias stress condition. In the absence of a bias at the TFT drain terminal, VT shift after 30 000 s stressing did not vary remarkably with channel length. However, in the presence of drain bias, threshold voltage (VT) shift decreased as the channel length reduced. In the same experiment carried out for a-Si:H TFTs with different channel widths, the VT shift showed no considerable difference as it was for different lengths. 2. Experiment Inverted staggered bottom gate type thin film transistors with different channel lengths of 2–100 lm were fabricated (W = 200 lm). The Mo/AlNd double layer was deposited on Corning 1737 glass by DC sputtering for the gate elec˚ ), a-Si:H (2000 A ˚ ), n+ trode. Triple layer of SiNx (4500 A ˚ a-Si:H (500 A) was deposited on the gate by using plasma-enhanced chemical vapor deposition (PECVD).
K.-S. Shin et al. / Journal of Non-Crystalline Solids 352 (2006) 1708–1710
1709
For the source and drain regions, the Mo/AlNd/Mo triple ˚ ) was deposited on the n+ a-Si:H layer. After layer (4500 A patterning the source and drain electrode, the n+ a-Si layer between the source and drain electrode was removed by dry etching to make an etch back type channel structure. ˚ thick SiNx was deposited as the passivation Finally, 3000 A layer. To reduce the contact resistance, the overlap lengths between the source/drain electrode and gate electrode were designed to be 10 lm, respectively. The TFTs with different channel widths but the same length (L = 4 lm) were also prepared to verify the effect of channel width on the threshold voltage (VT) shift. The test devices were annealed at 180 °C for 1 h before they were subjected to the bias stress experiment. After 30 000 s ofpDC ffiffiffiffiffi bias stressing at the room temperature of 25–27 °C, I D –V G curve was measured by using the semiconductor parameter analyzer (HP4156B) to extract VT. The gate and drain electrode were connected to place the devices in the saturation mode, and the VGS and VDS were swept from 0 to 20 V with a step size of 0.2 V. VT is defined as the intercept at which the extended slope between VG p ffiffiffiffiffi= 8 V, 16 V passes through the VG-axis in the I D –V G curve. The threshold voltages of a-Si:H TFTs before bias stressing ranged from 2.8 to 2.9 V.
drain bias. As the drain bias increases, the carrier concentration in the channel decreases [1]. Since the portion of the depleted charges over total charges increases with reducing channel length, the short channel TFTs have the smaller carrier concentration than the long channel TFTs. Consequently, the VT degradation in short channel TFTs would be smaller than that of long channel TFTs under the same drain bias condition. Our experiment showed that the short channel a-Si:H TFT of 2 lm have smaller VT shift of 0.35 V than the 10 lm channel a-Si:H TFT with VT shift of 0.6 V, under the same bias stress condition (at VG = 15 V, VD = 20 V). In the TFTs with over 10 lm channel length, the VT shift was almost the same as that of 10 lm channel length TFT, even though the channel length increased.
3. Results
DV T ðtÞ ¼ AðV ST V Ti Þtb ;
The threshold voltage shifts after 30 000 s DC bias stressing at the room temperature are shown in Fig. 1. In the absence of a bias at the TFT drain terminal (VG = 15 V, VD = 0 V), VT shift did not vary significantly with channel length, but in the presence of drain bias (VG = 15 V, VD = 10 V), VT shift decreased as the channel length reduced. VT shift decreased more significantly in the higher drain bias condition (VG = 15 V, VD = 20 V). Smaller VT shift in the short channel TFTs can be explained by the concentration of the channel charge varying with the
where A and b are temperature-dependent parameters, VST is the gate bias stress voltage, VTi is the VT of the TFT before bias stress is applied, and t is the bias stress time duration. When a bias is applied to the drain terminal, the carrier concentration in the channel decreases and consequently, less defect states are created so that the VT shift decreases if the drain bias exists. Therefore, Eq. (1) can be modified as follows [1]: QG DV T ðtÞ ¼ ð2Þ AðV GS V Ti Þtb . QG0
2.5 VG = 15V, VD = 0V VG = 15V, VD = 10V VG = 15V, VD = 20V
VT Shift (V)
2.0 1.5 1.0 0.5
VT shift decreased as the channel length reduced.
0.0 0
20
40
60
100
Channel Length (μm) Fig. 1. Threshold voltage shift versus channel length for different applied voltages (W = 200 lm). The stress time is 30 000 s.
4. Discussion a-Si:H TFTs exhibit a bias-induced metastability phenomenon that causes the threshold voltage shift over time in the presence of a gate bias [2]. a-Si:H TFTs under gate bias stress may degrade by two mechanisms. Defect state creation dominates at lower positive bias voltages, while charge trapping in the gate insulator becomes significant at higher gate voltages [3–5]. Defect state creation can be characterized by a power law dependence of DVT over time, and DVT can be represented as follows [6,7]: ð1Þ
Here, QG0 is the maximum channel charge (at VGS = VGD), QG is the gate and drain bias-dependent channel charge, and QG/QG0 is the normalized channel charge. VST has been replaced by VGS, and again, A and b are temperature-dependent parameters. The charge concentration plots along the channel, calculated by a two dimensional simulation, are shown in Fig. 2(a). In the absence of a drain bias (VG = 15 V, VD = 0 V), the concentration plots for 2, 4, 10, 20 lm channel length TFTs are almost the same regardless of channel length variation, but in the presence of drain bias (VG = 15 V, VD = 20 V), the charge concentration near the drain decreases, and the amount of depleted charges increases as the channel length is reduced. Fig. 2(b) shows the normalized channel charge (QG/ QG0) as a function of channel length. QG, QG0 were
1710
K.-S. Shin et al. / Journal of Non-Crystalline Solids 352 (2006) 1708–1710 16
2.5
3x10
4 μm VG=15V VD=20V
2μm 16
1x10
VG=15V, VD=20V
2.0
VG=15V VD= 0V
VT Shift (V)
16
2x10
20μm 10μm
1.5
No significant change of VT according to channel width.
1.0
-
-3
e conc. (cm )
2, 4, 10, 20μm
0.5 0
0.0 0.0
0.2
0.4
0.6
0.8
1.0
100
y/L
300
400
500
Channel Width (μm)
Fig. 2(a). Charge concentration along the channel for different channel lengths (calculated by two dimensional device simulator). The y coordinate represents the channel position from source toward drain.
Normalized channel charge (QG/QG0)
200
Fig. 3. Threshold voltage shift versus channel width under drain bias stress (L = 4 lm). The stress time is 30 000 s.
though the channel width is varied, the carrier concentration in the channel would not change.
1.6
VG = 15V, VD = 0V VG = 15V, VD = 10V VG = 15V, VD = 20V
1.4 1.2
5. Conclusion
1.0 0.8 0.6 0.4 0.2 0
10
20
30
40
50
60
100
Channel Length (μm) Fig. 2(b). Normalized channel charge (QG/QG0) as a function of channel length (W = 200 lm). QG, QG0 were calculated from Fig. 2(a).
calculated by integrating the curves in the Fig. 2(a). The normalized channel charge decreases with reducing channel length when the drain bias is applied, and it drops more significantly as the drain bias increases. The reduction of the normalized channel charge in the short channel TFTs may help explain their smaller DVT compared to the DVT of the long channel TFTs by using Eq. (2). The experimental data in Fig. 1 is in good agreement with the simulation result, and this can be explained by the DVT model in Eq. (2). Fig. 3 shows the dependence of VT shift on channel width under drain bias stress. The bias stress condition was VG = 15 V, VD = 20 V, and the channel length was fixed to 4 lm. The VT shift according to width varied from 100–500 lm showed no remarkable difference, as it was according to length. Since the charge depletion caused by a drain bias is merely affected by the channel length, even
We investigated the effect of channel length and width on the threshold voltage degradation of a-Si:H TFTs under drain bias stress. Our experimental results showed that a short channel a-Si:H TFT exhibited less degradation than a long channel TFT when the drain bias is applied. The less carrier concentration in a short channel TFT under drain bias creates less defect states, so that a short channel TFT exhibits less VT degradation than a long channel TFT. This can be an advantage of the a-Si:H TFT over the poly-Si TFT which can degrade more significantly when the channel length is reduced. We also simulated the carrier concentration in the channel for various channel length TFTs. It was in good agreement with our experimental result, and this can be explained by the defect creation model under drain bias. Our experiment indicates that a short channel a-Si:H TFT can be a reliable device for high resolution AMOLED display. References [1] K.S. Karim, A. Nathan, M. Hack, W.I. Milne, IEEE Electron Device Lett. 25 (2004) 188. [2] M.J. Powell, C. van Berkel, I.D. French, D.H. Nicholls, Appl. Phys. Lett. 51 (1987) 1242. [3] M.J. Powell, Appl. Phys. Lett. 43 (1983) 15. [4] F.R. Libsch, J. Kanicki, Appl. Phys. Lett. 62 (1993) 1286. [5] M.J. Powell, C.V. Berkel, A.R. Franklin, S.C. Deane, W.I. Milne, Am. Phys. Soc. Phys. Rev. B 45 (1992) 4160. [6] C.-S. Chiang, J. Kanicki, K. Takechi, Jpn. J. Appl. Phys. 37 (1998) 4704. [7] N. Ibaraki, M. Kigoshi, K. Fukuda, J. Kobayashi, J. Non-Cryst. Solids 115 (1989) 138.