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Effect of implant damage on the gate oxide thickness
Solid-State Electronics 43 (1999) 985±988
Eect of implant damage on the gate oxide thickness H.-H. Vuong a,*, J. Bude a, F.H. Baumann a, K. Evans-Lutterodt a, J. Ning b, Y. Ma b, J. Mcmacken b, H.-J. Gossmann a, P. Silverman a, C.S. Raerty a, S.J. Hillenius a a
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA b Bell Laboratories, Lucent Technologies, Orlando, FL 32819, USA Received 1 January 1999; accepted 25 January 1999
Abstract Large area capacitors were fabricated with doping and oxide thickness representative of an n-MOSFET channel region. Capacitance±voltage (C±V ) measurements on these capacitors showed a systematic change in the accumulation capacitance when additional implant damage is introduced by a 11014 cmÿ2 40 keV silicon implant. The oxide thickness values extracted from the C±V data increase by 1±4 AÊ with the additional implant damage. This trend is con®rmed by additional high resolution TEM and X-ray re¯ectivity measurements. We postulate that the implant damage increased the oxidation rate, due either to the interstitial ¯ux during TED, or to an increase in surface roughness. For channels doped with boron implantation, the increase in thickness does not change with a 5 increase in the doping dose. In contrast, with BF2-implanted channels, the eects are smaller for higher doping dose. # 1999 Elsevier Science Ltd. All rights reserved.
1. Introduction As CMOS technology continues to scale down, channel doping levels increase to maintain resistance to short-channel eects [1]. Furthermore, to reduce cost and processing time, most or all of the doping for the channel is implanted just before gate oxidation, rather than at earlier steps as in older technologies. A prime example is the shift from using diused well to using high energy implant (HEI) before gate oxidation for the well doping [2,3]. Both these trends increase the total implant dose, and hence the implant damage, in the bulk silicon just prior to gate oxidation. Therefore, it is important to study the eects of the implant damage. The eect of transient enhanced diusion
* Corresponding author. Tel.: +1-908-582-6692. E-mail address: [email protected] (H.H. Vuong)
(TED) caused by the implant damage on the dopant pro®les had been addressed previously (e.g. [2,3]). In this study, we report for the ®rst time on the eect of the implant damage on the gate oxide itself. The oxide is investigated primarily through C±V measurement via its capacitance COX, which is the quantity entering directly into equations governing the device performance. Additional high resolution TEM (HR-TEM) and X-ray re¯ectivity were used to measure some samples to provide greater understanding of the phenomenon. 2. Experiment A 20-nm sacri®cial oxide was grown on [100] silicon substrates. Wafers were then split between four implant recipes: (A) 41012 cmÿ2 boron at 40 keV, (B) 21013 cmÿ2 boron at 40 keV, (C) 41012 cmÿ2 BF2 at 40 keV and (D) 21013 cmÿ2 BF2 at 40 keV. Half
0038-1101/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 9 9 ) 0 0 0 5 0 - 7
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H.-H. Vuong et al. / Solid-State Electronics 43 (1999) 985±988
Fig. 1. High-frequency C±V curves for the 120 AÊ nominal oxidation, for the four implant conditions (A±D) described in the text. No additional Si implant was given for these splits.
of the wafers received a second implant of 1 1014 cmÿ2 silicon implant at 40 keV to produce additional implant damage without introducing any further dopant atoms. The sacri®cial oxide was etched, and gate oxidation performed immediately. The wafers were split between 60 and 120 AÊ oxidation, with all wafers oxidized together for each split. The two oxidation splits were carried out at 8508C, with an ambient of dry oxygen and 2% DCE, with the same furnace ramp conditions, and diering only in the oxidation time. After the gate oxidation, 2800 AÊ of polysilicon was deposited, doped with a 4 1015 cmÿ2 60 keV arsenic implant which was activated by rapid thermal anneal at 10508C for 5 s. Aluminum was deposited, and capacitor patterns formed by aluminum and polysilicon etching. 3. Results Simultaneous quasistatic and high-frequency (100 kHz) C±V measurements on 200 200 mm capacitors were carried out. This enables extraction of the doping pro®les which will be reported fully later. For this study, the results can be summarized as showing that the doping pro®les extracted from C±V measurements and from SIMS analysis agree well with those simulated from the experimental conditions given in Section 2. In the accumulation region quasistatic and high-frequency measurements give the same data. Since the latter is less noisy, for the sake of clarity, our ®gures will only show the high-frequency data. Fig. 1 plots the C± V curves for the 120 AÊ oxidation for dopant implant splits (A) to (D), without additional Si implant. The
Fig. 2. The accumulation region of the high-frequency C±V curves for the (a) 60 AÊ and (b) 120 AÊ nominal oxidation. Solid and dotted lines are splits without and with additional silicon implant, respectively. Dopant implant splits were: (A) 4 1012 cmÿ2 boron, (B) 2 1013 cmÿ2 boron, (C) 4 1012 cmÿ2 BF2, (D) 2 1013 cmÿ2 BF2, all at 40 keV implant energy. DCdamage is de®ned for split C in Fig. 2(a).
dierent dopant conditions lead to dierences in the depletion part of the C±V curves. However, in the accumulation region of the curves, all four curves coincide (on the scale of this graph), since the capacitance in this region is determined primarily by COX. Fig. 2(a) and (b) show the accumulation region in close-up for all the splits in the experiment. Clearly, the additional silicon implant causes a reduction in accumulation capacitance, DCdamage, which corresponds to an increase in the electrically-measured gate oxide thickness. DCdamage is much larger than the intrawafer variation, and is also larger than the dierence between
H.-H. Vuong et al. / Solid-State Electronics 43 (1999) 985±988
987
Values of TOX, the gate oxide thickness, were extracted from the C±V curves using a simulator which takes into account the quantum eects and the Fermi±Dirac carrier distribution as well as polysilicon depletion eect [4]. Fig. 3 shows DTOXdamage, the dierence in the extracted oxide thickness due to the silicon implant, for each of the four dopant implant splits. The plot restates observations (a±c) quantitatively in terms of TOX. Table 1 compares the electrical oxide thickness to that measured physically for four of the splits. 4. Discussion
Fig. 3. The dierence in oxide thickness due to the eect of the additional silicon implant as a function of the dopant implant condition and oxidation process. The oxide thicknesses were extracted from C±V curves using a simulator which accounted for quantum-mechanical eects in carrier distribution and for polysilicon eect. Error bars re¯ect measurement variations from site to site. The inset shows a typical ®t to the quasi-static C±V curves between simulated (symbols) and measured data (lines), using the doping pro®le obtained from SIMS analysis.
dopant implant splits when there is no silicon implant. The following additional observations are clearest for the 60 AÊ oxidation, but they hold for both 60 and 120 AÊ: (a) DCdamage appears to be identical for 4 1012 cmÿ2 and 2 1013 cmÿ2 boron implants; (b) DCdamage is larger for the BF2-implanted wafers compared with the boron-implanted wafers; (c) DCdamage is larger for the lower dose 41012 cmÿ2 BF2 than for the 21013 cmÿ2 BF2-implanted wafers.
Table 1 shows that TOX values extracted from C±V measurements agree well with that measured physically: all electrical oxide thicknesses fall between the values measured by HR-TEM and by X-ray re¯ectivity. The uncertainty in the TEM value is relatively large because HR-TEM probes only a small area and thus has a small statistical sampling. However, within the uncertainty, the average TEM values are consistent with the electrically-measured trend of increasing oxide thickness with increased implant damage. In contrast, the X-ray measurement probes an area comparable to the capacitor area. Its measured values, though, include the thickness of both the bulk and the interfacial SiO2 [5,6], and are larger than the TEM values. The X-ray TOX values also con®rm the trend of increasing oxide thickness with increased TED. It is known that implant damage can induce a pileup of boron at the oxide interface during TED [7]. The pile-up could in principle increase the oxidation rate, since oxidation is faster for extrinsically-doped silicon. However, quantitative simulations show that for the present processing conditions, this is a small eect. We postulate instead that the additional TED damage itself increases the oxidation rate. Two possible mechanisms for this are: (a) the oxidation reaction rate is increased by the additional ¯ux of silicon interstitials moving to the interface during TED [7] and (b) the ¯ux of silicon interstitials to the interface changes the
Table 1 Errors quoted in Table 1 are (a) one sigma of the variation of the accumulation capacitance for each split in the C±V TOX values; (b) one sigma of the variation in measured HR-TEM TOX across the sample due to interface roughness at the Si±SiO2 and the SiO2±polysilicon interfaces; (c) least-square ®t errors in analysis of the X-ray re¯ectivity curves for the X-ray TOX Implant 2E13 2E13 2E13 2E13
cmÿ2 cmÿ2 cmÿ2 cmÿ2
B B+1E14 cmÿ2 Si B B+1E14 cmÿ2 Si
Nominal thickness (AÊ)
C±V TOX ( AÊ)
HR-TEM TOX (AÊ)
X-ray TOX (AÊ)
60 60 120 120
62.020.04 64.720.07 11920.1 120.520.2
6024 6021 10621 11423
64.120.14 67.020.3 120.420.14 122.120.14
988
H.-H. Vuong et al. / Solid-State Electronics 43 (1999) 985±988
interfacial layer in a way which increases the oxidation rate, for example by increasing the surface roughness and thus presenting more surface area for the oxidation reaction. We have modeled an increase in the initial oxidation rate [8] with additional implant damage such as to give DTOXdamage of 2 AÊ for the 60 AÊ oxidation. This model predicts that DTOXdamage for the 120 AÊ oxidation should be greater or at least equal to 2 AÊ, depending on how the increase in the oxidation rate is assumed to vary with time. The HR-TEM and X-ray data support this trend, but not the C±V TOX. However, the latter is dependent not only on oxide thickness but also on the dielectric constant. Given that a substantial interfacial layer exists whose dielectric constant is intermediate between that of silicon and SiO2, and given that the layer's extent decreases on additional annealing [5], this could explain the slight decrease of the C±V measured DTOXdamage with additional oxidation time. The behavior of DTOXdamage for the dopant splits with BF2 dopant is more complex. Even without the silicon implant, BF2 increases the oxide thickness slightly, compared with boron-implanted wafers (Fig. 2(a) and (b)). This is due to the presence of ¯uorine from BF2, because ¯uorine acts to increase the oxidation rate [9±11]. With the addition of silicon implant, the apparent oxide increased to its largest value with the low BF2 dopant dose, for both the 60 and 120 AÊ nominal oxidation (Fig. 3). However, when the BF2 dose is increased 5 , DTOXdamage decreases. A second eect must be involved. Fluorine is known to reduce the interstitial concentration: TED experiments have shown that implanted ¯uorine can act as an interstitial trap [12]. For the higher BF2 dose, the eect of interstitial trapping may dominate over the ¯uorine-interstitial enhancement of oxidation. This would explain the observed DTOXdamage dependence on BF2 dose. 5. Conclusion We report on a systematic increase in the oxide thickness when additional implant damage is introduced before thermal oxidation. The increase is measured electrically from C±V data as well as in the physical values measured by HR-TEM and X-ray. The
observed increase in the electrical oxide thickness ranges up to 4 AÊ, which is of signi®cance as device scaling dictates gate oxide thickness of 30 AÊ and smaller. We postulate that the implant damage increases the oxidation rate itself, with the electrical measurement being aected by changes in the interfacial oxide layer also. For BF2 implant species, as opposed to boron, the eect shows a dopant±implant dose dependence most likely due to opposing eects of ¯uorine on the oxidation rate and on the interstitial concentration. Acknowledgements We thank the Murray Hill SFRL and the Orlando OR1 lines for device processing, and J. Bevk, K. Krisch, and M.L. Green for helpful discussions. References [1] Brews JR, Fitchner W, Nicollian EH, Sze SM. IEEE Electron Device Lett 1980;1:2. [2] Kamgar A, Vuong H-H, Liu CT, Raerty CS, Clemens JT. IEDM Tech Dig 1997:695. [3] Chaudhry S, Raerty CS, Nagy WJ, Chyan YF, Carroll MS, Chen AS, Lee KH. IEDM Tech Dig 1997:679. [4] Krisch KS, Bude JD, Manchanda L. IEEE Electron Dev Lett 1996;17:521. [5] Kosowsky SD, Pershan PS, Krisch KS, Bevk J, Green ML, Brasen D, Feldman LC, Roy PK. Appl Phys Lett 1997;70:3119. [6] Tan M-T, Evans-Lutterodt KW, Green ML, Brasen D, Krisch K, Manchanda L, Higashi GS, Boone T. Appl Phys Lett 1994;64:748. [7] Raerty CS, Vuong H-H, Eshraghi SA, Giles MD, Pinto MR, Hillenius SJ. IEDM Tech Dig 1993:311. [8] Massoud HZ, Plummer JD, Irene EA. J Electrochem Soc 1985;132:2685. [9] Morita M, Kubo T, Ishihara T, Hirose M. Appl Phys Lett 1984;45:1312. [10] Kouvatsos D, Huang JG, Jaccodine RJ. J Electrochem Soc 1991;138:1752. [11] Tsai J-Y, Shi Y, Prasad S, Yeh SW-C, Rakkhit R. IEEE Electron Device Lett 1998;19:351. [12] Vuong HH, Gossmann H-J, Raerty CS, Luftman HS, Unterwald FC, Jacobson DC, Ahrens RE, Boone T, Zeitzo PM. J Appl Phys 1995;77:3056.
Eect of implant damage on the gate oxide thickness H.-H. Vuong a,*, J. Bude a, F.H. Baumann a, K. Evans-Lutterodt a, J. Ning b, Y. Ma b, J. Mcmacken b, H.-J. Gossmann a, P. Silverman a, C.S. Raerty a, S.J. Hillenius a a
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA b Bell Laboratories, Lucent Technologies, Orlando, FL 32819, USA Received 1 January 1999; accepted 25 January 1999
Abstract Large area capacitors were fabricated with doping and oxide thickness representative of an n-MOSFET channel region. Capacitance±voltage (C±V ) measurements on these capacitors showed a systematic change in the accumulation capacitance when additional implant damage is introduced by a 11014 cmÿ2 40 keV silicon implant. The oxide thickness values extracted from the C±V data increase by 1±4 AÊ with the additional implant damage. This trend is con®rmed by additional high resolution TEM and X-ray re¯ectivity measurements. We postulate that the implant damage increased the oxidation rate, due either to the interstitial ¯ux during TED, or to an increase in surface roughness. For channels doped with boron implantation, the increase in thickness does not change with a 5 increase in the doping dose. In contrast, with BF2-implanted channels, the eects are smaller for higher doping dose. # 1999 Elsevier Science Ltd. All rights reserved.
1. Introduction As CMOS technology continues to scale down, channel doping levels increase to maintain resistance to short-channel eects [1]. Furthermore, to reduce cost and processing time, most or all of the doping for the channel is implanted just before gate oxidation, rather than at earlier steps as in older technologies. A prime example is the shift from using diused well to using high energy implant (HEI) before gate oxidation for the well doping [2,3]. Both these trends increase the total implant dose, and hence the implant damage, in the bulk silicon just prior to gate oxidation. Therefore, it is important to study the eects of the implant damage. The eect of transient enhanced diusion
* Corresponding author. Tel.: +1-908-582-6692. E-mail address: [email protected] (H.H. Vuong)
(TED) caused by the implant damage on the dopant pro®les had been addressed previously (e.g. [2,3]). In this study, we report for the ®rst time on the eect of the implant damage on the gate oxide itself. The oxide is investigated primarily through C±V measurement via its capacitance COX, which is the quantity entering directly into equations governing the device performance. Additional high resolution TEM (HR-TEM) and X-ray re¯ectivity were used to measure some samples to provide greater understanding of the phenomenon. 2. Experiment A 20-nm sacri®cial oxide was grown on [100] silicon substrates. Wafers were then split between four implant recipes: (A) 41012 cmÿ2 boron at 40 keV, (B) 21013 cmÿ2 boron at 40 keV, (C) 41012 cmÿ2 BF2 at 40 keV and (D) 21013 cmÿ2 BF2 at 40 keV. Half
0038-1101/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 9 9 ) 0 0 0 5 0 - 7
986
H.-H. Vuong et al. / Solid-State Electronics 43 (1999) 985±988
Fig. 1. High-frequency C±V curves for the 120 AÊ nominal oxidation, for the four implant conditions (A±D) described in the text. No additional Si implant was given for these splits.
of the wafers received a second implant of 1 1014 cmÿ2 silicon implant at 40 keV to produce additional implant damage without introducing any further dopant atoms. The sacri®cial oxide was etched, and gate oxidation performed immediately. The wafers were split between 60 and 120 AÊ oxidation, with all wafers oxidized together for each split. The two oxidation splits were carried out at 8508C, with an ambient of dry oxygen and 2% DCE, with the same furnace ramp conditions, and diering only in the oxidation time. After the gate oxidation, 2800 AÊ of polysilicon was deposited, doped with a 4 1015 cmÿ2 60 keV arsenic implant which was activated by rapid thermal anneal at 10508C for 5 s. Aluminum was deposited, and capacitor patterns formed by aluminum and polysilicon etching. 3. Results Simultaneous quasistatic and high-frequency (100 kHz) C±V measurements on 200 200 mm capacitors were carried out. This enables extraction of the doping pro®les which will be reported fully later. For this study, the results can be summarized as showing that the doping pro®les extracted from C±V measurements and from SIMS analysis agree well with those simulated from the experimental conditions given in Section 2. In the accumulation region quasistatic and high-frequency measurements give the same data. Since the latter is less noisy, for the sake of clarity, our ®gures will only show the high-frequency data. Fig. 1 plots the C± V curves for the 120 AÊ oxidation for dopant implant splits (A) to (D), without additional Si implant. The
Fig. 2. The accumulation region of the high-frequency C±V curves for the (a) 60 AÊ and (b) 120 AÊ nominal oxidation. Solid and dotted lines are splits without and with additional silicon implant, respectively. Dopant implant splits were: (A) 4 1012 cmÿ2 boron, (B) 2 1013 cmÿ2 boron, (C) 4 1012 cmÿ2 BF2, (D) 2 1013 cmÿ2 BF2, all at 40 keV implant energy. DCdamage is de®ned for split C in Fig. 2(a).
dierent dopant conditions lead to dierences in the depletion part of the C±V curves. However, in the accumulation region of the curves, all four curves coincide (on the scale of this graph), since the capacitance in this region is determined primarily by COX. Fig. 2(a) and (b) show the accumulation region in close-up for all the splits in the experiment. Clearly, the additional silicon implant causes a reduction in accumulation capacitance, DCdamage, which corresponds to an increase in the electrically-measured gate oxide thickness. DCdamage is much larger than the intrawafer variation, and is also larger than the dierence between
H.-H. Vuong et al. / Solid-State Electronics 43 (1999) 985±988
987
Values of TOX, the gate oxide thickness, were extracted from the C±V curves using a simulator which takes into account the quantum eects and the Fermi±Dirac carrier distribution as well as polysilicon depletion eect [4]. Fig. 3 shows DTOXdamage, the dierence in the extracted oxide thickness due to the silicon implant, for each of the four dopant implant splits. The plot restates observations (a±c) quantitatively in terms of TOX. Table 1 compares the electrical oxide thickness to that measured physically for four of the splits. 4. Discussion
Fig. 3. The dierence in oxide thickness due to the eect of the additional silicon implant as a function of the dopant implant condition and oxidation process. The oxide thicknesses were extracted from C±V curves using a simulator which accounted for quantum-mechanical eects in carrier distribution and for polysilicon eect. Error bars re¯ect measurement variations from site to site. The inset shows a typical ®t to the quasi-static C±V curves between simulated (symbols) and measured data (lines), using the doping pro®le obtained from SIMS analysis.
dopant implant splits when there is no silicon implant. The following additional observations are clearest for the 60 AÊ oxidation, but they hold for both 60 and 120 AÊ: (a) DCdamage appears to be identical for 4 1012 cmÿ2 and 2 1013 cmÿ2 boron implants; (b) DCdamage is larger for the BF2-implanted wafers compared with the boron-implanted wafers; (c) DCdamage is larger for the lower dose 41012 cmÿ2 BF2 than for the 21013 cmÿ2 BF2-implanted wafers.
Table 1 shows that TOX values extracted from C±V measurements agree well with that measured physically: all electrical oxide thicknesses fall between the values measured by HR-TEM and by X-ray re¯ectivity. The uncertainty in the TEM value is relatively large because HR-TEM probes only a small area and thus has a small statistical sampling. However, within the uncertainty, the average TEM values are consistent with the electrically-measured trend of increasing oxide thickness with increased implant damage. In contrast, the X-ray measurement probes an area comparable to the capacitor area. Its measured values, though, include the thickness of both the bulk and the interfacial SiO2 [5,6], and are larger than the TEM values. The X-ray TOX values also con®rm the trend of increasing oxide thickness with increased TED. It is known that implant damage can induce a pileup of boron at the oxide interface during TED [7]. The pile-up could in principle increase the oxidation rate, since oxidation is faster for extrinsically-doped silicon. However, quantitative simulations show that for the present processing conditions, this is a small eect. We postulate instead that the additional TED damage itself increases the oxidation rate. Two possible mechanisms for this are: (a) the oxidation reaction rate is increased by the additional ¯ux of silicon interstitials moving to the interface during TED [7] and (b) the ¯ux of silicon interstitials to the interface changes the
Table 1 Errors quoted in Table 1 are (a) one sigma of the variation of the accumulation capacitance for each split in the C±V TOX values; (b) one sigma of the variation in measured HR-TEM TOX across the sample due to interface roughness at the Si±SiO2 and the SiO2±polysilicon interfaces; (c) least-square ®t errors in analysis of the X-ray re¯ectivity curves for the X-ray TOX Implant 2E13 2E13 2E13 2E13
cmÿ2 cmÿ2 cmÿ2 cmÿ2
B B+1E14 cmÿ2 Si B B+1E14 cmÿ2 Si
Nominal thickness (AÊ)
C±V TOX ( AÊ)
HR-TEM TOX (AÊ)
X-ray TOX (AÊ)
60 60 120 120
62.020.04 64.720.07 11920.1 120.520.2
6024 6021 10621 11423
64.120.14 67.020.3 120.420.14 122.120.14
988
H.-H. Vuong et al. / Solid-State Electronics 43 (1999) 985±988
interfacial layer in a way which increases the oxidation rate, for example by increasing the surface roughness and thus presenting more surface area for the oxidation reaction. We have modeled an increase in the initial oxidation rate [8] with additional implant damage such as to give DTOXdamage of 2 AÊ for the 60 AÊ oxidation. This model predicts that DTOXdamage for the 120 AÊ oxidation should be greater or at least equal to 2 AÊ, depending on how the increase in the oxidation rate is assumed to vary with time. The HR-TEM and X-ray data support this trend, but not the C±V TOX. However, the latter is dependent not only on oxide thickness but also on the dielectric constant. Given that a substantial interfacial layer exists whose dielectric constant is intermediate between that of silicon and SiO2, and given that the layer's extent decreases on additional annealing [5], this could explain the slight decrease of the C±V measured DTOXdamage with additional oxidation time. The behavior of DTOXdamage for the dopant splits with BF2 dopant is more complex. Even without the silicon implant, BF2 increases the oxide thickness slightly, compared with boron-implanted wafers (Fig. 2(a) and (b)). This is due to the presence of ¯uorine from BF2, because ¯uorine acts to increase the oxidation rate [9±11]. With the addition of silicon implant, the apparent oxide increased to its largest value with the low BF2 dopant dose, for both the 60 and 120 AÊ nominal oxidation (Fig. 3). However, when the BF2 dose is increased 5 , DTOXdamage decreases. A second eect must be involved. Fluorine is known to reduce the interstitial concentration: TED experiments have shown that implanted ¯uorine can act as an interstitial trap [12]. For the higher BF2 dose, the eect of interstitial trapping may dominate over the ¯uorine-interstitial enhancement of oxidation. This would explain the observed DTOXdamage dependence on BF2 dose. 5. Conclusion We report on a systematic increase in the oxide thickness when additional implant damage is introduced before thermal oxidation. The increase is measured electrically from C±V data as well as in the physical values measured by HR-TEM and X-ray. The
observed increase in the electrical oxide thickness ranges up to 4 AÊ, which is of signi®cance as device scaling dictates gate oxide thickness of 30 AÊ and smaller. We postulate that the implant damage increases the oxidation rate itself, with the electrical measurement being aected by changes in the interfacial oxide layer also. For BF2 implant species, as opposed to boron, the eect shows a dopant±implant dose dependence most likely due to opposing eects of ¯uorine on the oxidation rate and on the interstitial concentration. Acknowledgements We thank the Murray Hill SFRL and the Orlando OR1 lines for device processing, and J. Bevk, K. Krisch, and M.L. Green for helpful discussions. References [1] Brews JR, Fitchner W, Nicollian EH, Sze SM. IEEE Electron Device Lett 1980;1:2. [2] Kamgar A, Vuong H-H, Liu CT, Raerty CS, Clemens JT. IEDM Tech Dig 1997:695. [3] Chaudhry S, Raerty CS, Nagy WJ, Chyan YF, Carroll MS, Chen AS, Lee KH. IEDM Tech Dig 1997:679. [4] Krisch KS, Bude JD, Manchanda L. IEEE Electron Dev Lett 1996;17:521. [5] Kosowsky SD, Pershan PS, Krisch KS, Bevk J, Green ML, Brasen D, Feldman LC, Roy PK. Appl Phys Lett 1997;70:3119. [6] Tan M-T, Evans-Lutterodt KW, Green ML, Brasen D, Krisch K, Manchanda L, Higashi GS, Boone T. Appl Phys Lett 1994;64:748. [7] Raerty CS, Vuong H-H, Eshraghi SA, Giles MD, Pinto MR, Hillenius SJ. IEDM Tech Dig 1993:311. [8] Massoud HZ, Plummer JD, Irene EA. J Electrochem Soc 1985;132:2685. [9] Morita M, Kubo T, Ishihara T, Hirose M. Appl Phys Lett 1984;45:1312. [10] Kouvatsos D, Huang JG, Jaccodine RJ. J Electrochem Soc 1991;138:1752. [11] Tsai J-Y, Shi Y, Prasad S, Yeh SW-C, Rakkhit R. IEEE Electron Device Lett 1998;19:351. [12] Vuong HH, Gossmann H-J, Raerty CS, Luftman HS, Unterwald FC, Jacobson DC, Ahrens RE, Boone T, Zeitzo PM. J Appl Phys 1995;77:3056.