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Effects of composition and thickness of TiN metal gate on the equivalent oxide thickness and flat-band voltage in metal oxide semiconductor devices
Microelectronic Engineering 109 (2013) 160–162
Contents lists available at SciVerse ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Effects of composition and thickness of TiN metal gate on the equivalent oxide thickness and flat-band voltage in metal oxide semiconductor devices Seok-Hee Lee a, Rino Choi b, Changhwan Choi c,⇑ a
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Republic of Korea School of Materials Science and Engineering, Inha University, Incheon 402-751, Republic of Korea c Division of Materials Science and Engineering, Hanyang University, Seoul 133-791, Republic of Korea b
a r t i c l e
i n f o
Article history: Available online 27 March 2013 Keywords: High-j gate dielectric Metal gate Flat-band voltage CMOS integration
a b s t r a c t We investigated the effects of gas flow rates during sputtering and thickness of TiN metal gate on the equivalent oxide thickness (EOT) and flat band voltage (VFB) in the gate-first (GF) processed metal oxide semiconductor (MOS) devices with HfO2 and HfSiON-based gate dielectrics. For both HfO2 and HfiSON devices, more metallic TiN causes thinner EOT with lower VFB while higher VFB is observed along with thicker EOT for nitrogen-rich TiN case. Also, thicker TiN induces more positive VFB shift. However, for HfSiON, amount of VFB shift and EOT reduction is smaller than those of HfO2-based device, resulting from stronger immunity of Hf-Si bonding against oxygen vacancy generation during thermal process. Ó 2013 Elsevier B.V. All rights reserved.
1. Introduction Improved transistor performance and reduced power consumption have been continuously achieved by scaling device dimensions in conjunction with adopting alternative materials and integration schemes. Among them, high-k gate dielectric/metal gate (HKMG) technology has been suggested to enhance device functionality and lower power dissipation. Since 45 nm technology node, HKMG technology have been firstly implemented into commercial Si chip products using gate last (GL) integration process scheme, called replacement gate process [1]. However, considering process cost and complexity, GL process may not be necessary for low power mobile devices where leakage reduction is more important parameter than performance enhancement. Also, threshold voltage (Vth) requirement of peripheral transistor for dynamic random access memory (DRAM) device is not as strict as high performance applications. Therefore, conventional GF integration scheme is still attractive to devices aforementioned if HKMG gate stack meets device requirements for complementary metal oxide semiconductor (CMOS) such as symmetric low Vth. Beside materials innovation with HKMG, device structure was expanded to even 3-dimensional transistor such as FinFET for 22 nm technology [2]. Hf-based gate dielectrics (HfO2 and/or HfSiON) have been selected due to their excellent thermal and appropriate electrical properties. However, in general, for CMOS device integration, symmetric and low Vth with scaled EOT is required. Scaling EOT and lowering Vth are difficult to achieve simultaneously in HKMG tech⇑ Corresponding author. Tel.: + 82 2 2220 0383; fax: + 82 2 2220 0389. E-mail address: [email protected] (C. Choi). 0167-9317/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2013.03.056
nology. For example, unlike SiO2 gate dielectric, the high-k gate dielectrics suffer from thermally-induced oxygen vacancy defects, leading to VFB/Vth roll-off and reliability problems [3,4]. High temperature process through integration causes oxygen out-diffusion from high-k gate dielectrics and generates defects related to oxygen vacancy during conventional GF process as shown in the following equation.
1 Oo ! V2þ o þ 2e þ O2 2 where Oo is the oxygen atom at the oxygen site and V2þ o is the oxygen vacancy in high-k gate dielectrics, respectively. This positively charged oxygen vacancy generated during the high temperature process limits to attain high effective work-function and/or low Vth (=high VFB) in pMOS devices. This thermal instability with Vth/ VFB in pMOS makes it difficult to fabricate CMOS with symmetric and low Vth. Therefore, integration scheme has been divided into two different integration ways like GF and GL to meet required specifications of each device [5–7]. For example, high thermal budge processing steps can be intentionally avoidable for gate stack in GL to improve thermal stability of Vth/VFB. As for metal gate, regardless of integration schemes, TiN has been popularly considered as a metal gate electrode in the HKMG technology [8–10]. Even though numerous studies on TiN have been reported, there are few reports on the systematic investigation on the effects of composition and thickness of TiN metal gate on EOT and VFB in MOS devices. In this study, we present VFB modulation and EOT scaling by just varying composition and thickness of TiN metal gate in MOS devices, which could pave the way to attain simple GF-based CMOS
161
S.-H. Lee et al. / Microelectronic Engineering 109 (2013) 160–162
Si substrate pre-clean (chemical oxide) High-k gate dielectric deposition : ALD HfO2, Sputtered HfSiON Post deposition anneals at N2 or NH3 ambients TiN metal gate deposition : gas flow & thickness modulation Si cap anneal W capping Gate patterning
Si removal
Al backside contact & forming gas anneal
Fig. 1. MOS device fabrication steps using ALD HfO2 and sputtered HfSiON gate dielectrics with nitrogen-modulated TiN metal gate.
integration scheme applicable to potential low power devices and peripheral transistor for DRAM.
Fig. 3. C–V characteristics for gate first processed HfO2-device as a function of gas flow ratios in TiN metal gate.
2. Experiment 0.45
3. Result and Discussion Fig. 3 shows C–V characteristics of TiN gated- MOS devices with ALD HfO2. TiN with the lowest [N2]/[[Ar] + [N2]] ratio (=Ti-rich TiN,
50 mV shift 0.40
VFB (V)
HKMG MOS capacitors were fabricated using atomic layer deposition (ALD) and sputtering systems as shown in Fig. 1. After device isolation and interface preparation, ALD HfO2 and sputtered HfSiON gate dielectrics were prepared. On the chemically treated SiO2 interfacial layer, HfO2 was deposited with TEMA-Hf and H2O for precursor and oxidant at 300 °C, respectively. ALD process sequence is shown in Fig. 2. Post deposition annealing was carried out at 650 °C for 30 s in N2 ambient. For HfSiON, HfSi target (99.99%) was sputtered, followed by NH3 furnace annealing at 500 °C. Then, TiN metal gate was sputtered by varying Ar and N2 gas flow rates and changing deposition time. [N2]/[N2] + [Ar] ratios were varied from 0.3 to 0.8. To mimic GF process with our MOS devices, devices were with chemically vapor deposited Si as a capping layer, followed by rapid thermal annealing at 1000 °C for 5 s in N2 ambient. Then, Si capping layer was finally removed by wet method before testing. For thickness variation experiment, TiN thickness was varied from 2.5 to 10.0 nm. Tungsten was used for final capping metal. After gate patterning, backside Al deposition for the good ohmic contact and final forming gas annealing were carried out in a 95 % N2/5 % H2 at 450 °C for 30 min. The electrical properties were characterized by capacitance voltage (C–V) measurement at a frequency of 100 kHz before and after FGA using an Agilent E4980A CV-meter and a HP 4145B parameter analyzer.
0.35
0.30
120 mV shift
0.25
HfO 2 0.20
0.8
0.7
0.6
HfSiON 0.5
0.4
0.3
N2 / N 2 +[Ar] Fig. 4. Flat-band voltage behaviors for MOS devices using HfO2 and HfSiON gate dielectrics and TiN metal gate, where nitrogen and argon gas ratios were varied during deposition.
ratio = 0.3) shows the highest accumulation capacitance (= thinnest EOT scaling) with lower VFB while TiN with the highest [N2]/ [[Ar] + [N2]] ratio (=N-rich TiN, ratio = 0.8) exhibits positive VFB with relatively thicker EOT. This behavior could be explained by oxygen vacancy generation in high-k gate dielectrics as a result of oxygen scavenging within gate stack. For more metallic TiN, more Ti element in metal gate electrode scavenges excess oxygen, a culprit of EOT degradation in HKMG gate stack, leading to thinning interfacial layer (EOT scaling). Positive VFB shift with increas-
Fig. 2. ALD HfO2 process sequences.
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S.-H. Lee et al. / Microelectronic Engineering 109 (2013) 160–162
2.4 2.3 2.2
0.3 nm
HfSiON
EOT (nm)
2.1 2.0 1.9 1.8
0.4-0.5 nm
1.7
HfO2
1.6 1.5
0.8
0.7
0.6
0.5
0.4
0.3
N2 / N2 +[Ar] Fig. 5. EOT dependence of MOS devices using HfO2 and HfSiON gate dielectrics and TiN metal gate with various compositions.
pared with HfO2 device. Gas flow ratios also affect EOT scaling substantially. Fig. 5 represents EOT variations as a function of gas flow ratios for devices with HfO2 and HfSiON gate dielectrics. For HfO2, Ti-rich TiN scales EOT down to about 1.6 nm and nitrogen-modulated TiN scales EOT by 0.4–0.5 nm thickness range for HfO2. For HfSiON, impacts of gas flow rates are similar to those of HfO2. However, as like VFB shifts, EOT scaling is not as high as HfO2 gate dielectric. Difference in EOT scaling between the lowest gas flow ratio and the highest one is 0.3 nm. These smaller gains in both VFB shift and EOT scaling with HfSiON stems from Hf-Si bonding. Strong Hf-Si bonds in HfSiON gate dielectric cause smaller scavenging, leading to less oxygen vacancy generation compared with HfO2. Besides composition effects on electrical properties, TiN thickness has also strong impacts on both VFB and EOT. Fig. 6 shows that thicker TiN shows more positive VFB shift. It is demonstrated that VFB is shifted by about 150 mV as a result of varying inserted TiN thickness, which is ascribed to different composition and amount of initial oxygen incorporated TiN. As aforementioned, GF and GL integration schemes could be chosen depending on device applications. Our results suggests that for simple CMOS integration scheme, more metallic and thinner TiN is compatible with nMOS metal gate while N-rich and thicker TiN is appropriate for pMOS metal gate as proposed in Fig. 7. 4. Conclusions
Fig. 6. Flat-band voltage dependence on TiN thickness of HfO2-device. Thk 1 through thk 4 are with 2.5, 5.0, 7.5, and 10.0 nm, respectively.
For HfO2 device, TiN using the lower [N2]/[[Ar] + [N2]] gas flow ratio shows more EOT scaling with lower VFB while the nitrogenrich TiN exhibits more positive VFB shift with relatively thicker EOT. By varying gas flow rates simply, we could tune VFB by about 120 mV and reduce EOT further by 0.4–0.5 nm for HfO2, which can be enough for low power applications. Varying TiN thickness also affects VFB shift by 150 mV between 2.5 and 10.0 nm thickness ranges in our case. For HfSiON gate dielectric, amount of VFB shift and EOT scaling depending on gas flow ratios is similar to HfO2 case, but values are smaller than those of HfO2 device, indicating that HfSiON has a stronger immunity to oxygen vacancy generation due to Hf-Si bonding. Acknowledgements This research was supported by the IT R&D program of MKE/ KEIT (10039174, Technology Development of 22 nm level Foundry Device and PDK) and this work was also supported by an Inha university research grant. References
Fig. 7. Proposed integration scheme using varying composition and thickness of TiN metal gate for low power and peripheral transistor of DRAM devices.
ing N content in TiN can be attributed to modulated work-function due to crystallinity or grain size change, resulting from excess nitrogen during TiN deposition. Fig. 4 clearly shows the dependence of composition in TiN on the VFB. VFB tunability with about 120 mV is demonstrated by only nitrogen modulation in the GFprocessed TiN device. For alternative HfSiON gate dielectric, VFB dependence on gas flow ratios during TiN deposition is similar to HfO2 case. However, smaller VFB shift (50 mV) is attained com-
[1] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, et al., IEDM Tech. Dig. (2007) 247. [2] Intel, www.intel.com/technology/architecture-silicon/22nm/index.html. [3] G. Bersuker, C.S. Park, H.C. Wen, K. Choi, O. Sharia, A. Demkov, Eur. Solid State Device Res. Conf. (ESSDERC), 2008, p. 134. [4] C. Choi, Microelec. Eng. 86 (2009) 1737. [5] P. Packan, S. Akbar, M. Armstrong, D. Bergstrom, M. Brazier, et al., Int. Electron Devices Meet. (IEDM), 2009, p. 659. [6] D.-G. Park, X. Wang, ECS Trans. 28 (2010) 39. [7] M. Chudzik, B. Doris, R. Mo, J. Sleight, E. Cartier, et al., Symp. VLSI Technol. (VLSI), 2007, p. 197. [8] D.H. Lee, K.H. Yeom, M.H. Cho, N.S. Kang, T.E, Shim, Symp. VLSI Tech, 1996, p. 208. [9] Y. Sugimoto, M. Kajiwara, K. Yamamoto, Y. Suehiro, D. Wang, H. Hakashima, Appl. Phys. Lett. 91 (2007) 112105. [10] S.C. Heo, C. Choi, Microelectron. Eng. 94 (2012) 11.
Contents lists available at SciVerse ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Effects of composition and thickness of TiN metal gate on the equivalent oxide thickness and flat-band voltage in metal oxide semiconductor devices Seok-Hee Lee a, Rino Choi b, Changhwan Choi c,⇑ a
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Republic of Korea School of Materials Science and Engineering, Inha University, Incheon 402-751, Republic of Korea c Division of Materials Science and Engineering, Hanyang University, Seoul 133-791, Republic of Korea b
a r t i c l e
i n f o
Article history: Available online 27 March 2013 Keywords: High-j gate dielectric Metal gate Flat-band voltage CMOS integration
a b s t r a c t We investigated the effects of gas flow rates during sputtering and thickness of TiN metal gate on the equivalent oxide thickness (EOT) and flat band voltage (VFB) in the gate-first (GF) processed metal oxide semiconductor (MOS) devices with HfO2 and HfSiON-based gate dielectrics. For both HfO2 and HfiSON devices, more metallic TiN causes thinner EOT with lower VFB while higher VFB is observed along with thicker EOT for nitrogen-rich TiN case. Also, thicker TiN induces more positive VFB shift. However, for HfSiON, amount of VFB shift and EOT reduction is smaller than those of HfO2-based device, resulting from stronger immunity of Hf-Si bonding against oxygen vacancy generation during thermal process. Ó 2013 Elsevier B.V. All rights reserved.
1. Introduction Improved transistor performance and reduced power consumption have been continuously achieved by scaling device dimensions in conjunction with adopting alternative materials and integration schemes. Among them, high-k gate dielectric/metal gate (HKMG) technology has been suggested to enhance device functionality and lower power dissipation. Since 45 nm technology node, HKMG technology have been firstly implemented into commercial Si chip products using gate last (GL) integration process scheme, called replacement gate process [1]. However, considering process cost and complexity, GL process may not be necessary for low power mobile devices where leakage reduction is more important parameter than performance enhancement. Also, threshold voltage (Vth) requirement of peripheral transistor for dynamic random access memory (DRAM) device is not as strict as high performance applications. Therefore, conventional GF integration scheme is still attractive to devices aforementioned if HKMG gate stack meets device requirements for complementary metal oxide semiconductor (CMOS) such as symmetric low Vth. Beside materials innovation with HKMG, device structure was expanded to even 3-dimensional transistor such as FinFET for 22 nm technology [2]. Hf-based gate dielectrics (HfO2 and/or HfSiON) have been selected due to their excellent thermal and appropriate electrical properties. However, in general, for CMOS device integration, symmetric and low Vth with scaled EOT is required. Scaling EOT and lowering Vth are difficult to achieve simultaneously in HKMG tech⇑ Corresponding author. Tel.: + 82 2 2220 0383; fax: + 82 2 2220 0389. E-mail address: [email protected] (C. Choi). 0167-9317/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2013.03.056
nology. For example, unlike SiO2 gate dielectric, the high-k gate dielectrics suffer from thermally-induced oxygen vacancy defects, leading to VFB/Vth roll-off and reliability problems [3,4]. High temperature process through integration causes oxygen out-diffusion from high-k gate dielectrics and generates defects related to oxygen vacancy during conventional GF process as shown in the following equation.
1 Oo ! V2þ o þ 2e þ O2 2 where Oo is the oxygen atom at the oxygen site and V2þ o is the oxygen vacancy in high-k gate dielectrics, respectively. This positively charged oxygen vacancy generated during the high temperature process limits to attain high effective work-function and/or low Vth (=high VFB) in pMOS devices. This thermal instability with Vth/ VFB in pMOS makes it difficult to fabricate CMOS with symmetric and low Vth. Therefore, integration scheme has been divided into two different integration ways like GF and GL to meet required specifications of each device [5–7]. For example, high thermal budge processing steps can be intentionally avoidable for gate stack in GL to improve thermal stability of Vth/VFB. As for metal gate, regardless of integration schemes, TiN has been popularly considered as a metal gate electrode in the HKMG technology [8–10]. Even though numerous studies on TiN have been reported, there are few reports on the systematic investigation on the effects of composition and thickness of TiN metal gate on EOT and VFB in MOS devices. In this study, we present VFB modulation and EOT scaling by just varying composition and thickness of TiN metal gate in MOS devices, which could pave the way to attain simple GF-based CMOS
161
S.-H. Lee et al. / Microelectronic Engineering 109 (2013) 160–162
Si substrate pre-clean (chemical oxide) High-k gate dielectric deposition : ALD HfO2, Sputtered HfSiON Post deposition anneals at N2 or NH3 ambients TiN metal gate deposition : gas flow & thickness modulation Si cap anneal W capping Gate patterning
Si removal
Al backside contact & forming gas anneal
Fig. 1. MOS device fabrication steps using ALD HfO2 and sputtered HfSiON gate dielectrics with nitrogen-modulated TiN metal gate.
integration scheme applicable to potential low power devices and peripheral transistor for DRAM.
Fig. 3. C–V characteristics for gate first processed HfO2-device as a function of gas flow ratios in TiN metal gate.
2. Experiment 0.45
3. Result and Discussion Fig. 3 shows C–V characteristics of TiN gated- MOS devices with ALD HfO2. TiN with the lowest [N2]/[[Ar] + [N2]] ratio (=Ti-rich TiN,
50 mV shift 0.40
VFB (V)
HKMG MOS capacitors were fabricated using atomic layer deposition (ALD) and sputtering systems as shown in Fig. 1. After device isolation and interface preparation, ALD HfO2 and sputtered HfSiON gate dielectrics were prepared. On the chemically treated SiO2 interfacial layer, HfO2 was deposited with TEMA-Hf and H2O for precursor and oxidant at 300 °C, respectively. ALD process sequence is shown in Fig. 2. Post deposition annealing was carried out at 650 °C for 30 s in N2 ambient. For HfSiON, HfSi target (99.99%) was sputtered, followed by NH3 furnace annealing at 500 °C. Then, TiN metal gate was sputtered by varying Ar and N2 gas flow rates and changing deposition time. [N2]/[N2] + [Ar] ratios were varied from 0.3 to 0.8. To mimic GF process with our MOS devices, devices were with chemically vapor deposited Si as a capping layer, followed by rapid thermal annealing at 1000 °C for 5 s in N2 ambient. Then, Si capping layer was finally removed by wet method before testing. For thickness variation experiment, TiN thickness was varied from 2.5 to 10.0 nm. Tungsten was used for final capping metal. After gate patterning, backside Al deposition for the good ohmic contact and final forming gas annealing were carried out in a 95 % N2/5 % H2 at 450 °C for 30 min. The electrical properties were characterized by capacitance voltage (C–V) measurement at a frequency of 100 kHz before and after FGA using an Agilent E4980A CV-meter and a HP 4145B parameter analyzer.
0.35
0.30
120 mV shift
0.25
HfO 2 0.20
0.8
0.7
0.6
HfSiON 0.5
0.4
0.3
N2 / N 2 +[Ar] Fig. 4. Flat-band voltage behaviors for MOS devices using HfO2 and HfSiON gate dielectrics and TiN metal gate, where nitrogen and argon gas ratios were varied during deposition.
ratio = 0.3) shows the highest accumulation capacitance (= thinnest EOT scaling) with lower VFB while TiN with the highest [N2]/ [[Ar] + [N2]] ratio (=N-rich TiN, ratio = 0.8) exhibits positive VFB with relatively thicker EOT. This behavior could be explained by oxygen vacancy generation in high-k gate dielectrics as a result of oxygen scavenging within gate stack. For more metallic TiN, more Ti element in metal gate electrode scavenges excess oxygen, a culprit of EOT degradation in HKMG gate stack, leading to thinning interfacial layer (EOT scaling). Positive VFB shift with increas-
Fig. 2. ALD HfO2 process sequences.
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S.-H. Lee et al. / Microelectronic Engineering 109 (2013) 160–162
2.4 2.3 2.2
0.3 nm
HfSiON
EOT (nm)
2.1 2.0 1.9 1.8
0.4-0.5 nm
1.7
HfO2
1.6 1.5
0.8
0.7
0.6
0.5
0.4
0.3
N2 / N2 +[Ar] Fig. 5. EOT dependence of MOS devices using HfO2 and HfSiON gate dielectrics and TiN metal gate with various compositions.
pared with HfO2 device. Gas flow ratios also affect EOT scaling substantially. Fig. 5 represents EOT variations as a function of gas flow ratios for devices with HfO2 and HfSiON gate dielectrics. For HfO2, Ti-rich TiN scales EOT down to about 1.6 nm and nitrogen-modulated TiN scales EOT by 0.4–0.5 nm thickness range for HfO2. For HfSiON, impacts of gas flow rates are similar to those of HfO2. However, as like VFB shifts, EOT scaling is not as high as HfO2 gate dielectric. Difference in EOT scaling between the lowest gas flow ratio and the highest one is 0.3 nm. These smaller gains in both VFB shift and EOT scaling with HfSiON stems from Hf-Si bonding. Strong Hf-Si bonds in HfSiON gate dielectric cause smaller scavenging, leading to less oxygen vacancy generation compared with HfO2. Besides composition effects on electrical properties, TiN thickness has also strong impacts on both VFB and EOT. Fig. 6 shows that thicker TiN shows more positive VFB shift. It is demonstrated that VFB is shifted by about 150 mV as a result of varying inserted TiN thickness, which is ascribed to different composition and amount of initial oxygen incorporated TiN. As aforementioned, GF and GL integration schemes could be chosen depending on device applications. Our results suggests that for simple CMOS integration scheme, more metallic and thinner TiN is compatible with nMOS metal gate while N-rich and thicker TiN is appropriate for pMOS metal gate as proposed in Fig. 7. 4. Conclusions
Fig. 6. Flat-band voltage dependence on TiN thickness of HfO2-device. Thk 1 through thk 4 are with 2.5, 5.0, 7.5, and 10.0 nm, respectively.
For HfO2 device, TiN using the lower [N2]/[[Ar] + [N2]] gas flow ratio shows more EOT scaling with lower VFB while the nitrogenrich TiN exhibits more positive VFB shift with relatively thicker EOT. By varying gas flow rates simply, we could tune VFB by about 120 mV and reduce EOT further by 0.4–0.5 nm for HfO2, which can be enough for low power applications. Varying TiN thickness also affects VFB shift by 150 mV between 2.5 and 10.0 nm thickness ranges in our case. For HfSiON gate dielectric, amount of VFB shift and EOT scaling depending on gas flow ratios is similar to HfO2 case, but values are smaller than those of HfO2 device, indicating that HfSiON has a stronger immunity to oxygen vacancy generation due to Hf-Si bonding. Acknowledgements This research was supported by the IT R&D program of MKE/ KEIT (10039174, Technology Development of 22 nm level Foundry Device and PDK) and this work was also supported by an Inha university research grant. References
Fig. 7. Proposed integration scheme using varying composition and thickness of TiN metal gate for low power and peripheral transistor of DRAM devices.
ing N content in TiN can be attributed to modulated work-function due to crystallinity or grain size change, resulting from excess nitrogen during TiN deposition. Fig. 4 clearly shows the dependence of composition in TiN on the VFB. VFB tunability with about 120 mV is demonstrated by only nitrogen modulation in the GFprocessed TiN device. For alternative HfSiON gate dielectric, VFB dependence on gas flow ratios during TiN deposition is similar to HfO2 case. However, smaller VFB shift (50 mV) is attained com-
[1] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, et al., IEDM Tech. Dig. (2007) 247. [2] Intel, www.intel.com/technology/architecture-silicon/22nm/index.html. [3] G. Bersuker, C.S. Park, H.C. Wen, K. Choi, O. Sharia, A. Demkov, Eur. Solid State Device Res. Conf. (ESSDERC), 2008, p. 134. [4] C. Choi, Microelec. Eng. 86 (2009) 1737. [5] P. Packan, S. Akbar, M. Armstrong, D. Bergstrom, M. Brazier, et al., Int. Electron Devices Meet. (IEDM), 2009, p. 659. [6] D.-G. Park, X. Wang, ECS Trans. 28 (2010) 39. [7] M. Chudzik, B. Doris, R. Mo, J. Sleight, E. Cartier, et al., Symp. VLSI Technol. (VLSI), 2007, p. 197. [8] D.H. Lee, K.H. Yeom, M.H. Cho, N.S. Kang, T.E, Shim, Symp. VLSI Tech, 1996, p. 208. [9] Y. Sugimoto, M. Kajiwara, K. Yamamoto, Y. Suehiro, D. Wang, H. Hakashima, Appl. Phys. Lett. 91 (2007) 112105. [10] S.C. Heo, C. Choi, Microelectron. Eng. 94 (2012) 11.