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Effect of oxide growth temperature on the electrical performance of extremely thin (∼3 nm) wet oxides of silicon
Materials Science and Engineering B98 (2003) 140 /143 www.elsevier.com/locate/mseb
Effect of oxide growth temperature on the electrical performance of extremely thin ( 3 nm) wet oxides of silicon /
Vishwanath Krishna Bhat a, K.N. Bhat b, A. Subrahmanyam a,* a
b
Department of Physics, Indian Institute of Technology, Madras 600 036, India Department of Electrical Engineering, Indian Institute of Technology, Madras 600 036, India Received 30 August 2002
Abstract In the present investigation, extremely thin (/3 nm) oxides of silicon are grown by using wet oxidation technique in the temperature range 600 /900 8C. The capacitance /voltage, current /voltage and charge trapping characteristics are used to study the electrical properties of these thin oxides. The results show that the electrical performance of the extremely thin oxide improves with the increase in the oxide growth temperature. # 2003 Elsevier Science B.V. All rights reserved. Keywords: Wet oxidation; Thin silicon dioxide
Extremely thin (/3 nm) oxides of silicon are required for the ultra large scale integration (ULSI) applications such as submicron MOS transistors and 1 G-bit DRAMs. Hence the growth and characterization of the extremely thin oxides with good electrical properties became the subject of intensive study [1 /4]. The requirement for extremely thin oxide with good electrical performance places stringent demands on the oxidation techniques used to grow these oxides. In general, the thin oxides of silicon are grown by reducing the oxide growth temperature [5], by diluting the oxidant gas by nitrogen [6] or by reducing the oxidant gas pressure [7]. Even though the thermal budget consideration favors the reduction in the oxide growth temperature, the electrical quality of these extremely thin oxide films need to be examined with respect to the oxide growth temperature. In this letter, we report the effect of growth temperature (600 /900 8C) on the electrical performance of extremely thin (/3 nm) oxides of silicon. The extremely thin oxides of silicon are grown by wet oxidation technique, these thin oxides are
* Corresponding author. Tel.: /91-44-445-8671; fax: /91-44-2350509. E-mail addresses: [email protected], [email protected] (A. Subrahmanyam).
characterized by capacitance /voltage (C /V ), current / voltage (I /V ) and charge trapping characteristics. In the present study, single crystal silicon (100) oriented, n-type, and having a resistivity of 1/10 V cm are used. The wafers are cleaned by the sacrificial oxide growth method [8]. Then the extremely thin oxides of silicon are grown on these wafers by using wet oxidation in the temperature range of 600/900 8C. The details about the oxidation setup used are given in Ref. [9]. The oxidation duration is adjusted such that the oxide thickness is about 3 nm. In order to characterize the oxides, the MOS tunnel diodes, fabricated by thermal evaporation of aluminum using a metal shadow mask, are used. The circular diode area is 0.002 cm2. In this study, the main emphasis is to study the electrical properties of the as grown oxides, hence MOS tunnel diodes are not subjected to post metallization annealing (PMA). The C /V measurements in the frequency range 10 kHz to 1 MHz are carried out using an automated HP 4275 A LCR meter. An automated Keithley 238 High Current Source Measure Unit (SMU) is used for the I /V and the constant current stress (CCS) measurements of the tunnel diodes. Fig. 1 gives the C /V characteristics (10 kHz and 1 MHz) of the MOS tunnel diodes with the oxide grown at 900 8C. The observed frequency dependence of accu-
0921-5107/03/$ - see front matter # 2003 Elsevier Science B.V. All rights reserved. doi:10.1016/S0921-5107(02)00757-2
V.K. Bhat et al. / Materials Science and Engineering B98 (2003) 140 /143
Fig. 1. C /V characteristics at 10 kHz and 1 MHz for the MOS tunnel diodes with oxide grown at 900 8C.
mulation capacitance is attributed to the presence of series resistance in the device structure [10]. It is found that the effect of series resistance is negligible when the C /V measurement is done at 10 kHz [11]. Hence the 10 kHz C /V characteristics are used to estimate the thickness of the extremely thin oxides following the method proposed by Maserjian [12]. The estimated oxide thickness in all the cases is in the range 2.8 /3.0 nm. The 10 kHz C /V characteristics of the MOS tunnel diodes with oxide grown at different temperatures and having oxide thickness of about 3 nm are given in Fig. 2; the dotted line represents the ideal curve. The ideal curve
Fig. 2. 10 kHz C /V characteristics of the MOS tunnel diodes with oxide grown at different temperatures.
141
is calculated using the standard method [10]. It may be seen from the Fig. 2, the C /V curve for the oxide grown at 900 8C is the closest to the ideal curve: with the decrease in the growth temperature, the C /V curves deviate from the ideal curve. This observation may be attributed to the increase in the fixed oxide charge density with the decrease in the oxide growth temperature. Similar results have been reported in the literature for thicker oxides of silicon [10]. It is also seen that the slope of the C /V curve in the depletion region decreases with the decrease in the growth temperature, leading to the stretch out of the C /V curves along the voltage axis. The increase in the stretch out of the C /V curves suggests an increase in the interface state density with the decrease in the oxide growth temperature. Fig. 3 gives the C /V characteristics at 10 kHz and 1 MHz for the tunnel diodes with oxide grown at 900 and 600 8C. The observed frequency dependence of capacitance in the depletion region of the C /V curves may be attributed to the presence of interface states at the Si / SiO2, interface [10]. When the measurement frequency is 10 kHz, the interface states can respond to the measurement signal. Hence, the capture and emission of interface charges behave like a capacitor, which is added in parallel with the Si depletion capacitance, resulting in an increase of total capacitance (10 kHz). When the measurement frequency is 1 MHz, fewer interface states are able to follow the test signal. Consequently, the capacitance associated with the interface state decreases resulting in the decrease in the total capacitance. Hence, for a given value of the bias voltage the capacitance is higher for the case of 10 kHz compared to that of 1 MHz measurement. In addition, interface capacitance also depends on the density of the interface states. A higher interface state density causes larger frequency
Fig. 3. C /V characteristics (depletion region) at 10 kHz and 1 MHz for the MOS tunnel diodes with oxide grown at 900 and 600 8C.
V.K. Bhat et al. / Materials Science and Engineering B98 (2003) 140 /143
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dispersion. It can be noted from Fig. 3 that the frequency dispersion is more pronounced in the case of the oxide grown at 600 8C compared to that of the oxide grown at 900 8C. This result demonstrates the presence of large density of interface states in the oxide grown at 600 8C compared to that grown at 900 8C. The extracted values of interface state density (Dit) and the fixed oxide charge density (Qf) are presented in Table 1. It may be seen that Dit and Qf decreases with the increase in the oxide growth temperature. This result is in good agreement with the results obtained for the thicker oxides reported in literature [10]. The I /V characteristics of the MOS tunnel diodes with the oxide layer grown at different temperatures are given in Fig. 4. It may be seen from the Fig. 4 that the tunnel current density increases with the decrease in the oxide growth temperature. The MOS tunnel diodes with oxide grown at 600 8C exhibited a tunnel current density more than two orders of magnitude higher compared to that grown at 900 8C even though the oxide thickness in all the cases are identical ( /3 nm). This increased tunnel current density with the decrease in the oxide growth temperature may be due to the increased trap assisted tunneling in these oxides [13]. The charge trapping characteristics of the extremely thin oxides is studied by CCS technique. In this CCS measurement constant current density of 25 mA cm 2 is maintained across the oxide and the change in gate voltage with stress duration is recorded. Fig. 5 gives the charge trapping characteristics of the MOS tunnel diodes with oxides grown at different temperatures. In all the cases, the change in the gate voltage (DVg) is negative corresponding to positive charge trapping [14]. It may be noted that the gate-voltage-decrease is more pronounced in the case of oxides grown at lower temperatures, indicating the enhanced positive charge trapping in these cases. The plausible explanation for the improvement in the electrical performance of the extremely thin oxides of silicon with the increase in the oxide growth temperature could be the decreased interfacial strain with the increase in the oxide growth temperature. According to the viscoelastic theory of SiO2 [15] higher the temperature, the more feasible is the relaxation of the
Fig. 4. J /V characteristics of the MOS tunnel diodes with oxide grown at different temperatures.
Fig. 5. Charge trapping characteristics of the MOS tunnel diodes with oxide grown at different temperatures.
Table 1 Values of interface state density (Dit), fixed oxide charge density (Qf), tunnel current density at the gate bias of 1 V (JT) and change in gate voltage at the end of 5 min stress duration (DVg) for the oxide grown at different temperatures (Tox) Tox (8C)
Dit (1011 cm 2 eV 1)
Qf (1012 cm 2)
JT at 1 V gate bias (mA cm 2)
DVg after 5 min of stress (mV)
600 700 800 900
4.3 4.1 3.3 1.8
5.1 3.7 2.1 1.2
18.06 1.97 0.45 0.21
/80 /69 /49 /37
V.K. Bhat et al. / Materials Science and Engineering B98 (2003) 140 /143
intrinsic stress that is expected to build up in the Si /SiO2 interface as a consequence of the volume expansion that accompanies the conversion of Si into SiO2. This relaxation takes place as the oxidation reaction proceeds and higher oxidation temperature results in a more relaxed oxide structure. In conclusion, electrical performance of the extremely thin ( /3 nm) oxides of silicon grown at wide temperature range (600 /900 8C) are compared. It is shown that the interface state density (Dit), fixed oxide charge density (Qf), tunnel current density (JT) and charge trapping (DVg) can be drastically reduced by choosing a higher oxidation temperature.
Acknowledgements One of the authors V.K. Bhat acknowledges the support (Senior Research Fellowship) of the Council of Scientific and Industrial Research (CSIR), New Delhi, India in carrying out this work.
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References [1] E.A. Irene, Crit. Rev. Solid State Mater. Sci. 14 (1988) 175. [2] T. Hattori, Crit. Rev. Solid State Mater. Sci. 20 (1995) 339. [3] C. Sofield, A.M. Stoneham, Semicond. Sci. Technol. 10 (1995) 215. [4] D.A. Buchanan, IBM J. Res. Develop. 43 (1999) 245. [5] A.M. Goodman, J.M. Breece, J. Electrochem. Sec. 117 (1970) 982. [6] Y. Kramigaki, Y. ltoh, J. Appl. Phys. 48 (1977) 2891. [7] A.C. Adams, T.E. Smith, C.C. Chang, J. Electrochem. Soc. 127 (1980) 1788. [8] V.K. Bhat, K.N. Bhat, A. Subrahamanyam, Semicond. Sci. Technol. 14 (1999) 705. [9] V.K. Bhat, M. Pattabiraman, K.N. Bhat, A. Subrahamanyam, Mater. Res. Bull. 34 (1999) 1797. [10] E.H. Nicollian, J.R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, John Wiley and Sons, New York, 1982. [11] V.K. Bhat, K.N. Bhat, A. Subrahamanyam, Semicond. Sci. Technol. 15 (2000) 883. [12] J. Maserjian, in: C.R. Helms, B.E. Deal (Eds.), The Physics and Chemistry of SiO2 and the Si /SiO2 interface, New York: Plenum Press, 1988, p. 497. [13] B. Ricco, G. Gozzi, M. Lanzoni, IEEE Trans. Electron Devices 45 (1998) 1554. [14] A. Martin, P. O’Sullivan, A. Mathewson, Microelectron. Reliability 38 (1998) 37. [15] E.P Eernisse, Appl. Phys. Lett. 30 (1977) 290.
Effect of oxide growth temperature on the electrical performance of extremely thin ( 3 nm) wet oxides of silicon /
Vishwanath Krishna Bhat a, K.N. Bhat b, A. Subrahmanyam a,* a
b
Department of Physics, Indian Institute of Technology, Madras 600 036, India Department of Electrical Engineering, Indian Institute of Technology, Madras 600 036, India Received 30 August 2002
Abstract In the present investigation, extremely thin (/3 nm) oxides of silicon are grown by using wet oxidation technique in the temperature range 600 /900 8C. The capacitance /voltage, current /voltage and charge trapping characteristics are used to study the electrical properties of these thin oxides. The results show that the electrical performance of the extremely thin oxide improves with the increase in the oxide growth temperature. # 2003 Elsevier Science B.V. All rights reserved. Keywords: Wet oxidation; Thin silicon dioxide
Extremely thin (/3 nm) oxides of silicon are required for the ultra large scale integration (ULSI) applications such as submicron MOS transistors and 1 G-bit DRAMs. Hence the growth and characterization of the extremely thin oxides with good electrical properties became the subject of intensive study [1 /4]. The requirement for extremely thin oxide with good electrical performance places stringent demands on the oxidation techniques used to grow these oxides. In general, the thin oxides of silicon are grown by reducing the oxide growth temperature [5], by diluting the oxidant gas by nitrogen [6] or by reducing the oxidant gas pressure [7]. Even though the thermal budget consideration favors the reduction in the oxide growth temperature, the electrical quality of these extremely thin oxide films need to be examined with respect to the oxide growth temperature. In this letter, we report the effect of growth temperature (600 /900 8C) on the electrical performance of extremely thin (/3 nm) oxides of silicon. The extremely thin oxides of silicon are grown by wet oxidation technique, these thin oxides are
* Corresponding author. Tel.: /91-44-445-8671; fax: /91-44-2350509. E-mail addresses: [email protected], [email protected] (A. Subrahmanyam).
characterized by capacitance /voltage (C /V ), current / voltage (I /V ) and charge trapping characteristics. In the present study, single crystal silicon (100) oriented, n-type, and having a resistivity of 1/10 V cm are used. The wafers are cleaned by the sacrificial oxide growth method [8]. Then the extremely thin oxides of silicon are grown on these wafers by using wet oxidation in the temperature range of 600/900 8C. The details about the oxidation setup used are given in Ref. [9]. The oxidation duration is adjusted such that the oxide thickness is about 3 nm. In order to characterize the oxides, the MOS tunnel diodes, fabricated by thermal evaporation of aluminum using a metal shadow mask, are used. The circular diode area is 0.002 cm2. In this study, the main emphasis is to study the electrical properties of the as grown oxides, hence MOS tunnel diodes are not subjected to post metallization annealing (PMA). The C /V measurements in the frequency range 10 kHz to 1 MHz are carried out using an automated HP 4275 A LCR meter. An automated Keithley 238 High Current Source Measure Unit (SMU) is used for the I /V and the constant current stress (CCS) measurements of the tunnel diodes. Fig. 1 gives the C /V characteristics (10 kHz and 1 MHz) of the MOS tunnel diodes with the oxide grown at 900 8C. The observed frequency dependence of accu-
0921-5107/03/$ - see front matter # 2003 Elsevier Science B.V. All rights reserved. doi:10.1016/S0921-5107(02)00757-2
V.K. Bhat et al. / Materials Science and Engineering B98 (2003) 140 /143
Fig. 1. C /V characteristics at 10 kHz and 1 MHz for the MOS tunnel diodes with oxide grown at 900 8C.
mulation capacitance is attributed to the presence of series resistance in the device structure [10]. It is found that the effect of series resistance is negligible when the C /V measurement is done at 10 kHz [11]. Hence the 10 kHz C /V characteristics are used to estimate the thickness of the extremely thin oxides following the method proposed by Maserjian [12]. The estimated oxide thickness in all the cases is in the range 2.8 /3.0 nm. The 10 kHz C /V characteristics of the MOS tunnel diodes with oxide grown at different temperatures and having oxide thickness of about 3 nm are given in Fig. 2; the dotted line represents the ideal curve. The ideal curve
Fig. 2. 10 kHz C /V characteristics of the MOS tunnel diodes with oxide grown at different temperatures.
141
is calculated using the standard method [10]. It may be seen from the Fig. 2, the C /V curve for the oxide grown at 900 8C is the closest to the ideal curve: with the decrease in the growth temperature, the C /V curves deviate from the ideal curve. This observation may be attributed to the increase in the fixed oxide charge density with the decrease in the oxide growth temperature. Similar results have been reported in the literature for thicker oxides of silicon [10]. It is also seen that the slope of the C /V curve in the depletion region decreases with the decrease in the growth temperature, leading to the stretch out of the C /V curves along the voltage axis. The increase in the stretch out of the C /V curves suggests an increase in the interface state density with the decrease in the oxide growth temperature. Fig. 3 gives the C /V characteristics at 10 kHz and 1 MHz for the tunnel diodes with oxide grown at 900 and 600 8C. The observed frequency dependence of capacitance in the depletion region of the C /V curves may be attributed to the presence of interface states at the Si / SiO2, interface [10]. When the measurement frequency is 10 kHz, the interface states can respond to the measurement signal. Hence, the capture and emission of interface charges behave like a capacitor, which is added in parallel with the Si depletion capacitance, resulting in an increase of total capacitance (10 kHz). When the measurement frequency is 1 MHz, fewer interface states are able to follow the test signal. Consequently, the capacitance associated with the interface state decreases resulting in the decrease in the total capacitance. Hence, for a given value of the bias voltage the capacitance is higher for the case of 10 kHz compared to that of 1 MHz measurement. In addition, interface capacitance also depends on the density of the interface states. A higher interface state density causes larger frequency
Fig. 3. C /V characteristics (depletion region) at 10 kHz and 1 MHz for the MOS tunnel diodes with oxide grown at 900 and 600 8C.
V.K. Bhat et al. / Materials Science and Engineering B98 (2003) 140 /143
142
dispersion. It can be noted from Fig. 3 that the frequency dispersion is more pronounced in the case of the oxide grown at 600 8C compared to that of the oxide grown at 900 8C. This result demonstrates the presence of large density of interface states in the oxide grown at 600 8C compared to that grown at 900 8C. The extracted values of interface state density (Dit) and the fixed oxide charge density (Qf) are presented in Table 1. It may be seen that Dit and Qf decreases with the increase in the oxide growth temperature. This result is in good agreement with the results obtained for the thicker oxides reported in literature [10]. The I /V characteristics of the MOS tunnel diodes with the oxide layer grown at different temperatures are given in Fig. 4. It may be seen from the Fig. 4 that the tunnel current density increases with the decrease in the oxide growth temperature. The MOS tunnel diodes with oxide grown at 600 8C exhibited a tunnel current density more than two orders of magnitude higher compared to that grown at 900 8C even though the oxide thickness in all the cases are identical ( /3 nm). This increased tunnel current density with the decrease in the oxide growth temperature may be due to the increased trap assisted tunneling in these oxides [13]. The charge trapping characteristics of the extremely thin oxides is studied by CCS technique. In this CCS measurement constant current density of 25 mA cm 2 is maintained across the oxide and the change in gate voltage with stress duration is recorded. Fig. 5 gives the charge trapping characteristics of the MOS tunnel diodes with oxides grown at different temperatures. In all the cases, the change in the gate voltage (DVg) is negative corresponding to positive charge trapping [14]. It may be noted that the gate-voltage-decrease is more pronounced in the case of oxides grown at lower temperatures, indicating the enhanced positive charge trapping in these cases. The plausible explanation for the improvement in the electrical performance of the extremely thin oxides of silicon with the increase in the oxide growth temperature could be the decreased interfacial strain with the increase in the oxide growth temperature. According to the viscoelastic theory of SiO2 [15] higher the temperature, the more feasible is the relaxation of the
Fig. 4. J /V characteristics of the MOS tunnel diodes with oxide grown at different temperatures.
Fig. 5. Charge trapping characteristics of the MOS tunnel diodes with oxide grown at different temperatures.
Table 1 Values of interface state density (Dit), fixed oxide charge density (Qf), tunnel current density at the gate bias of 1 V (JT) and change in gate voltage at the end of 5 min stress duration (DVg) for the oxide grown at different temperatures (Tox) Tox (8C)
Dit (1011 cm 2 eV 1)
Qf (1012 cm 2)
JT at 1 V gate bias (mA cm 2)
DVg after 5 min of stress (mV)
600 700 800 900
4.3 4.1 3.3 1.8
5.1 3.7 2.1 1.2
18.06 1.97 0.45 0.21
/80 /69 /49 /37
V.K. Bhat et al. / Materials Science and Engineering B98 (2003) 140 /143
intrinsic stress that is expected to build up in the Si /SiO2 interface as a consequence of the volume expansion that accompanies the conversion of Si into SiO2. This relaxation takes place as the oxidation reaction proceeds and higher oxidation temperature results in a more relaxed oxide structure. In conclusion, electrical performance of the extremely thin ( /3 nm) oxides of silicon grown at wide temperature range (600 /900 8C) are compared. It is shown that the interface state density (Dit), fixed oxide charge density (Qf), tunnel current density (JT) and charge trapping (DVg) can be drastically reduced by choosing a higher oxidation temperature.
Acknowledgements One of the authors V.K. Bhat acknowledges the support (Senior Research Fellowship) of the Council of Scientific and Industrial Research (CSIR), New Delhi, India in carrying out this work.
143
References [1] E.A. Irene, Crit. Rev. Solid State Mater. Sci. 14 (1988) 175. [2] T. Hattori, Crit. Rev. Solid State Mater. Sci. 20 (1995) 339. [3] C. Sofield, A.M. Stoneham, Semicond. Sci. Technol. 10 (1995) 215. [4] D.A. Buchanan, IBM J. Res. Develop. 43 (1999) 245. [5] A.M. Goodman, J.M. Breece, J. Electrochem. Sec. 117 (1970) 982. [6] Y. Kramigaki, Y. ltoh, J. Appl. Phys. 48 (1977) 2891. [7] A.C. Adams, T.E. Smith, C.C. Chang, J. Electrochem. Soc. 127 (1980) 1788. [8] V.K. Bhat, K.N. Bhat, A. Subrahamanyam, Semicond. Sci. Technol. 14 (1999) 705. [9] V.K. Bhat, M. Pattabiraman, K.N. Bhat, A. Subrahamanyam, Mater. Res. Bull. 34 (1999) 1797. [10] E.H. Nicollian, J.R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, John Wiley and Sons, New York, 1982. [11] V.K. Bhat, K.N. Bhat, A. Subrahamanyam, Semicond. Sci. Technol. 15 (2000) 883. [12] J. Maserjian, in: C.R. Helms, B.E. Deal (Eds.), The Physics and Chemistry of SiO2 and the Si /SiO2 interface, New York: Plenum Press, 1988, p. 497. [13] B. Ricco, G. Gozzi, M. Lanzoni, IEEE Trans. Electron Devices 45 (1998) 1554. [14] A. Martin, P. O’Sullivan, A. Mathewson, Microelectron. Reliability 38 (1998) 37. [15] E.P Eernisse, Appl. Phys. Lett. 30 (1977) 290.