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Effect of well and substrate parameters on the latchup degradation of CMOS structures during e-beam voltage contrast measurements
Microelectronic Engineering 15 (1991) 113-116 Elsevier
113
Effect of well and substrate parameters on the latchup degradation of CMOS structures during e-beam voltage contrast measurements E M. Roche, S. D. Bocus and P. Girard Laboratoire d'Informatique, de Robotique et de Micro~lectronique de Montpellier (ex LAMM), URA CNRS DO1480, Universit6 de Montpellier II: Sciences et Techniques du Languedoc, P1. E. Bataillon, 34095 Montpellier C&lex 5, France
Abstract This paper relates to the contactless testing of Complementary Metal Oxide Semiconductor (CMOS) structures. It points out experimental data showing a degradation in the latchup immunity during standard e-beam voltage contrast testing. It emphasizes the phenomenon of charge deposition on the oxide and a lost of reliability related to well and substrate parameter values. The experiments have been carried out in a classical Scanning Electron Microscope (SEM) on 2 I.tm, epitaxial, CMOS test vehicles. An electrical model is used to explain the results.
1. I N T R O D U C T I O N The scaling down of integrated devices makes their characterization increasingly difficult. The SEM has become an essential tool to access directly, in a probe manner, the nodes of VLSI and ULSI functioning circuits [ 1,2]. The latchup phenomenon, for its part, is controlled by adjusting technological and layout parameters [3]. This paper analyses the interference of the SEM characterization operations with the circumstances of latchup triggering in passivated CMOS structures. It shows that in the usual capacitive coupling voltage contrast (CCVC) conditions (low primary energy, low dose), the e-beam can indirectly spoil the electrical response of the device [4,5]. We report quantitative observations related to the latchup triggering threshold changes with the well and substrate resistances under the usual impinging electron conditions [6].
2. EXPERIMENTS The test vehicle is a four terminal structure in which the p+ diffusion in the well and the n + diffusion in the substrate are the sources of an actual CMOS device. The remaining two contacts polarize respectively the well and the substrate. The passivation oxide is about 1 ~tm thick. Figure 1 exhibits its cross-section. This basic structure represents the most sensitive part of a CMOS circuit concerning the latchup phenomenon. The main parasitic elements involved are the vertical PNP and lateral NPN bipolar transistors, and the resistances: Rw of the well and Rs of the substrate. 0167-9317/91/$3.50 © 1991 - Elsevier Science Publishers B.V. All fights reserved.
114
F.M. Roche et al. / Effect of well and substrate parameters
A primary energy of 1 keV and an extraction field of 500 V/mm is used. The supply voltage being fixed to 5 V, we trigger latchup by modulating the negative voltage Ven of the n÷ diffusion in the substrate, the latter being the most sensitive terminal. The switching voltage Vs is defined as the minimum absolute value of V ~ which initiates the phenomenon.
e-
d,
e-
J,
e-
J,
e-
e-
J,
~/ee
J,
'Ien
~Rs
Ven
Figure 1. Cross-section of the test structure.
Figure 2. Lumped element model.
For an increase in the value of the incident electron dose Di, defined as the total charge incident per unit area, the experiment shows a decrease of the switching voltage followed by a catastrophic behavior at a critical dose (Figure 3). Figure 4 represents the evolution of measured Vs for different values of the substrate resistance Rs with a well resistance Rw of 1.1 kf~. On Figure 5 we report this evolution for different Rw when Rs is fixed to 100 f~. The values of Rw and Rs are directly proportional to the distance between the well contact and the p+ diffusion and between the substrate contact and the n + diffusion respectively.
v, (v) ..............
ia . . . . . . . .
0.6 0.4 b: during I B T
0.2
0
0.8 Di (10-7 C/cm2)
I
1.6
Figure 3. Degradation of the switching voltage Vs as a function of the incident dose D i.
116
F.M. Roche et al. / Effect of well and substrate parameters
3.2. Effect of the substrate resistance Rs According to equation 1, self triggering occurs when the channel current attains a critical value Ichl given by: Icm =
VT V* l n ~ = an Ieno Rw Rs Isp
(2)
So, an increase of Rs diminishes the value of Iehl. Since the channel current is directly related to the surface deposited charge, and hence to the incident dose Di, a decrease of lcracauses the self triggering to occur at lower incident doses. The experimental results shown in Figure 4 confirms this behavior.
3.3 Effect of the well resistance Rw When self triggering occurs, the base-emitter bias of the PNP transistor can be expressed as a function of the n-channel resistance Rch: Vebp = Rw Ichl = Rw
Vcc Rch + Rw
(3)
For lchl constant, an increase in the well resistance tends to sensitize the structure by causing a higher potential drop across it. However, an increase of the parameter Rw is accompanied by a decrease of Iehl, since the latter is inversely proportional to the sum of the two resistances Rw and Reh involved here. In our test structure, these two effects nearly counterbalance each other as shown by the very little variations in the characteristics shown in figure 5.
4. CONCLUSION We have shown how the e-beam voltage contrast methods currently used (CCVC) to access the potential of scaled CMOS structures can have a direct effect on the reliability of testing. The latchup immunity can be seriously degraded and even in some conditions, reach the occurrence of a self triggering. This phenomenon is related to the creation of parasitic channels in the substrate by a capacitive coupling effect across the superficially charged oxide layer. The observations have been interpreted, modelled and the well and substrate contributions discussed.
5. REFERENCES 1 2 3 4
E. Menzel, E. Kubalek, Scanning Microscopy, Vol. 5, 103-122 (1983). C. Canali, M. Giannini, E. Zanoni, Microelectron. Reliab. Vol. 28, No. 1,119-161 (1988). R.R. Troutman, Latchup in CMOS Technology, Kluwer Academic Publishers (1986) H. Todokoro, S. Fukuhara, T. Komoda, JARECT, Vol. 13, Semiconductor Technologies (1984). 5 P. Girard, F. M. Roche, B. Pistoulet, IFIP 86, Wafer Scale Integration Proceedings, 301-310. 6 F.M. Roche, S. D. Bocus, EOBT 91, Proceedings of the 3rd European Conference on Electron and Optical Testing of Integrated Circuits (to be published). 7 S. G6rlich, K. D. Hermann, W. Reiners, E. Kubalek, Scanning Microscopy, Vol. 2, 447-464 (1986).
113
Effect of well and substrate parameters on the latchup degradation of CMOS structures during e-beam voltage contrast measurements E M. Roche, S. D. Bocus and P. Girard Laboratoire d'Informatique, de Robotique et de Micro~lectronique de Montpellier (ex LAMM), URA CNRS DO1480, Universit6 de Montpellier II: Sciences et Techniques du Languedoc, P1. E. Bataillon, 34095 Montpellier C&lex 5, France
Abstract This paper relates to the contactless testing of Complementary Metal Oxide Semiconductor (CMOS) structures. It points out experimental data showing a degradation in the latchup immunity during standard e-beam voltage contrast testing. It emphasizes the phenomenon of charge deposition on the oxide and a lost of reliability related to well and substrate parameter values. The experiments have been carried out in a classical Scanning Electron Microscope (SEM) on 2 I.tm, epitaxial, CMOS test vehicles. An electrical model is used to explain the results.
1. I N T R O D U C T I O N The scaling down of integrated devices makes their characterization increasingly difficult. The SEM has become an essential tool to access directly, in a probe manner, the nodes of VLSI and ULSI functioning circuits [ 1,2]. The latchup phenomenon, for its part, is controlled by adjusting technological and layout parameters [3]. This paper analyses the interference of the SEM characterization operations with the circumstances of latchup triggering in passivated CMOS structures. It shows that in the usual capacitive coupling voltage contrast (CCVC) conditions (low primary energy, low dose), the e-beam can indirectly spoil the electrical response of the device [4,5]. We report quantitative observations related to the latchup triggering threshold changes with the well and substrate resistances under the usual impinging electron conditions [6].
2. EXPERIMENTS The test vehicle is a four terminal structure in which the p+ diffusion in the well and the n + diffusion in the substrate are the sources of an actual CMOS device. The remaining two contacts polarize respectively the well and the substrate. The passivation oxide is about 1 ~tm thick. Figure 1 exhibits its cross-section. This basic structure represents the most sensitive part of a CMOS circuit concerning the latchup phenomenon. The main parasitic elements involved are the vertical PNP and lateral NPN bipolar transistors, and the resistances: Rw of the well and Rs of the substrate. 0167-9317/91/$3.50 © 1991 - Elsevier Science Publishers B.V. All fights reserved.
114
F.M. Roche et al. / Effect of well and substrate parameters
A primary energy of 1 keV and an extraction field of 500 V/mm is used. The supply voltage being fixed to 5 V, we trigger latchup by modulating the negative voltage Ven of the n÷ diffusion in the substrate, the latter being the most sensitive terminal. The switching voltage Vs is defined as the minimum absolute value of V ~ which initiates the phenomenon.
e-
d,
e-
J,
e-
J,
e-
e-
J,
~/ee
J,
'Ien
~Rs
Ven
Figure 1. Cross-section of the test structure.
Figure 2. Lumped element model.
For an increase in the value of the incident electron dose Di, defined as the total charge incident per unit area, the experiment shows a decrease of the switching voltage followed by a catastrophic behavior at a critical dose (Figure 3). Figure 4 represents the evolution of measured Vs for different values of the substrate resistance Rs with a well resistance Rw of 1.1 kf~. On Figure 5 we report this evolution for different Rw when Rs is fixed to 100 f~. The values of Rw and Rs are directly proportional to the distance between the well contact and the p+ diffusion and between the substrate contact and the n + diffusion respectively.
v, (v) ..............
ia . . . . . . . .
0.6 0.4 b: during I B T
0.2
0
0.8 Di (10-7 C/cm2)
I
1.6
Figure 3. Degradation of the switching voltage Vs as a function of the incident dose D i.
116
F.M. Roche et al. / Effect of well and substrate parameters
3.2. Effect of the substrate resistance Rs According to equation 1, self triggering occurs when the channel current attains a critical value Ichl given by: Icm =
VT V* l n ~ = an Ieno Rw Rs Isp
(2)
So, an increase of Rs diminishes the value of Iehl. Since the channel current is directly related to the surface deposited charge, and hence to the incident dose Di, a decrease of lcracauses the self triggering to occur at lower incident doses. The experimental results shown in Figure 4 confirms this behavior.
3.3 Effect of the well resistance Rw When self triggering occurs, the base-emitter bias of the PNP transistor can be expressed as a function of the n-channel resistance Rch: Vebp = Rw Ichl = Rw
Vcc Rch + Rw
(3)
For lchl constant, an increase in the well resistance tends to sensitize the structure by causing a higher potential drop across it. However, an increase of the parameter Rw is accompanied by a decrease of Iehl, since the latter is inversely proportional to the sum of the two resistances Rw and Reh involved here. In our test structure, these two effects nearly counterbalance each other as shown by the very little variations in the characteristics shown in figure 5.
4. CONCLUSION We have shown how the e-beam voltage contrast methods currently used (CCVC) to access the potential of scaled CMOS structures can have a direct effect on the reliability of testing. The latchup immunity can be seriously degraded and even in some conditions, reach the occurrence of a self triggering. This phenomenon is related to the creation of parasitic channels in the substrate by a capacitive coupling effect across the superficially charged oxide layer. The observations have been interpreted, modelled and the well and substrate contributions discussed.
5. REFERENCES 1 2 3 4
E. Menzel, E. Kubalek, Scanning Microscopy, Vol. 5, 103-122 (1983). C. Canali, M. Giannini, E. Zanoni, Microelectron. Reliab. Vol. 28, No. 1,119-161 (1988). R.R. Troutman, Latchup in CMOS Technology, Kluwer Academic Publishers (1986) H. Todokoro, S. Fukuhara, T. Komoda, JARECT, Vol. 13, Semiconductor Technologies (1984). 5 P. Girard, F. M. Roche, B. Pistoulet, IFIP 86, Wafer Scale Integration Proceedings, 301-310. 6 F.M. Roche, S. D. Bocus, EOBT 91, Proceedings of the 3rd European Conference on Electron and Optical Testing of Integrated Circuits (to be published). 7 S. G6rlich, K. D. Hermann, W. Reiners, E. Kubalek, Scanning Microscopy, Vol. 2, 447-464 (1986).