- Email: [email protected]
Effects of annealing on CeO2-based flash memories
Vacuum xxx (2015) 1e5
Contents lists available at ScienceDirect
Vacuum journal homepage: www.elsevier.com/locate/vacuum
Effects of annealing on CeO2-based flash memories Chyuan Haur Kao a, Hsiang Chen b, *, Su Zhien Chen a, Sheng-Hao Hung b, Chian You Chen b, Yun-Yang He b, Shang-Ren Lin b, Kun-Min Hsieh b, Min-Han Lin b a b
Chang Gung University, No. 259, Wenhua 1st Rd., Guishan Dist., Taoyuan City 33302, Taiwan, ROC National Chi Nan University, No. 1, University Rd, Puli, Nantou County 54561, Taiwan, ROC
a r t i c l e i n f o
a b s t r a c t
Article history: Received 14 September 2014 Received in revised form 21 January 2015 Accepted 23 January 2015 Available online xxx
In this study, CeO2 was used as a trapping layer in metal oxide high-K-oxide-Si (MOHOS)-type memory devices. This trapping layer underwent annealing to enhance memory performance. Multiple material analyses indicate that annealing enables enhanced crystallization and suppresses silicate formation. MOHOS-type flash memory devices incorporating a CeO2 charge trapping layer annealed at 950 C exhibited a large memory window of 4.7 V, as well as a fast program and erase speed. Our research indicates that MOHOS-type memory devices utilizing CeO2 show great promise for future industrial flash memory applications. © 2015 Elsevier Ltd. All rights reserved.
Keywords: CeO2 Flash memory Annealing Memory window Crystallization
1. Introduction Over the past few years, rare-earth-based materials have emerged to replace silicon oxide in electronic devices [1]. Since rare-earth high-K oxides such as Er2O3 [2] and Sm2O3 [3] exhibit advantages such as providing a thinner interfacial layer, higher capacitance value, high effective electric field across the tunneling oxide and lower leakage current [4], rare-earth-based electronic devices provide improved reliability and performance. Among the various rare-earth oxides, CeO2, with a high dielectric constant of 26, has emerged as one of the most promising rare-earth oxides for use in semiconductor fabrication. Recently, CeO2-based nonvolatile field-effect transistors [5], sensors [6], and dielectrics [7] have been examined for their practical application in electronic devices. However, high-K CeO2 materials used as a charge trapping layer in metal oxide high-K-oxide-Si (MOHOS)-type devices [8] have not been extensively reported. With an appropriate material incorporated as a trapping layer, MOHOS-type memory devices can exhibit a large memory window and a faster program and erase speed [9].
It is therefore crucial to find new materials and fabrication processes to further enhance memory performance. CeO2 has a wide band gap of 3.19 eV, great mechanical strength, good redox properties [10], and has been used for gas and humidity sensors [11,12]. In this study, we used CeO2 as a trapping layer to fabricate MOHOStype memory devices [13e15]. Additionally, post-annealing treatment was introduced to the fabrication process to optimize device performance. The influence of post-annealing on the material properties of the trapping layer was evaluated using multiple material characterizations including X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), and atomic force microscopy (AFM). Results indicate that annealing at a high temperature of 900 C results in enhanced crystallization and suppression of silicate formation. Consistent with the material analyses, MOHOS-type memory incorporating a CeO2 trapping layer annealed at 950 C exhibited both the fastest program and erase speed and largest memory windows. Our results indicate that CeO2-based flash memory shows promise for future industrial memory applications. 2. Experimental
* Corresponding author. Tel.: þ886 49 2910960; fax: þ886 49 2912238. E-mail address: [email protected] (H. Chen).
A MOHOS memory structure incorporating a CeO2 charge was fabricated on single-crystal 4-inch n-type silicon (100) wafers. The
http://dx.doi.org/10.1016/j.vacuum.2015.01.024 0042-207X/© 2015 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Kao CH, et al., Effects of annealing on CeO2-based flash memories, Vacuum (2015), http://dx.doi.org/10.1016/ j.vacuum.2015.01.024
2
C.H. Kao et al. / Vacuum xxx (2015) 1e5
(CeV) hysteresis was measured by an HP-4284 impedance analyzer, and the P/E speed was measured by an HP8110 pulse generator. 3. Results and discussion
Fig. 1. The growth process and device structure of the CeO2-based MOHOS-type memory device.
wafers were cleaned using a standard RCA process. First, a thin 3 nm SiO2 layer was thermally grown using a dry oxidation furnace system at 850 C. Then, a 12 nm CeO2 trapping layer was deposited by radio frequency (RF) sputtering with a Cerium oxide target (purity, 99.99%) in diluted O2 Ar/O2 ¼ 20/5. The RF power was 150 W and the substrate temperature was around 300 C. Next, the wafers were annealed at different temperatures by rapid thermal annealing (RTA) in O2 ambient for 30 s at 700 Ce950 C. Then a 20 nm SiO2 layer was deposited as a blocking oxide layer via RF sputtering with RF power of 150 W, followed by postedeposit annealing (PDA) at 300 C. Next, a 300 nm Al film was deposited by a thermal evaporator, and the gate pattern was defined using lithography and wet etching. Finally, a 300 nm-thick Al layer was deposited on the backside. Layer by layer, the device structure from top to bottom was Al gate/blocking oxide SiO2 (20 nm)/CeO2 trapping layer (12 nm)/tunneling oxide (3 nm)/Si substrate/Al. The growth process and device structure is shown in Fig. 1. Before we deposited the blocking oxide layer, the high-K trapping layer was characterized using XRD, XPS, and AFM. The XRD was performed using XRD Bede D1. The X-ray source was Cu Ka (l ¼ 1.542 Å); the configuration was BraggeBrentano theta-2 theta. The system used a grazing incidence angle (q ¼ 0.5 ) in the diffraction and the diffraction angle 2q range were from 20 to 60 . The XPS spectra were measured by a VG ESCA spectrometer. Capacitance voltage
To study the crystalline structures of the trapping layer annealed under various conditions, XRD measurements were conducted on the films, as shown in Fig. 2. The results show that weak diffraction peaks can be observed for the as-deposited sample. As the annealing temperature increased, the diffraction peaks CeO2 (200), (220), and (311) became stronger, indicating that annealing at a high temperature resulted in crystallization of the film. The strongest crystallization phases appeared for the sample annealed at a high temperature of 950 C. Annealing likely suppresses defects and removes dangling bonds, allowing the film to crystallize. Consistent with the XRD analysis, XPS measurements reveal a similar trend. Fig. 3(a) and (b) shows O 1s and Ce core level XPS spectra for the annealed films. For the as-deposited film, the silicate intensity is very strong but the CeO2 intensity is very weak. As the annealing temperatures increased, the silicate intensity decreased, but the CeO2 intensity increased [16,17]. The strongest CeO2 intensity and the weakest silicate intensity occurred for the film annealed at a high temperature of 950 C. Similarly, Ce 3d XPS spectra as shown in Fig. 3(b) also show the higher the annealing temperature was, the stronger the CeeO bond would be. Since annealing at a high temperature of 950 C provided a sufficient thermal budget, the CeO2 film could reach full reaction and silicate formation could be suppressed [16,17]. Additionally, AFM was used to examine the surface roughness of the CeO2 trapping layer of the annealed samples. The surface morphology of the as-deposited film as well as films annealed at 700 C, 800 C, 900 C, and 950 C are shown in Fig. 4(a)e(e). The AFM analysis reveals that the surface roughness increased as the annealing temperature increased. The growth of the CeO2 nanocrystal might be related to the surface roughness. Crystallization or grain growth might cause the increase of surface roughness, which is in line with the XRD measurements. To investigate the influence of the improvements of the material properties on practical CeO2 flash memory devices, electrical measurements including capacitance voltage (CeV)
Fig. 2. XRD spectra for the as-deposited and annealed CeO2 films.
Please cite this article in press as: Kao CH, et al., Effects of annealing on CeO2-based flash memories, Vacuum (2015), http://dx.doi.org/10.1016/ j.vacuum.2015.01.024
C.H. Kao et al. / Vacuum xxx (2015) 1e5
Fig. 3. XPS spectra of (a) O 1s and (b) Ce 3d energy levels for the as-deposited and annealed CeO2 films.
Please cite this article in press as: Kao CH, et al., Effects of annealing on CeO2-based flash memories, Vacuum (2015), http://dx.doi.org/10.1016/ j.vacuum.2015.01.024
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C.H. Kao et al. / Vacuum xxx (2015) 1e5
Fig. 4. AFM images of (a) the as-deposited CeO2 film and the film annealed at (b) 700 C, (c) 800 C, (d) 900 C, and (e) 950 C.
Fig. 5. The forward and reverse sweep CeV curves of CeO2-based MOHOS-type flash memory device.
characteristics and flat band voltage (VFB) shift over time were conducted. Fig. 5 shows the forward and reverse sweep CeV curves of MOHOS-type flash memory incorporating the annealed CeO2. Based on the CeV curves, the trapping behavior is dominated by electron trapping, which may cause the asymmetric gate voltage changes in positive and negative directions [18]. The program and erase cycles are related to the effects of electron charging and discharging [14] and the sweep goes from the inversion region to the accumulation region. Results indicate that the memory window increased as the annealing temperature increased. Flash memory with a CeO2 trapping layer could achieve the largest memory window of 4.7 V among all the CeO2-based memory devices with trapping layers treated at various annealing temperatures. Therefore, annealing could enhance the memory window by causing crystallization. Since annealing can cause the trapping layer to form a well-crystallized structure, the improvements of the material quality could provide the trapping layer with a higher trapping density. Therefore, the memory window could increase. Finally, Fig. 6(a) and (b) illustrate DVFB values as a function of the program and erase time for the CeO2 MOHOS-type memory device with trapping layers annealed at various temperatures. The P/E speeds were measured by a HP8110 pulse generator. A Source
Please cite this article in press as: Kao CH, et al., Effects of annealing on CeO2-based flash memories, Vacuum (2015), http://dx.doi.org/10.1016/ j.vacuum.2015.01.024
C.H. Kao et al. / Vacuum xxx (2015) 1e5
5
Fig. 6. VFB shifts as a function of (a) the program and (b) erase time for the CeO2-based MOHOS-type memory device.
Measurement Unit (SMU) supplied a DC voltage (a program voltage of 13 V and an erase voltage of 16 V) to the device under test (DUT) and simultaneously measured the resultant flat-band voltage shift. The pulse generator controlled the duration of the pulse (pulse width) from 1000 ns to 1s. Similar to the previous material and electrical measurements, the CeO2 MOHOS-type memory device with a trapping layer annealed at 950 C exhibited the largest VFB shift. The improvements of material properties caused by annealing at a high temperature likely results in a more effective electric field passing through the CeO2 layer. Therefore, the program and erase speed can be increased. 4. Conclusion In this study, MOHOS-type memories were fabricated with a sputtered CeO2 charge trapping layer. The MOHOS-type flash memory device incorporating a CeO2 charge trapping layer annealed at 950 C exhibited a large memory window of 4.7 V and a fast program and erase speed. Multiple material analyses including XRD, XPS, and AFM indicated that annealing could enhance crystallization and suppress the silicate formation. CeO2-based MOHOS-type memory devices show great promise for future industrial flash memory applications.
References [1] Zhao C, Witters T, Brijs B, Bender H, Richard O, Caymax M. Appl Phys Lett 2005;86:132903. [2] Kao CH, Chen H, Pan YT, Chiu JS, Lu TC. Solid State Commun 2012;152:504. [3] Kao CH, Chen H, Lin SP. Electrochem Solid State Lett 2011;G9:142. [4] Chen H. Appl Surf Sci 2011;257:7481. [5] Kim L, Kim J, Jung D, Roh Y. Appl Phys Lett 2000;76:1881. [6] Kao CH, Chen H, Lee ML, Liu CC, Ueng HY, Chu YC, et al. Sensors Actuators B 2014;194:503. [7] Lim DG, Kang GS, Yi JH, Yang KJ, Lee JH. J Korean Phys Soc 2007;51:1085. [8] Hsu TH, You HC, Ko FH, Lei TF. J Electrochem Soc 2006;153:934. [9] Kao CH, Chen H, Chang HW, Chuang CS. J Vac Sci Technol A 2011;29(6). 06B102. [10] Arul NS, Mangalaraj D, Kim TW. Appl Phys Lett 2013;102. 223115e1. [11] Izu N, Itoh T, Shin W, Matsubara I, Murayama N. Electrochem Solid State Lett 2007;10:37. [12] Fu XQ, Wang C, Yu HC, Wang YG, Wang TH. Nanotechnology 2007;18. 145503e1. [13] Younis A, Chu D, Li CM, Das T, Sehar S, Manefield M, et al. Langmuir 2014;30: 1183. [14] Younis A, Chu D, Mihail I, Li S. ACS Appl Mater Interfaces 2013;5:9429. [15] Younis A, Chu D, Lin X, Yi J, Dang F, Li S. ACS Appl Mater Interfaces 2013;5: 2249. €cker J, Bertram F, Wollschla €ger J, Schmidt T, et al. Appl [16] Flege JI, Kaemena B, Ho Phys Lett 2014;104:131604. [17] Kakushima K, Okamoto K, Koyanagi T, Kouda M, Tachi K, Kawanago T, et al. Microelectron Reliab 2010;50:356. [18] Kim DH, Lim D. J Korean Phys Soc 2010;57:1444.
Please cite this article in press as: Kao CH, et al., Effects of annealing on CeO2-based flash memories, Vacuum (2015), http://dx.doi.org/10.1016/ j.vacuum.2015.01.024
Contents lists available at ScienceDirect
Vacuum journal homepage: www.elsevier.com/locate/vacuum
Effects of annealing on CeO2-based flash memories Chyuan Haur Kao a, Hsiang Chen b, *, Su Zhien Chen a, Sheng-Hao Hung b, Chian You Chen b, Yun-Yang He b, Shang-Ren Lin b, Kun-Min Hsieh b, Min-Han Lin b a b
Chang Gung University, No. 259, Wenhua 1st Rd., Guishan Dist., Taoyuan City 33302, Taiwan, ROC National Chi Nan University, No. 1, University Rd, Puli, Nantou County 54561, Taiwan, ROC
a r t i c l e i n f o
a b s t r a c t
Article history: Received 14 September 2014 Received in revised form 21 January 2015 Accepted 23 January 2015 Available online xxx
In this study, CeO2 was used as a trapping layer in metal oxide high-K-oxide-Si (MOHOS)-type memory devices. This trapping layer underwent annealing to enhance memory performance. Multiple material analyses indicate that annealing enables enhanced crystallization and suppresses silicate formation. MOHOS-type flash memory devices incorporating a CeO2 charge trapping layer annealed at 950 C exhibited a large memory window of 4.7 V, as well as a fast program and erase speed. Our research indicates that MOHOS-type memory devices utilizing CeO2 show great promise for future industrial flash memory applications. © 2015 Elsevier Ltd. All rights reserved.
Keywords: CeO2 Flash memory Annealing Memory window Crystallization
1. Introduction Over the past few years, rare-earth-based materials have emerged to replace silicon oxide in electronic devices [1]. Since rare-earth high-K oxides such as Er2O3 [2] and Sm2O3 [3] exhibit advantages such as providing a thinner interfacial layer, higher capacitance value, high effective electric field across the tunneling oxide and lower leakage current [4], rare-earth-based electronic devices provide improved reliability and performance. Among the various rare-earth oxides, CeO2, with a high dielectric constant of 26, has emerged as one of the most promising rare-earth oxides for use in semiconductor fabrication. Recently, CeO2-based nonvolatile field-effect transistors [5], sensors [6], and dielectrics [7] have been examined for their practical application in electronic devices. However, high-K CeO2 materials used as a charge trapping layer in metal oxide high-K-oxide-Si (MOHOS)-type devices [8] have not been extensively reported. With an appropriate material incorporated as a trapping layer, MOHOS-type memory devices can exhibit a large memory window and a faster program and erase speed [9].
It is therefore crucial to find new materials and fabrication processes to further enhance memory performance. CeO2 has a wide band gap of 3.19 eV, great mechanical strength, good redox properties [10], and has been used for gas and humidity sensors [11,12]. In this study, we used CeO2 as a trapping layer to fabricate MOHOStype memory devices [13e15]. Additionally, post-annealing treatment was introduced to the fabrication process to optimize device performance. The influence of post-annealing on the material properties of the trapping layer was evaluated using multiple material characterizations including X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), and atomic force microscopy (AFM). Results indicate that annealing at a high temperature of 900 C results in enhanced crystallization and suppression of silicate formation. Consistent with the material analyses, MOHOS-type memory incorporating a CeO2 trapping layer annealed at 950 C exhibited both the fastest program and erase speed and largest memory windows. Our results indicate that CeO2-based flash memory shows promise for future industrial memory applications. 2. Experimental
* Corresponding author. Tel.: þ886 49 2910960; fax: þ886 49 2912238. E-mail address: [email protected] (H. Chen).
A MOHOS memory structure incorporating a CeO2 charge was fabricated on single-crystal 4-inch n-type silicon (100) wafers. The
http://dx.doi.org/10.1016/j.vacuum.2015.01.024 0042-207X/© 2015 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Kao CH, et al., Effects of annealing on CeO2-based flash memories, Vacuum (2015), http://dx.doi.org/10.1016/ j.vacuum.2015.01.024
2
C.H. Kao et al. / Vacuum xxx (2015) 1e5
(CeV) hysteresis was measured by an HP-4284 impedance analyzer, and the P/E speed was measured by an HP8110 pulse generator. 3. Results and discussion
Fig. 1. The growth process and device structure of the CeO2-based MOHOS-type memory device.
wafers were cleaned using a standard RCA process. First, a thin 3 nm SiO2 layer was thermally grown using a dry oxidation furnace system at 850 C. Then, a 12 nm CeO2 trapping layer was deposited by radio frequency (RF) sputtering with a Cerium oxide target (purity, 99.99%) in diluted O2 Ar/O2 ¼ 20/5. The RF power was 150 W and the substrate temperature was around 300 C. Next, the wafers were annealed at different temperatures by rapid thermal annealing (RTA) in O2 ambient for 30 s at 700 Ce950 C. Then a 20 nm SiO2 layer was deposited as a blocking oxide layer via RF sputtering with RF power of 150 W, followed by postedeposit annealing (PDA) at 300 C. Next, a 300 nm Al film was deposited by a thermal evaporator, and the gate pattern was defined using lithography and wet etching. Finally, a 300 nm-thick Al layer was deposited on the backside. Layer by layer, the device structure from top to bottom was Al gate/blocking oxide SiO2 (20 nm)/CeO2 trapping layer (12 nm)/tunneling oxide (3 nm)/Si substrate/Al. The growth process and device structure is shown in Fig. 1. Before we deposited the blocking oxide layer, the high-K trapping layer was characterized using XRD, XPS, and AFM. The XRD was performed using XRD Bede D1. The X-ray source was Cu Ka (l ¼ 1.542 Å); the configuration was BraggeBrentano theta-2 theta. The system used a grazing incidence angle (q ¼ 0.5 ) in the diffraction and the diffraction angle 2q range were from 20 to 60 . The XPS spectra were measured by a VG ESCA spectrometer. Capacitance voltage
To study the crystalline structures of the trapping layer annealed under various conditions, XRD measurements were conducted on the films, as shown in Fig. 2. The results show that weak diffraction peaks can be observed for the as-deposited sample. As the annealing temperature increased, the diffraction peaks CeO2 (200), (220), and (311) became stronger, indicating that annealing at a high temperature resulted in crystallization of the film. The strongest crystallization phases appeared for the sample annealed at a high temperature of 950 C. Annealing likely suppresses defects and removes dangling bonds, allowing the film to crystallize. Consistent with the XRD analysis, XPS measurements reveal a similar trend. Fig. 3(a) and (b) shows O 1s and Ce core level XPS spectra for the annealed films. For the as-deposited film, the silicate intensity is very strong but the CeO2 intensity is very weak. As the annealing temperatures increased, the silicate intensity decreased, but the CeO2 intensity increased [16,17]. The strongest CeO2 intensity and the weakest silicate intensity occurred for the film annealed at a high temperature of 950 C. Similarly, Ce 3d XPS spectra as shown in Fig. 3(b) also show the higher the annealing temperature was, the stronger the CeeO bond would be. Since annealing at a high temperature of 950 C provided a sufficient thermal budget, the CeO2 film could reach full reaction and silicate formation could be suppressed [16,17]. Additionally, AFM was used to examine the surface roughness of the CeO2 trapping layer of the annealed samples. The surface morphology of the as-deposited film as well as films annealed at 700 C, 800 C, 900 C, and 950 C are shown in Fig. 4(a)e(e). The AFM analysis reveals that the surface roughness increased as the annealing temperature increased. The growth of the CeO2 nanocrystal might be related to the surface roughness. Crystallization or grain growth might cause the increase of surface roughness, which is in line with the XRD measurements. To investigate the influence of the improvements of the material properties on practical CeO2 flash memory devices, electrical measurements including capacitance voltage (CeV)
Fig. 2. XRD spectra for the as-deposited and annealed CeO2 films.
Please cite this article in press as: Kao CH, et al., Effects of annealing on CeO2-based flash memories, Vacuum (2015), http://dx.doi.org/10.1016/ j.vacuum.2015.01.024
C.H. Kao et al. / Vacuum xxx (2015) 1e5
Fig. 3. XPS spectra of (a) O 1s and (b) Ce 3d energy levels for the as-deposited and annealed CeO2 films.
Please cite this article in press as: Kao CH, et al., Effects of annealing on CeO2-based flash memories, Vacuum (2015), http://dx.doi.org/10.1016/ j.vacuum.2015.01.024
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Fig. 4. AFM images of (a) the as-deposited CeO2 film and the film annealed at (b) 700 C, (c) 800 C, (d) 900 C, and (e) 950 C.
Fig. 5. The forward and reverse sweep CeV curves of CeO2-based MOHOS-type flash memory device.
characteristics and flat band voltage (VFB) shift over time were conducted. Fig. 5 shows the forward and reverse sweep CeV curves of MOHOS-type flash memory incorporating the annealed CeO2. Based on the CeV curves, the trapping behavior is dominated by electron trapping, which may cause the asymmetric gate voltage changes in positive and negative directions [18]. The program and erase cycles are related to the effects of electron charging and discharging [14] and the sweep goes from the inversion region to the accumulation region. Results indicate that the memory window increased as the annealing temperature increased. Flash memory with a CeO2 trapping layer could achieve the largest memory window of 4.7 V among all the CeO2-based memory devices with trapping layers treated at various annealing temperatures. Therefore, annealing could enhance the memory window by causing crystallization. Since annealing can cause the trapping layer to form a well-crystallized structure, the improvements of the material quality could provide the trapping layer with a higher trapping density. Therefore, the memory window could increase. Finally, Fig. 6(a) and (b) illustrate DVFB values as a function of the program and erase time for the CeO2 MOHOS-type memory device with trapping layers annealed at various temperatures. The P/E speeds were measured by a HP8110 pulse generator. A Source
Please cite this article in press as: Kao CH, et al., Effects of annealing on CeO2-based flash memories, Vacuum (2015), http://dx.doi.org/10.1016/ j.vacuum.2015.01.024
C.H. Kao et al. / Vacuum xxx (2015) 1e5
5
Fig. 6. VFB shifts as a function of (a) the program and (b) erase time for the CeO2-based MOHOS-type memory device.
Measurement Unit (SMU) supplied a DC voltage (a program voltage of 13 V and an erase voltage of 16 V) to the device under test (DUT) and simultaneously measured the resultant flat-band voltage shift. The pulse generator controlled the duration of the pulse (pulse width) from 1000 ns to 1s. Similar to the previous material and electrical measurements, the CeO2 MOHOS-type memory device with a trapping layer annealed at 950 C exhibited the largest VFB shift. The improvements of material properties caused by annealing at a high temperature likely results in a more effective electric field passing through the CeO2 layer. Therefore, the program and erase speed can be increased. 4. Conclusion In this study, MOHOS-type memories were fabricated with a sputtered CeO2 charge trapping layer. The MOHOS-type flash memory device incorporating a CeO2 charge trapping layer annealed at 950 C exhibited a large memory window of 4.7 V and a fast program and erase speed. Multiple material analyses including XRD, XPS, and AFM indicated that annealing could enhance crystallization and suppress the silicate formation. CeO2-based MOHOS-type memory devices show great promise for future industrial flash memory applications.
References [1] Zhao C, Witters T, Brijs B, Bender H, Richard O, Caymax M. Appl Phys Lett 2005;86:132903. [2] Kao CH, Chen H, Pan YT, Chiu JS, Lu TC. Solid State Commun 2012;152:504. [3] Kao CH, Chen H, Lin SP. Electrochem Solid State Lett 2011;G9:142. [4] Chen H. Appl Surf Sci 2011;257:7481. [5] Kim L, Kim J, Jung D, Roh Y. Appl Phys Lett 2000;76:1881. [6] Kao CH, Chen H, Lee ML, Liu CC, Ueng HY, Chu YC, et al. Sensors Actuators B 2014;194:503. [7] Lim DG, Kang GS, Yi JH, Yang KJ, Lee JH. J Korean Phys Soc 2007;51:1085. [8] Hsu TH, You HC, Ko FH, Lei TF. J Electrochem Soc 2006;153:934. [9] Kao CH, Chen H, Chang HW, Chuang CS. J Vac Sci Technol A 2011;29(6). 06B102. [10] Arul NS, Mangalaraj D, Kim TW. Appl Phys Lett 2013;102. 223115e1. [11] Izu N, Itoh T, Shin W, Matsubara I, Murayama N. Electrochem Solid State Lett 2007;10:37. [12] Fu XQ, Wang C, Yu HC, Wang YG, Wang TH. Nanotechnology 2007;18. 145503e1. [13] Younis A, Chu D, Li CM, Das T, Sehar S, Manefield M, et al. Langmuir 2014;30: 1183. [14] Younis A, Chu D, Mihail I, Li S. ACS Appl Mater Interfaces 2013;5:9429. [15] Younis A, Chu D, Lin X, Yi J, Dang F, Li S. ACS Appl Mater Interfaces 2013;5: 2249. €cker J, Bertram F, Wollschla €ger J, Schmidt T, et al. Appl [16] Flege JI, Kaemena B, Ho Phys Lett 2014;104:131604. [17] Kakushima K, Okamoto K, Koyanagi T, Kouda M, Tachi K, Kawanago T, et al. Microelectron Reliab 2010;50:356. [18] Kim DH, Lim D. J Korean Phys Soc 2010;57:1444.
Please cite this article in press as: Kao CH, et al., Effects of annealing on CeO2-based flash memories, Vacuum (2015), http://dx.doi.org/10.1016/ j.vacuum.2015.01.024