Effects of various gate materials on electrical degradation of a-Si:H TFT in industrial display application

Solid-State Electronics xxx (2015) xxx–xxx

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Effects of various gate materials on electrical degradation of a-Si:H TFT in industrial display application Ching-Yuan Ho ⇑, Yaw-Jen Chang Department of Mechanical Engineering, Chung Yuan Christian University, Chung-Li, Taiwan

a r t i c l e

i n f o

Article history: Received 31 August 2015 Received in revised form 10 October 2015 Accepted 19 October 2015 Available online xxxx Keywords: a-Si:H TFT Electron-migration Threshold voltage stability Power-law time dependency Recovery performance

a b s t r a c t Both aluminum (Al) and copper (Cu), acting as transmission lines in the hydrogenated amorphous silicon of a thin film transistor (a-Si:H TFT), were studied to investigate electrical degradation including electronmigration (EM) and threshold voltage (Vt) stability and recovery performance. Under long-term current stress, the Cu material exhibited excellent resistance to EM properties, but a passivated SiNx crack was observed due to fast heat conductivity. By applying electrical stress on the gate and drain for 5
104 s, the power-law time dependency of the threshold voltage shift (DVt) indicated that the defective state creation dominated the TFT device’s instability. The presence of drain stress increased the overall DVt because the high longitudinal field induced impact ionization and then, enhanced hot-carrier-induced electron trapping within the gate SiNx dielectric. An annealing effect prompted a stressed a-Si:H TFT back to virgin status. This study proposes better DVt stability and excellent resistance against electronmigration in a Cu gate device which can be considered as a candidate for a transmission line on prolonged TFT applications. Crown Copyright Ó 2015 Published by Elsevier Ltd. All rights reserved.

1. Introduction Hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) have been intensively studied as a switching device for liquid crystal displays (LCD) during the past decade. Due to fascinating factors, such as low cost, low depositing temperature and acceptable electrical characteristics, a-Si:H TFTs are still continuously used not only on LCD glass substrate but extending their application to novel active matrix organic light-emitting diodes (AMOLED) on flexible polymer substrate and TFT driver. Although the low temperature of fabricated a-Si:H TFT has rich charge trapping sites and a defect in its interface trap as well as low electron mobility, it still possesses important advantages including largearea panel fabrication, a high breakdown field and application to standard industrial processes [1,2]. Therefore, until now, a-Si:H TFTs have been attracting much interest in realizing fundamental physics and continuously improving their electrical properties on novel devices, such as SOI TFT and gate-all-around poly-Si TFT [3,4]. In a standard TFT process, aluminum-based (Al-based) alloy is the most commonly used for gate electrodes due to its acceptable ⇑ Corresponding author at: 200, Chung Pei Rd., Chung-Li 32023, Taiwan. Tel.: +886 3 2654321; fax: +886 3 2654399. E-mail address: [email protected] (C.-Y. Ho).

resistivity, low material cost, high adhesion on glass substrate and superior patterning ability in dry etching. However, serious electro-migration (EM) and hillock problems on Al-based alloys could induce potential open and short circuits, respectively. Therefore, copper (Cu), acting as an electrode and transmission line on TFTs, has been considered as a possible substitute for Al-based alloys due to its higher electrical conductivity and potentially greater resistance to EM failure [5,6]. Besides, the timedependency of threshold voltage stability issues has become the most important factor affecting a-Si:H TFT performance for display panel instruments. For specific circuit designs, there are many a-Si: H TFTs that operate in both normal and reverse modes which are very susceptible to the effect of prolonged voltage stressing. Although there have been recent reports on threshold voltage shifts (DVt) of a-Si:H TFTs on glass and flexible polymer substrates, most papers have mentioned that the DVt could be eliminated by increasing drain voltage but illustrations of deteriorated a-Si:H TFT characteristics by thermal stress and hot-carrier-induced threshold voltage shifts during prolonged bias stress have never been reported [7–10]. In this paper, the degradation of shorter channel lengths on a-Si:H TFTs associated with various metal gate materials (Al and Cu) are extensively investigated. For the threshold voltage shift, the phenomenon of a hot-carrier generated from a high longitudinal electrical field (drain voltage), which induces more DVt, will be discussed by interchanging the source and drain

http://dx.doi.org/10.1016/j.sse.2015.10.006 0038-1101/Crown Copyright Ó 2015 Published by Elsevier Ltd. All rights reserved.

Please cite this article in press as: Ho C-Y, Chang Y-J. Effects of various gate materials on electrical degradation of a-Si:H TFT in industrial display application. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.10.006

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polarity. The thermal stress distribution of a TFT structure is simulated to explain the rich defect density states on the a-Si:H/SiNx interface. For EM deterioration in both Al and Cu transmission lines, activated energy is obtained by means of long-term constant current measurement with baking at various temperatures. 2. Experimental details Bottom-gate (BG) inverted staggered TFT with back-channelpassivated a-Si:H was used to evaluate the performances of various gate metals. The fabricated processes of this structure have been announced elsewhere [11]. Both Al and Cu metals with 150 nm thick and thin capped molybdenum acted as bottom gate electrodes was deposited on glass substrate by sputter system. The gate pattern was performed by lithography and plasma etching processes. A 400 nm thick SiNx film and 170 nm thick a-Si:H films were sequentially deposited over metal gate for gate dielectric film and TFT channel, respectively. The thin n+ a-Si layer was then deposited on a-Si:H surface to form ohmic contact, following by Al/Mo with thickness of 500 nm/20 nm deposition using PVD sputter chamber. The lithography and etching technologies were used to define source/drain electrodes by etching Al/Mo, n+ a-Si layers, stop on a-Si:H channel. Finally, the passivated SiNx layer was deposited to complete a-Si:H TFT configuration. All SiNx dielectric and a-Si:H films were deposited in PECVD multi-chamber cluster tool. Metal films including gate electrode and source/drain of Al line were deposited by Ar+ sputter chamber. The channel width and length in this TFT devices were 36 lm and 6.5 lm, respectively. Fig. 1 depicts the schematic representation of threedimensional industrial standard BG a-Si:H TFT structure which could be seen everywhere. Failure morphologies and element analysis were identified by field emission scanning electron microscope (FESEM, JEOL 7600F) and energy dispersive X-ray spectrometer (EDX). Meanwhile, thermal stress during various anneal conditions were simulated using the finite element analysis (FEA) software. The simulation software (ANSYS User’s manual, 2010) combined with couple-field physics model of TFT device structure was calculated. Current–voltage measurement of a-Si:H TFT was performed using HP4145 semiconductor characterization system and magnetically shielding of probe station with elevating temperature stage. Based on the standard equation of long channel metal–oxide-semiconductor field-effect transistor, the threshold voltage (Vt) and field-effect mobility (lFE) could be extracted from

Fig. 1. Schematic depiction of bottom-gate (BG) inverted staggered structure with back-channel-passivated a-Si:H using 3D representation.

linear and saturation regions of channel conductance [12,13]. The sub-threshold slope was derived from the inverse slope of logarithmic scale Ids versus Vgs. According to the time-to-failure (TTF) model on micro metal lines, the activity energy of Al and Cu extracted from the Black’ equation was introduced to illustrate the properties of Al and Cu signal transmission [14,15]. To evaluate the instability of the a-Si:H TFT, a bias stress of 20 V was applied to gate electrode with drain bias ranging from 0 V to 20 V. The duration of voltage bias measurement were performed up to 5
104 s at room temperature and interrupted at regular intervals to retrieve transfer characteristics and threshold voltage shift. 3. Results and discussion Test structures, with 10 lm-wide and 0.43 lm-high Al/Cu metal lines capped with a Mo layer and SiNx dielectric layer, were electrically measured to evaluate time-to-failure by constant current stress. A criterion of suddenly decreasing the current is used in defining the approximate time-to-failure (TTF) which is given by the Black equation:

TTF ¼ AJn expðQ=kTÞ Q¼

  n  KT 1 T 2 TTF 1 J ln
1 T2  T1 TTF 2 J2

ð1Þ ð2Þ

where A is a constant, J is the current density (1
106 A/cm2), n is a model parameter for the current density and takes 2 and 3 for Cu and Al, respectively. Q is the activation energy, k is the Boltzmann’s constant and T is the Kelvin temperature. Under high current stress at 25 °C and 120 °C, the activation energies extracted from Eqs. (1) and (2) corresponding to the average failure time (not show here) of Cu and Al metal lines were extracted to be 0.34 eV and 0.23 eV, respectively. This elucidates that the inherently low resistivity of a Cu line is adequately used to conquer the EM issue and provide a longer life-time for signal transmission as well as gate electrodes in TFT devices. Fig. 2 shows the cross-sectional images of the failure site on both the Cu and Al lines. As shown in Fig. 2(a), a long-term current flow through the Cu line, and the Joule heating quickly spreads out over the passivated SiNx film, consequently inducing a SiNx crack and then, some atoms diffusing to the covered SiNx’s surface. The chemical compositions diffused from the SiNx seams are identified. Analytical results, shown in Fig. 2(b), demonstrate that the main element of the residue on a SiNx’s surface is a Cu atom, and the inset lists the qualitative analysis of the EDX spectrum. Due to a high coefficient of thermal conductivity on the Cu material, the heating is quickly conducted into the SiNx dielectric film, consequently inducing the SiNx to crack, and facilitating Cu atom diffusion along the SiNx’s seams. The interface between the Cu/SiNx dielectric-cap is the preferred failure site due to a significantly different coefficient of thermal expansion [16,17]. In Fig. 2(c), a void is found in the swelled Al line in which the failure morphology is obviously different from the Cu line. Due to a low amount of activity energy to overcome EM failure, the failure morphology of the Al line can be explained by the fact that Al atoms diffuse along the grain boundary and then, facilitate void formation [18,19]. The study concludes that the Cu material inherently proposes high activity energy to conquer the EM issue, low electrical resistivity and 30% of the coefficient of thermal expansion (CTE) which is less than that of aluminum. Although the Cu line suffers instantaneous crack failure before long-term current stress, several benefits mentioned above make Cu material the best candidate for signal transmission lines on TFT devices. The mechanism of a thermal-induced defect creation, in terms of an increase in the density of states and the reduction of the energy barrier to break bonds in strained a-Si:H, has been qualitatively

Please cite this article in press as: Ho C-Y, Chang Y-J. Effects of various gate materials on electrical degradation of a-Si:H TFT in industrial display application. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.10.006

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2.4x10-7

virgin Al gate after gate stressing

Drain current (A)

2.0x10-7

virgin Cu gate after gate stressing recovery at 180 ഒ 4hr

recovery at 180ഒ 4hr

2.4x10-7 2.0x10-7

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(b)

0.0

0.0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 10

Gate voltage (V)

Gate voltage (V)

Fig. 4. Current–voltage curve of a-Si:H TFT device undergo prolonged voltage bias and annealing recovery.

10

(b) Cu gate TFT

(a) Al gate TFT

VG=20V, VD=0V VG=20V, VD=10V VG=20V, VD=15V VG=20V, VD=20V

VG=20V, VD=0V VG=20V, VD=10V VG=20V, VD=15V VG=20V, VD=20V

ΔVth (V)

1

Fig. 2. After long-term of constant current stress, (a) the cross-sectional images of failure site for Cu, (b) EDX spectra and their corresponding qualitatively elemental analysis (inset) verification of Cu diffusion, and (c) cross-sectional images of failure site for Al.

0.1

10 2

reported by Stutzmann [20]. Actually, a thermal-stress-induced defect is inevitable because a prolonged high current on the transmission line will induce Joule heating. In order to realize the thermal stress distribution within a-Si:H TFT films during the prolonged gate voltage period, the annealing effect was simulated using simulation software to qualitatively illustrate the thermal stress distribution between both Al and Cu gate of structures. The simulation results from the model showing thermal stress distribution by couple-field physics is shown in Fig. 3. Abrupt thermal stress at the metal gates/SiNx/a-Si interfaces is clearly found,

200 Cu 150°C Cu 120°C Cu 75°C Al 150°C Al 120°C Al 75°C

Stress (MPa)

100

0

SiNx

-100

a-Si

SiNx Cu/Al Glass

-200

SiNx

-300 0

2

a-Si 4

SiNx 6

Cu/Al 8

10

12

Glass 14

16

Path (mm) Fig. 3. Thermal stress distribution within a-Si:H TFT stacked films by simulation.

10 3

10 4

10 2

103

104

105

Stress time (s) Fig. 5. Logarithmic plot of the threshold voltage shift of an a-Si:H TFT as a function of the stressing time for (a) Al metal gate and (b) Cu metal gate.

and the apparent increasing stress with increase in temperature may result in a defect density state creation. This means that long term device operation will probably enhance the defect state creation at the interfaces and result in electrical degradation. The Vt deviation of a-Si:H TFT correlated with prolonged voltage duration and recovery performance should be identified because it limits the life-time and reliability in applying TFT display instruments. The Ids–Vgs plots under a fixed 20 V gate bias (Vgs) with lasting 5
104 s duration and annealing recovery for Al and Cu metal gates are shown in Figs. 4(a) and (b), respectively. After prolonged device operation, the obvious DVt illustrated that a-Si:H TFT suffered from electrical damage. Fortunately, the DVt could be recovered from the excited state to the virgin state by an annealing process. For the prolonged stress drain bias experiments, Vt was recorded at positive drain voltages (Vds) of 0 V, +10 V, +15 V and +20 V with a constant gate voltage (Vgs) of 20 V. These devices were stressed up to 5
104 s. A logarithmic plot of DVt as a function of various drain bias conditions and stressing time were measured, as shown in Fig. 5. The linear behavior of DVt exhibits a powerlaw time dependency (PLTD), indicating that DVt is dominated by defect state generation which is mainly caused by breaking Si–Si bonds and thermal stress between the silicon channel and SiNx dielectric film [21–24]. These factors lead to an increased density state in the band gap of an amorphous Si channel and the interface of a-Si:H/SiNx. Furthermore, due to high longitudinal electrical field ðeL Þ stress at a lasting drain voltage bias, the increasing DVt is attrib-

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e-

(a)

Source Drain

increasing Vd

Normal operation

e-

(b) Acting drain

increasing Vd

Acting source Reverse operation Fig. 6. Energy band diagram of stressed device at (a) normal operation and (b) reverse operation.

uted to hot-electron generation of impact ionization which may induce threshold voltage instability. At drain current saturation regions, near the drain side where the eL is sufficiently high, electrons acquire a high kinetic energy to collide and cause an impact

1.6x10-6 Measurement Al gate TFT Stress VG=1V VD=0V VG=3V VG=20V VG=5V Time=50000s dotted -- reverse solid -- normal

-6

Ids (A)

1.2x10-6 1.0x10-6

Measurement Cu gate TFT Stress VG=1V VD=0V VG=3V VG=20V VG=5V Time=50000s

dotted -- reverse solid -- normal

(a)

8.0x10-7

(c) Measurement Al gate TFT Stress VG=1V V =15V D VG=3V V =20V G VG=5V Time=50000s dotted -- reverse solid -- normal

1.4x10-6 1.2x10

Ids (A)

1.6x10-6 1.4x10

ionization. If a transverse electrical field is applied, the multiplicative carriers with sufficiently kinetic energy will create an interface state between a-Si/SiNx, partially accelerating electrons that are fast-moving downward on the SiNx dielectric film as trapped charges. These trapped negative charges shift the conduction band edge upward and form a hump at the region adjacent to the drain side. Consequently, the hump prevents electrons from flowing from the source to the drain terminal, and Vt should be increased. Basically, the electrical characteristics on the virgin a-Si:H TFT should be symmetrical because the source and drain are interchangeable for normal and reverse operations. Here, the opposite polarity of a drain voltage compared to the normal operation is called a reverse operation. Fig. 6(a) shows the energy band diagram of a normal operation with varied Vds after stressing the TFT device. At smaller Vds, the higher hump barrier near the drain side originates from hot electrons being injected and prevents electron current (Ids) flow into the drain side. If the Vds is large enough, that hump can be neglected on Ids. The energy band diagram at reverse operation on stress devices is explained by Fig. 6(b). During reverse operation, in a linear region, the drain current in reverse operation is similar to that of normal operation because a low drain voltage affecting the energy hump height can be neglected. Besides, the hump is near an acting source. The positive voltage on the acting drain has little effect on the height of the hump barrier. This means that the Ids is reduced and the Vt is increased for reverse operation. Therefore, the presence of a hump reduces the Ids, and the threshold voltage is positively increased in comparison with its virgin state. The output characteristics (Ids–Vds curve) of a-Si:H TFT for its virgin state and both normal/reverse operations after different drain stresses were measured are shown in Fig. 7. As we can see from Figs. 7(a)– (d), the output characteristics exhibit asymmetric plots by swapping the polarity of the source and drain. Shown on the left-side of Fig. 7, in the saturation region the drain current of the Al gate

-6

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VD=15V VG=20V Time=50000s

1.6x10-6

1.6x10 -6

(b)

1.2x10 -6 1.0x10 -6 8.0x10 -7

Measurement Cu gate TFT Stress VG=1V V =10V D VG=3V V =20V G VG=5V Time=50000s dotted -- reverse solid -- normal

2

4

6

8

10 12 14

(d)

1.4x10-6 1.2x10

Ids (A)

Measurement Al gate TFT Stress VG=1V V =10V D VG=3V V =20V G VG=5V Time=50000s dotted -- reverese solid -- normal

-6

10 12 140

Vds (Volt)

Vds (Volt)

Ids (A)

Cu gate TFT Stress

0.0

0.0

1.4x10

Measurement VG=1V VG=3V VG=5V reverese

Measurement Al gate TFT Stress VG=1V V =20V D VG=3V V =20V G VG=5V Time=50000s dotted -- reverese solid -- normal

-6

1.0x10-6 8.0x10-7

6.0x10 -7

6.0x10-7

4.0x10 -7

4.0x10-7

2.0x10 -7

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Measurement VG=1V VG=3V VG=5V reverese

Cu gate TFT Stress

VD=20V VG=20V Time=50000s

0.0

0.0 0

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4

6

8

10 12 14

0

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10 12 14 0

2

4

6

8

10 12 14

Vds (Volt)

Fig. 7. Output characteristics measured for its virgin state and normal and reverse operations after prolonged drain stresses (Vds = 0 V, 10 V, 15 V and 20 V).

Please cite this article in press as: Ho C-Y, Chang Y-J. Effects of various gate materials on electrical degradation of a-Si:H TFT in industrial display application. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.10.006

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Stress Cu Stress Al

Cu relaxed at 100 °C Al relaxed at 100 °C Cu relaxed at 180 °C Al relaxed at 180 °C

Cu relaxed at RT Al relaxed at RT

ΔV (V) th

4

4

3

3

2

2

1

1

0

4. Conclusions

5

ΔV (V) th

5

0 0 2 4 6 8 10 12 14 10 20 30 40 50 60 70

Stress time (hr)

1

2

3

5

4

Relaxation time (hr)

Fig. 8. Threshold voltage shift correlates with time for stress (Vgs = 20 V, Vds = 20 V) and relaxation.

device is higher in normal operation than in reverse operation. In contrast, the drain current of a Cu gate device in both normal and reverse operations is similar, as shown on the right-side of Fig. 7. During normal operation, the height of a potential hump in the channel near the drain side (as shown in Fig. 6(a)) is reduced by the increasing Vds. When the source and drain are swapped for reverse operation, since a potential energy hump is near the acting source, the positive voltage on an acting drain has little effect on the height of the hump barrier and causes asymmetry in Ids–Vds characteristics. To conclude the above measurements, we demonstrate that the root cause of increasing a threshold voltage shift after prolonged stress of a-Si:H TFT originates from the hot electron of impact ionization on the drain side and the hump barrier at the conduction band. These rich interface trapping states and injected electrons within a SiNx dielectric increase the threshold voltage instability. Simultaneously, we speculate that the Cu gate device proposes lower defect density states and light impact ionization due to a smaller hump barrier and symmetric Ids–Vds curves between normal and reverse operations. In order to observe the recovery performance of stressed TFT devices, the Vt values of all stressed TFT devices were recovered at each relaxed interval. Fig. 8 is divided into three regions including voltage stress, relaxation with and relaxation without annealing. For the Al gate, the shift and relaxation of threshold voltages are both extremely fast at initial periods which can be attributed to the injected charges within the SiNx dielectric and the creation of defects at the interfaces. After the initial period, the rates of DVt and relaxation are slower with time. These values indicate that charge trapping and de-trapping occur in the SiNx dielectric. Finally, the relaxation of a-Si:H TFT returns to its original status by annealing, and the relaxed speed strongly correlates with temperature [25]. For the Cu gate, the behavior is similar to the Al one except for the voltage stress region. Due to a higher coefficient of thermal conduction, the creation of a defect state at the heterojunction between the SiNx and the gate materials is suspected to be the root cause of a linear DVt increase. Besides, a fast relaxed speed of the Cu gate can be obtained at higher baking conditions by providing higher thermal energy to trap electrons which can escape from the trapping sites.

In conclusion, the electrical degradation in both Al and Cu transmission lines was evaluated. During long-term, high current stress, the Cu line exhibits better EM properties compared to the Al line. Different fail morphologies of transmission lines were found. The fast thermal conductivity of a Cu line is speculated to induce SiNx cracking. In contrast, a swelled Al line with voids is found at failure sites which are explained by diffused Al atoms along the grain boundary. Although a Cu line fails as soon as a SiNx crack happens, a Cu line exhibits better EM properties than the Al line. In threshold voltage stability, DVt with prolonged voltage stressing shows the power-law time dependency (PLTD) and illustrates that DVt is dominated by defect state generation and hot electrons from impact ionization. In prolonged drain stress experiments, asymmetrical Ids curves of Al gate devices were found in normal and reverse operations. We speculate that there were fewer defect density states and injected hot electrons remained in the SiNx dielectric film of an Al gate device. In contrast, the Cu gate of TFT exhibits symmetric Ids curves in both normal and reverse operations which indicate a less defective density state and hotelectrons within the SiNx dielectric film. In this paper, we demonstrate that Cu material used for a-Si:H TFT has a highly resistive EM property, inherently low resistivity and stability Vt capabilities. These benefits elucidate that a Cu transmission line can sustain prolonged operation on a-Si:H TFT until it fails by SiNx cracking and is suitable to be a new candidate to replace Al for prolonged bias time of TFT device application. References [1] Risteska A, Chan KY, Gordijn A, Stiebig H, Knipp D. J Dispersion Technol 2012;8:27. [2] Tsujimura T. Jpn J Appl Phys 2004;43:5122. [3] Orouji AA, Kumar MJ. IEEE Trans Electron Devices 2005;52:1815. [4] Liao TC, Tu SW, Yu MH, Lin WK, Liu CC, Chang KJ, et al. IEEE Electron Device Lett 2008;29:889. [5] Yao HW, Yiang KY, Justison P, Rayasam M, Aubel O, Poppe J. J Appl Phys 2011;110:073504. [6] Gladkikh A, Lereah Y, Glickman E, Karpovski M, Palevski A, Schubert J. Appl Phys Lett 1995;66:1214. [7] Lee CH, Striakhilev D, Nathan A. IEEE Trans Electron Devices 2007;54:45. [8] Lee CH, Striakhilev D, Tao S, Nathan A. IEEE Electron Device Lett 2005;26:637. [9] Chan I, Moradi M, Sazonov A, Nathan A. J Dispersion Technol 2011;7:36. [10] MacDonald WA. J Mater Chem 2004;14:4. [11] Indluru A, Venugopal SM, Allee DR, Alford TL. J Dispersion Technol 2011;7:306. [12] Sze SM. Physics of semiconductor devices. New York: John Wiley & Sons; 1981. [13] Lee UG, Jang J. IEEE Electron Device Lett 2011;32:1233. [14] Heryanto A, Pey KL, Lim YK, Raghavan N, Liu W, Wei J, et al. J Appl Phys 2011;110:083702. [15] Yan MY, Tu KN, Vairagar AV, Mhaisalkar SG, Krishnamoorthy A. Appl Phys Lett 2005;87:1. [16] Hu CK, Gignac L, Liniger E, Rosenberg R. J Electrochem Soc 2002;149:G408. [17] Hau-Riege CS, Thompson CV. Appl Phys Lett 2001;78:3451. [18] Cho J, Thompson CV. Appl Phys Lett 1989;54:2577. [19] Kinsbron E. Appl Phys Lett 1980;36:968. [20] Stutzmann M. Appl Phys Lett 1985;47:21. [21] Powell MJ, van Berkel C, Hughes JR. Appl Phys Lett 1989;54:1323. [22] Rolland A, Richard J, Kleider JP, Mencaraglia D. J Electrochem Soc 1993;140:3679. [23] Kleider P, Longeaud C, Mencaraglia D, Rolland A, Vitrou P, Richard J, et al. Solids 1993;164:403. [24] Yilmaz G, Turan E, Günes M, Smirnov V, Finger F, Brüggemann R. Phys Status Solidi (c) 2010;7:700. [25] Oudwan M, Abramov A, Daineka D, Cabarrocas Roca I P. J Dispersion Technol 2012;8:23.

Please cite this article in press as: Ho C-Y, Chang Y-J. Effects of various gate materials on electrical degradation of a-Si:H TFT in industrial display application. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.10.006