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ZnO Hybrid Nanocomposites TFT for NAND Gate Application
Available online at www.sciencedirect.com
ScienceDirect Materials Today: Proceedings 5 (2018) 10827–10832
www.materialstoday.com/proceedings
ILAFM2016
PANI/ZnO Hybrid Nanocomposites TFT for NAND Gate Application. 1
Omprakash S.S1,Naveen Kumar S.K1* Department of Electronics, Mangalore University, Mangalore 574199, India.
Abstract
Thin Film Transistor (TFT) is the key element for future day’s electronic circuit, in which low cost, low temperature, vacuum free process and flexibility of the substrate are the need for the day. With Cellulose acetate substrate as an insulator layer for the TFT, the C-V characteristic had been performed to find the dielectric constant. Polyaniline (PANI) is doped with Zinc Oxide (ZnO), and these Nanocomposites are coated on the substrate. The structure of TFT is achieved by coating electrodes on PANI/ZnO layer and substrate. Study was done on this hybrid structure for its electrical characteristics such as mobility and resistivity. The surface roughness and morphology of PANI/ZnO were characterized by Atomic Force Microscope (AFM) and Scanning Electronic Microscope (SEM). The input and output characteristics of TFT was obtained using I-V measurement system. One of the basic building blocks of digital circuits is NAND gate. The NAND gate is designed, fabricated and tested for its output voltage. Keywords:
TFT, organic polymers semiconductor, Nanocomposites, NAND gate
1. Introduction A thin-film transistor (TFT) is a special kind of field effect transistor made by depositing thin films of an active semiconductor layer as well as the dielectric layer and metallic contacts over a supporting substrate. TFT’s can be made using a wide variety of semiconductor materials. TFT’s include compound semiconductors such as cadmium selenide, or metal oxides such as zinc oxide. TFT’s have also been made using organic materials, referred to as organic field-effect transistors or OTFT’s, one of the organic materials is polyaniline. Among the different types of conducting polymers, polyaniline (PANI) may have the greatest potential for commercial application because of its unique electrochemical properties and environmental stability [1]. Nanostructured ZnO materials have received broad attention due to their distinguished performance in electronics, optics and photonics. From the 1960s, synthesis of ZnO thin films has been an active field because of their applications as sensors, transducers and catalysts [2].
* Corresponding author. Tel.: 0824-2287437; Mob- 09448318252; E-mail address: [email protected]; 2214-7853 © 2017 Elsevier Ltd. All rights reserved. Selection and/or Peer-review under responsibility of Second International Conference on Large Area Flexible Microelectronics (ILAFM 2016): Wearable Electronics, December 20th–22nd, 2016.
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Omprakash S S et al / Materials Today: Proceedings 5 (2018) 10827–10832
2. Method of approach 2.1 Synthesis of PANI, ZnO and ZnO doped PANI Acid treated PANI nanofibers were procured from Aadarsh Innovations, Pune, Maharashtra, India and Zno is synthesized as follows. ZnO synthesized by sol-gel method. In a typical synthesis process, 4g of zinc acetate dehydrate was dissolved in 50ml of 2-methoxyethanol. The solution was kept in a magnetic stirrer at 600 temperatures. During stirring a few drops of mono-ethanolamine was added which acts as a stabilizer of the solution. Thus a ZnO solution was prepared. The stirring is continued for 2hrs until a transparent and homogeneous solution was obtained. The prepared solution is aged for overnight at room temperature to get ZnO. The procured PANI and synthesized ZnO solutions were mixed in a ratio of 5:1 respectively. The obtained solution was magnetically stirred for 30 min at a temperature of 60˚C. 2.2 Film deposition and characterization PANI and PANI/ZnOwas coated on the substrate using drop cast method at a height of 10 cm above the substrate in the ambient air at room temperature and allowed to dry for 30 min. The surface morphology of the coated material has been carried out using FESEM. Thickness of the material coated on the substrate has been analyzed using surface profiler. Study of the resistance of the film was done. 2.3
Device fabrication and characterization
The cellulose acetate was cleaned using acetone and ethanol and dried using hot air blower. The PANI and PANI/ZnO was coated using drop cast method. ~1500A˚ thick silver electrodes were coated by means of screen printing technique, for gate, drain and source with W/L as 0.5:10 mm. Electrical characteristics such as I-V characteristics and input and output characteristics of TFT were carried out. One of the basic logic gate i.e., NAND gate was designed using PANI/ZnO TFT and tested for its output voltages. 3. Result and Discussion 3.1 Preparation of ZnO doped PANI Thin Film Transistor is constructed using PANI/ZnO as semiconducting material with Cellulose acetate sheet as substrate, with silver as its electrodes. Organic PANI in chloroform is mixed with ZnO liquid using magnetic stirrer. The mixture of two solution forms hybrid material.
Figure 1 (a) PANI coated on Cellulose Acetate sheet (b) PANI/ZnO coated on Cellulose Acetate sheet (c) Gate electrode of TFT (d) Source and drain electrode ofTFT
Omprakash S S et al / Materials Today: Proceedings 5 (2018) 10827–10832
10829
The PANI in chloroform was mixed with ZnO using magnetic stirrer in the ratio of 5:1 respectively. PANI and PANI/ZnO were coated on substrate. The coated hybrid material is then used as TFT with its gate, source and drain electrodes shown in Figure 1 (c) and (d) respectively. 3.2 Characterization The coated PANI and hybrid material is then studied for its structural and electrical characterization. 3.2.1
Structural characterization
In structural characterization Thickness of the PANI was 4000 A˚ while that of PANI/ZnO was 6000 A˚ through surface profiler i.e., Dektak instrument. Surface morphology was study using FESEM. The Figure 2 (a) and (b) is the FESEM image of PANIand PANI/ZnO on substrate.
Figure 2 (a) FESEM image of PANI (b) FESEM image of PANI/ZnO
3.2.2
Electrical Characterization
3.2.2.1 Thin Film’s Electrical Characterization
Figure 3 (a) I-V characterization of PANI (b) I-V characterization of PANI/ZnO
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Omprakash S S et al / Materials Today: Proceedings 5 (2018) 10827–10832
The electrical characterization such as Resistance of the active layers (semiconductor layer) and Input and output Characteristics of the MOS device were also performed and analyzed. I-V measurement was taken, and the result shows that there is vast decrease in resistance, when PANI doped with ZnO. With in-house developed probe station electrical characterization has been carried out. From the graph Figure 3(a) and 3(b)) we can observe that resistance of the PANI material was found to be nearly much higher i.e., 90MΩ while that of PANI/ZnO is ~1MΩ at room temperature. There was one order change in drain current i.e., Id. Device characteristics have been carried out for PANI and PANI doped ZnO. 3.2.2.1 Thin Film Transistor (TFT) Electrical Characterization
Figure 4 (a) Id vs Vg for PANI (b) Id vs Vg for PANI/ZnO (c) Id vs Vd for PANI (d) Id vs Vd for PANI/ZnO
The input characteristic of PANI is as shown in Figure 4 (a), the threshold voltage is observed to be 4.3V. The output characteristic of PANI is as shown in Figure 4 (c), the pinch off voltage is observed to be 5.2V. The input characteristic of ZnO doped PANI is as shown in Figure 4 (b), the threshold voltage is observed to be 2.75V. The output characteristic of ZnO doped PANI is as shown in Figure 4 (d), the threshold voltage is observed to be 3.3V. ZnO doped PANI exhibits more superior qualities such as, one order increase in the drain current and lower threshold voltage Vth= 2.75V. ZnO doped PANI exhibits lower pinch off voltage as compared with PANI. Hence we have constructed NAND gate using ZnO doped PANI material.
Omprakash S S et al / Materials Today: Proceedings 5 (2018) 10827–10832
3.3
10831
Logic gate
Using Hybrid Thin Film Transistor, one of the logic gate i.e., NAND gate was designed, constructed and tested for its output voltage. The circuit is [3]
Figure 5 NAND gate circuit, Ref. [3]
A p type logic circuit for NAND gate is shown in Figure5, by constructing this logic circuit using TFT, the output was noted down and compared with its logical output. NAND gates are the fundamental building block for implementing larger scale digital circuits. 3.4
Measurement condition
The supply voltage was 12V and input voltage was 5V, the NAND gate was tested for the different logical state. The obtained results are shown in Table 1. Table 1 Output voltage of NAND gate as observed
A
B
0
l
l
(AB) V
(AB)
0
3.4
1
0
1
3.5
1
1
0
3.5
1
1
1
0.9
0
Figure 6 (a) Image of gate terminal connection (b) Image of source and drain terminal connection
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Omprakash S S et al / Materials Today: Proceedings 5 (2018) 10827–10832
In Figure 6 the NAND gate constructed upon the cellulose acetate sheet is shown. Since the design of gate was done in the ambient air at room temperature, the results were not repeatable. Further a passivation layer may be coated for the stability of the device. 4. CONCLUTION Using PANI as organic material and ZnO as inorganic material, hybrid material is synthesized using magnetic stirrer. This hybrid material was then coated upon the insulator i.e., cellulose acetate sheet which acts as substrate. The coated material is then studied for its surface morphology, roughness and thickness. The resistance of the coated film had been study. Later the TFT has been constructed electrical properties is carried out. By use of these TFT, NAND gates had been design and tested further. References [1] Wen-Chin Chiou, Jin-Lin Han, Sung-Nung Lee Synthesis and Studies of the Physical Properties of Polyaniline and Polyurethane-Modified Epoxy Composites. (2007) [2] Zhong Lin Wang Zinc oxide nanostructures: growth, properties and applications. (2004) R829–R858 [3] Tsung-Ching Huang, Member, IEEE, Kenjiro Fukuda, Chun-Ming Lo, Yung-HuiYeh, Member, IEEE,TsuyoshiSekitani, Takao Someya, Member, IEEE, and Kwang-Ting Cheng, Fellow, IEEE Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics(2011) VOL. 58
ScienceDirect Materials Today: Proceedings 5 (2018) 10827–10832
www.materialstoday.com/proceedings
ILAFM2016
PANI/ZnO Hybrid Nanocomposites TFT for NAND Gate Application. 1
Omprakash S.S1,Naveen Kumar S.K1* Department of Electronics, Mangalore University, Mangalore 574199, India.
Abstract
Thin Film Transistor (TFT) is the key element for future day’s electronic circuit, in which low cost, low temperature, vacuum free process and flexibility of the substrate are the need for the day. With Cellulose acetate substrate as an insulator layer for the TFT, the C-V characteristic had been performed to find the dielectric constant. Polyaniline (PANI) is doped with Zinc Oxide (ZnO), and these Nanocomposites are coated on the substrate. The structure of TFT is achieved by coating electrodes on PANI/ZnO layer and substrate. Study was done on this hybrid structure for its electrical characteristics such as mobility and resistivity. The surface roughness and morphology of PANI/ZnO were characterized by Atomic Force Microscope (AFM) and Scanning Electronic Microscope (SEM). The input and output characteristics of TFT was obtained using I-V measurement system. One of the basic building blocks of digital circuits is NAND gate. The NAND gate is designed, fabricated and tested for its output voltage. Keywords:
TFT, organic polymers semiconductor, Nanocomposites, NAND gate
1. Introduction A thin-film transistor (TFT) is a special kind of field effect transistor made by depositing thin films of an active semiconductor layer as well as the dielectric layer and metallic contacts over a supporting substrate. TFT’s can be made using a wide variety of semiconductor materials. TFT’s include compound semiconductors such as cadmium selenide, or metal oxides such as zinc oxide. TFT’s have also been made using organic materials, referred to as organic field-effect transistors or OTFT’s, one of the organic materials is polyaniline. Among the different types of conducting polymers, polyaniline (PANI) may have the greatest potential for commercial application because of its unique electrochemical properties and environmental stability [1]. Nanostructured ZnO materials have received broad attention due to their distinguished performance in electronics, optics and photonics. From the 1960s, synthesis of ZnO thin films has been an active field because of their applications as sensors, transducers and catalysts [2].
* Corresponding author. Tel.: 0824-2287437; Mob- 09448318252; E-mail address: [email protected]; 2214-7853 © 2017 Elsevier Ltd. All rights reserved. Selection and/or Peer-review under responsibility of Second International Conference on Large Area Flexible Microelectronics (ILAFM 2016): Wearable Electronics, December 20th–22nd, 2016.
10828
Omprakash S S et al / Materials Today: Proceedings 5 (2018) 10827–10832
2. Method of approach 2.1 Synthesis of PANI, ZnO and ZnO doped PANI Acid treated PANI nanofibers were procured from Aadarsh Innovations, Pune, Maharashtra, India and Zno is synthesized as follows. ZnO synthesized by sol-gel method. In a typical synthesis process, 4g of zinc acetate dehydrate was dissolved in 50ml of 2-methoxyethanol. The solution was kept in a magnetic stirrer at 600 temperatures. During stirring a few drops of mono-ethanolamine was added which acts as a stabilizer of the solution. Thus a ZnO solution was prepared. The stirring is continued for 2hrs until a transparent and homogeneous solution was obtained. The prepared solution is aged for overnight at room temperature to get ZnO. The procured PANI and synthesized ZnO solutions were mixed in a ratio of 5:1 respectively. The obtained solution was magnetically stirred for 30 min at a temperature of 60˚C. 2.2 Film deposition and characterization PANI and PANI/ZnOwas coated on the substrate using drop cast method at a height of 10 cm above the substrate in the ambient air at room temperature and allowed to dry for 30 min. The surface morphology of the coated material has been carried out using FESEM. Thickness of the material coated on the substrate has been analyzed using surface profiler. Study of the resistance of the film was done. 2.3
Device fabrication and characterization
The cellulose acetate was cleaned using acetone and ethanol and dried using hot air blower. The PANI and PANI/ZnO was coated using drop cast method. ~1500A˚ thick silver electrodes were coated by means of screen printing technique, for gate, drain and source with W/L as 0.5:10 mm. Electrical characteristics such as I-V characteristics and input and output characteristics of TFT were carried out. One of the basic logic gate i.e., NAND gate was designed using PANI/ZnO TFT and tested for its output voltages. 3. Result and Discussion 3.1 Preparation of ZnO doped PANI Thin Film Transistor is constructed using PANI/ZnO as semiconducting material with Cellulose acetate sheet as substrate, with silver as its electrodes. Organic PANI in chloroform is mixed with ZnO liquid using magnetic stirrer. The mixture of two solution forms hybrid material.
Figure 1 (a) PANI coated on Cellulose Acetate sheet (b) PANI/ZnO coated on Cellulose Acetate sheet (c) Gate electrode of TFT (d) Source and drain electrode ofTFT
Omprakash S S et al / Materials Today: Proceedings 5 (2018) 10827–10832
10829
The PANI in chloroform was mixed with ZnO using magnetic stirrer in the ratio of 5:1 respectively. PANI and PANI/ZnO were coated on substrate. The coated hybrid material is then used as TFT with its gate, source and drain electrodes shown in Figure 1 (c) and (d) respectively. 3.2 Characterization The coated PANI and hybrid material is then studied for its structural and electrical characterization. 3.2.1
Structural characterization
In structural characterization Thickness of the PANI was 4000 A˚ while that of PANI/ZnO was 6000 A˚ through surface profiler i.e., Dektak instrument. Surface morphology was study using FESEM. The Figure 2 (a) and (b) is the FESEM image of PANIand PANI/ZnO on substrate.
Figure 2 (a) FESEM image of PANI (b) FESEM image of PANI/ZnO
3.2.2
Electrical Characterization
3.2.2.1 Thin Film’s Electrical Characterization
Figure 3 (a) I-V characterization of PANI (b) I-V characterization of PANI/ZnO
10830
Omprakash S S et al / Materials Today: Proceedings 5 (2018) 10827–10832
The electrical characterization such as Resistance of the active layers (semiconductor layer) and Input and output Characteristics of the MOS device were also performed and analyzed. I-V measurement was taken, and the result shows that there is vast decrease in resistance, when PANI doped with ZnO. With in-house developed probe station electrical characterization has been carried out. From the graph Figure 3(a) and 3(b)) we can observe that resistance of the PANI material was found to be nearly much higher i.e., 90MΩ while that of PANI/ZnO is ~1MΩ at room temperature. There was one order change in drain current i.e., Id. Device characteristics have been carried out for PANI and PANI doped ZnO. 3.2.2.1 Thin Film Transistor (TFT) Electrical Characterization
Figure 4 (a) Id vs Vg for PANI (b) Id vs Vg for PANI/ZnO (c) Id vs Vd for PANI (d) Id vs Vd for PANI/ZnO
The input characteristic of PANI is as shown in Figure 4 (a), the threshold voltage is observed to be 4.3V. The output characteristic of PANI is as shown in Figure 4 (c), the pinch off voltage is observed to be 5.2V. The input characteristic of ZnO doped PANI is as shown in Figure 4 (b), the threshold voltage is observed to be 2.75V. The output characteristic of ZnO doped PANI is as shown in Figure 4 (d), the threshold voltage is observed to be 3.3V. ZnO doped PANI exhibits more superior qualities such as, one order increase in the drain current and lower threshold voltage Vth= 2.75V. ZnO doped PANI exhibits lower pinch off voltage as compared with PANI. Hence we have constructed NAND gate using ZnO doped PANI material.
Omprakash S S et al / Materials Today: Proceedings 5 (2018) 10827–10832
3.3
10831
Logic gate
Using Hybrid Thin Film Transistor, one of the logic gate i.e., NAND gate was designed, constructed and tested for its output voltage. The circuit is [3]
Figure 5 NAND gate circuit, Ref. [3]
A p type logic circuit for NAND gate is shown in Figure5, by constructing this logic circuit using TFT, the output was noted down and compared with its logical output. NAND gates are the fundamental building block for implementing larger scale digital circuits. 3.4
Measurement condition
The supply voltage was 12V and input voltage was 5V, the NAND gate was tested for the different logical state. The obtained results are shown in Table 1. Table 1 Output voltage of NAND gate as observed
A
B
0
l
l
(AB) V
(AB)
0
3.4
1
0
1
3.5
1
1
0
3.5
1
1
1
0.9
0
Figure 6 (a) Image of gate terminal connection (b) Image of source and drain terminal connection
10832
Omprakash S S et al / Materials Today: Proceedings 5 (2018) 10827–10832
In Figure 6 the NAND gate constructed upon the cellulose acetate sheet is shown. Since the design of gate was done in the ambient air at room temperature, the results were not repeatable. Further a passivation layer may be coated for the stability of the device. 4. CONCLUTION Using PANI as organic material and ZnO as inorganic material, hybrid material is synthesized using magnetic stirrer. This hybrid material was then coated upon the insulator i.e., cellulose acetate sheet which acts as substrate. The coated material is then studied for its surface morphology, roughness and thickness. The resistance of the coated film had been study. Later the TFT has been constructed electrical properties is carried out. By use of these TFT, NAND gates had been design and tested further. References [1] Wen-Chin Chiou, Jin-Lin Han, Sung-Nung Lee Synthesis and Studies of the Physical Properties of Polyaniline and Polyurethane-Modified Epoxy Composites. (2007) [2] Zhong Lin Wang Zinc oxide nanostructures: growth, properties and applications. (2004) R829–R858 [3] Tsung-Ching Huang, Member, IEEE, Kenjiro Fukuda, Chun-Ming Lo, Yung-HuiYeh, Member, IEEE,TsuyoshiSekitani, Takao Someya, Member, IEEE, and Kwang-Ting Cheng, Fellow, IEEE Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics(2011) VOL. 58