- Email: [email protected]
Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology
MR-11809; No of Pages 7 Microelectronics Reliability xxx (2015) xxx–xxx
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr
Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology Tao-Chih Chang b, Chang-Chun Lee a,⁎, Chia-Ping Hsieh c, Sheng-Che Hung b, Ren-Shin Cheng b a
Department of Mechanical Engineering, Chung Yuan Christian University, 200 Chung Pei Road, Chung Li District, Taoyuan City 32023, Taiwan, ROC 3D Stacking and Reliability Technology Department, Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, 195 Sec. 4, Chung-Hsing Road, Chutung, Hsinchu 31040, Taiwan, ROC c Department of Mechanical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei 10617, Taiwan, ROC b
a r t i c l e
i n f o
Article history: Received 22 May 2015 Received in revised form 23 September 2015 Accepted 4 October 2015 Available online xxxx Keywords: Insulated gate bipolar transistor Power module Reliability Chip embedding technology
a b s t r a c t With the current high demand for energy saving and low power consumption, numerous studies have been conducted to meet this requirement. Higher switch efficiency is one of the factors for power saving in power inverters and converters. Among the methods for improved switch efficiency, the modified package structure is one of the solutions. An embedded power module enables shortened transmitting routes and lower parasitic reactions, suggesting better power switching performance. Meanwhile, embedding allows the power devices to integrate active or passive devices above or beneath a component, leading to a three-dimensional packaging structure. This feature is also applicable in the integration of power devices because of its double side contact structure. Four dies that contain two insulated gate bipolar transistors and two diodes in this study were embedded and integrated in a carrier substrate to produce a next-generation power inverter module. The process began by attaching a die on a Cu lead frame by a SAC305 solder paste. This is followed by a lamination process to form a built-up dielectric layer on the Cu lead frame. The conducting vias and circuits were formed on the built-up dielectric layer by a UV laser and were metalized with sputtered seed layer and electroplating. The circuit layout can be revealed with subsequent etching processes by hatching another layer of electroplated Sn using UV laser. Finally, a layer of solder mask was printed to prevent electric shock on the surface layer. Structure and process features are discussed, and electrical testing and reliability tests are conducted in this paper. © 2015 Elsevier Ltd. All rights reserved.
1. Introduction In recent years, the solar industries are all committed to improving the PV system output power. The centralized inverters have been used in solar photovoltaic systems for a long time. However, any module defects may often lead to substantial decline in the overall system. During the repair period, the solar system cannot be connected to the grid and will result in a large output loss. Hence, introducing a micro-inverter can significantly improve the shortcomings of the traditional inverter and improve the efficiency and reliability of solar photovoltaic systems. The micro-inverter module enables the tracking of the maximum output individually. Meanwhile, device-embedded technologies using printed circuit board (PCB)-compatible processes, which form a system-in-package (SiP) structure, have played an important role in the IC packaging industry in recent years. Given that general power or communication components do not have as much I/O contacts as the logic or drawing devices, the embedded package structure that uses PCB technology can generate compact, high-density, and miniaturized
⁎ Corresponding author. E-mail address: [email protected] (C.-C. Lee).
products for modern, portable, and lightweight applications. Embedded technology allows a smaller form factor, a shorter signal transmission route and a reliable packaging structure; thus, it can be successfully used in the mass production of consumer electronics. Embedding discrete semiconductors into substrates can help achieve a high degree of miniaturization and a MOSFET power package based on the embedded die technology [1]. However, insulated gate bipolar transistor (IGBT) fault accident mostly occurs in the package process, wherein some components are prone to damage [2], thus causing thermal fatigue when the device operates, which then leads to solder cracking and peeling terminal [3]. Using pre-curved substrates can eliminate warpage and help achieve proper coplanarity [4]. Due to high power density-generated heat and dissipation by the heat sink through the wafer, metal composite substrate materials have been developed to increase structural stability [5]. Generally, the power cycle test is used to analyze the aluminum bonding wire fatigue of IGBT, the lead solder and tin-silver solder structure, and the contact failure [6–8]. The harmonic changes by the inverter output are also used to monitor the solder fatigue in IGBT [9]. A MOSFET-embedded technology is developed in this study using a PCB-compatible process. The study target is turned to the IGBT module using a similar approach. The details, including process flow, architecture and reliability performance, are also discussed in this paper.
http://dx.doi.org/10.1016/j.microrel.2015.10.004 0026-2714/© 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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T.-C. Chang et al. / Microelectronics Reliability xxx (2015) xxx–xxx
2. Package structure and process The current trend in today's packaging materials is that it should be light, thin, short, and small. The electrical properties of a package can be improved when it has a small size; in relation to this, the use of shorter transmitting path and electrical power module is trending toward the SiP structure. The structure design and electrical simulation of an embedded power module are developed in this study. The specifications are as follows: 600 V/20 A IGBT and diode, two embedded IGBTs, and two diodes of power components forming a half-bridged power module. The power module can be applied to the final output of the power conversion of a PV inverter, in order to reduce the parasitic resistance and parasitic inductance of the original circuit design and enhance the efficiency of the system. Fig. 1(a) and (b) shows the former design of a photovoltaic micro-inverter system and the present design, and the circuit topology is given in Fig. 2. The power rating of the PV module is 200 W, which is very close to those manufactured by the other companies shown in the website of Sunlight Electric (http://www.sunlightelectric. com/pvmodules.php). 2.1. Packaging design Two IGBTs and two diodes were embedded in the package structure. The contact pins contain VCC (P), GND (N), output (O), and two gates (G1 and G2) that control the IGBTs. Thus, the distance between each die can be significantly shortened regardless of the space reserved for wire bonding. Meanwhile, the parasitic resistance and inductance can also be relieved because of the absence of wire bonding. The surge effect (e.g., voltage spike) can be reduced, thus generating a low-loss and reliable power module. The size of the module can also be miniaturized, and it can become a low-profile structure, thereby realizing the advantages of a SiP structure. The specific sizes of the vias were determined in the design of the embedded power module. Two IGBTs and two diodes were embedded using the built-up process. Circuit connection was achieved by blind vias with plated Cu forming the RDL. The thickness of the Cu RDL was 35 μm, and the diameters of the blind vias were 300 and 150 μm for vias from the RDL to the substrate and those from the RDL to the die, respectively. The subsequent simulation was conducted to generalize the parasitic resistance and inductance values of the module. Standard power electronic packages with wire interconnections provide high and unbalanced parasitic capacitances and inductances [10]. In order to acquire the benefit of high frequency switching and low parasitics, embedded technologies have been investigated to reduce the parasitic inductances of fast switching power modules [10–11]. Several package forms exist from commercially available power components, and some low power modules were used as a comparison in this study. For example, the parasitic inductances for SOP 8 were Ls = 1.5 nH, Ld = 3 nH, and Ls + Ld = 6.8 nH for TO-257AA. A power system module is formed by integrating two packages of the
Fig. 2. The circuit topology of the embedded power module.
power device. Therefore, the parasitic inductance may even be larger because the inductance of the metal wire that connects each device should also be considered. The structure profile and the values for comparison are shown in Fig. 3, the parasitic inductance of the embedded power module generalized by simulation is only 2.496 nH (Ls + Ld), which is attributed to a shorter transmission route. As can be seen, it is only one-third of the mentioned commercial modules, showing the potential advantage of the embedded power module. It has been found that the power module packaged by embedded technology show a 16% reduction of voltage spike, compared to that packaged by wire-bonding method [12]. 2.2. Manufacturing process The embedded power module package structure was designed and implemented based on the process flow shown in Fig. 4. The processes were separated to P0 (before process preparation), P1
Fig. 1. PV inverter systems of (a) the former design and (b) the present design using an embedded power module.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
T.-C. Chang et al. / Microelectronics Reliability xxx (2015) xxx–xxx
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Fig. 3. Embedded IGBT module structure and comparison of the parasitic inductance values with conventional power modules.
Fig. 4. Process flow of the embedded IGBT power module.
(die attach process), P2 (built-up process), P3 (redistribution layer forming), and P4 (surface finish and test). Details about these are provided below.
2.2.1. Before process preparation A 500-μm thick Cu lead frame with a special circuit design was used as a carrier to mitigate the warpage of the power module. The assembly
Fig. 5. Cu lead frames before and after oxidation treatment: (a) Formal and (b) half-etched Cu lead frame before and after chemical oxidation.
Table 1 Die information on the two different systems. Chip type
Chip information
Die size
Infineon IGBT SIGC10T60 Infineon IGBT SIDC06D60AC6 Renesas IGBT RJP60V3DWT Renesas IGBT RJU6053DWT
VCES = 600 V IC = 20 A VCES = 600 V IC = 20 A VCES = 600 V IC = 35 A VCES = 600 V IC = 20 A
Thickness
3.19 × 3.21 mm2
75 μm
2.85 × 2 mm2
75 μm
3 × 3 mm
2
80 μm
2 × 2 mm
2
240 μm
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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Table 2 Physical properties of the dielectric material. ABF GX-TH3 CTE (b150 °C) Young's modulus Elongation (%) Filler content
23 7.6 1.7 b68
CTE (N150 °C) Tensile strength Tg (TMA/DMA, °C)
57 90 155/184
process was initiated by oxidizing the Cu carrier by chemicals, and then removing the oxide layer using a Siemens UV laser to form solder pads for die attaching. Fig. 5 shows the Cu lead frames before and after oxidation treatment. Two different lead frames were used for different IGBT dies, and two IGBT and two diodes were integrated in the power module. If the thicknesses of the dies were not identical, the diameters of the drilled vias will not be the same and will lead to badquality electroplating. Therefore, in addition to a formally designed Cu lead frame, another half-etched Cu lead frame was prepared for the integration of dies with different thickness values. 2.2.2. Die attach process The processes involved solder printing, die placement, reflow, and final cleaning to remove the residual flux. At the solder printing status, the printing window for the device was shrunk to 80% of the original length and width to prevent the excess solder paste from allowing the dies to float during reflow. SAC 305 solder paste was used as the conductive adhesive, and Ag paste was dispensed for the half-etching area. The dies, which included IGBTs and diodes, were subsequently placed on the solder/Ag paste printed/dispensed area by die bonder using the pick-and-place process with high accuracy (b10 μm). The die information is listed in Table 1. Two die systems, Infineon and Renesas, were used in this process. The die size and die thickness were different from each other. The Infineon die system was used in the formal Cu lead frame to obtain better electroplating result, whereas the Renesas system was used in the halfetched Cu lead frame because the thickness of the diode was larger than the IGBT. The thick diode was also placed in the half-etched area on the Cu lead frame. The reflow process with the maximum peak temperature of approximately 260 °C was subsequently performed to conductively fasten the dies on the lead frame. The final cleaning process, which used IPA and DI water, was conducted to completely remove the residual flux in the solder. 2.2.3. Built-up process The dielectric material used in this process was ABF GX-TH3 (thickness = 200 μm). Information about the material is listed in Table 2. The process parameters were carefully evaluated to obtain the proper dielectric thickness. The dielectric thickness required was approximately 100 μm to fully cover the dies and form an RDL layer. The ABF material must flow into the gaps between each block of the lead frame and form insulation; hence, two layers of 200-μm thick ABF material were laminated to form a thicker material sheet before laminating to the lead
frame. After lamination and curing, the module was subsequently followed by laser drilling for blind vias. The via sizes on the dies and lead frames were 150 and 300 μm, respectively. Given that no preformed UBM existed on the dies, the laser parameters were carefully adjusted to prevent them from damaging the Al pad on the die. The drilled vias are shown in Fig. 6, which shows an un-damaged Al pad on the IGBT die. 2.2.4. Redistribution layer formation The general re-distribution layer forming process involves desmearing, electroless plating Cu (seed layer), photolithography and electroplating, followed by dry film (photo resist) stripping and seed layer etching. Given that no UBM is formed on the Al pad of the dies in this study, performing the de-smearing process before the electroless Cu plating is not possible. Meanwhile, the ABF material used in this study may not be compatible with the conventional semi-additive process. The seed layer was formed using sputtering Ti/Cu (approximately 0.1/0.3 μm) technique and direct Cu electroplating. The thickness of the plated Cu was approximately 35 μm. An additional 1 μm-thick Sn layer was subsequently plated as a patterning mask. The laser skiving process removes the Sn above the Cu layer and forms a circuit pattern. Thereafter, the etching of Cu, Sn, and Ti processes was performed to remove the metal on the dielectric layer, thus forming the required circuit pattern. 2.2.5. Surface finishing and testing After an additional insulation layer was deposited on the RDL, the Cu lead frame-based module was singularized to accomplish the whole package process. The final insulation layer can be created using the screening printing solder mask or by merely laminating an additional ABF layer. Both materials can meet the demand of insulation. The schematic of the whole package process, together with the photo of the module at the process stage, is shown in Fig. 7. Fig. 8 shows the top, back, and side views of the packaged power module, all of which indicate a low-profile integrated package form. The electrical property inspection of the embedded half-bridged 20 A IGBT-FWD power module was performed via the curve tracer. The values of Vces/Ices, Vges/Iges, Vge(th), Vce(sat)/Ic, and Vf/If were inspected to check whether the module can normally function. The curve tracer equipment used was Iwatsu CS3300 (shown in Fig. 7). The inspection method was conducted by connecting specific wires to the sample based on the pin assignment. Fig. 9 shows the wires welded to the back side of the embedded IGBT power module and the schematic of the circuit. The samples that passed the inspection of the curve tracer subsequently underwent a reliability test. 3. Early failure screened by preconditioning In order to learn the stability of the architecture and the possible root-causes of early failure, the preconditioning test [13] or so-called moisture sensitivity level 3 [14] was conducted on the embedded IGBT power module. Samples were stored in 30 °C/60% humidity for 192 h, and then experienced reflow (peak temperature = 260 °C) thrice. The
Fig. 6. Blind via formed by laser drilling. (a) Top view and (b) cross-section view, showing no damage to the Al pad.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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Fig. 7. Schematic of the whole package process.
total amount of the tested sample was 32, and only two among these samples failed. Failure analysis was conducted on the failed samples. The cross-section view of the IGBT die is shown in Fig. 10. Die cracks and uneven solder joints were found at the interface between the die and the Cu lead frame. The conductive connection was achieved by solder printing and reflow. However, when the sample experienced a pre-condition test, the solder interface may have been re-melted as viscous fluid. When it solidified after the final cooling stage of reflow, this
resulted in uneven interface and stress concentration, thus leading to die cracks. In the conventional power modules, lifting of bonding wires has been pointed out being one of the failure mechanisms of power modules [15–16], since there is no bonding wire within the embedded power module, it is believed that the electroplated Cu circuit shall give an opportunity to improve the power module instead of wire bonding interconnection. Furthermore, Pederson et al. [17] have disclosed an
Fig. 8. Package accomplishment in the (a) top view, (b) back view, and (c) side view.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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Fig. 11. Ag paste-sintered joint remains stable after the reliability test.
Fig. 9. Wires welded to the back side of the embedded IGBT: (a) Curve tracer Iwatsu CS3300, (b) wires welded to the module, and (c) schematic of the circuit.
efficient four-point probing approach to assess the degradation type, speed, and distribution through different components as a function of stress and time, as well as helps to optimize the module design. The test circuits can be easily designed-in the newly developed embedded power modules to predict the lifetime by real-time measurement. Thermal dissipation is a big concern for embedded power modules [18], that's why the technology is only adopted to package power devices with a rated current less than 50 A, such as Infineon's DrBlade series (a DC/DC solution for server's power management), and the die size is small. The aim of the present research is to use the so-called embedded technologies to package some high rated voltage/high rated current power devices and extend the application fields of the power modules. For this purpose, the die size of the power devices would get larger, which significantly impact the package yield and reliability of embedded power modules because of a larger warpage. In order to reduce the stress/strain concentrated at the interface, a new die attaching method shall be studied to acquire a level joint. Meanwhile, given that the joint of the diode was formed by Ag paste, the joint remained stable after the pre-condition test, as shown in Fig. 11. This condition is explained by the fact that the Ag joint has a high melting point, which allowed the interface to maintain its reliability even after reflow. With regards power modules, developing a hightemperature stable conductive joint is necessary to prevent hightemperature failure or creep. When the developing trend of power
devices moves toward the use of SiC-based components, the even higher junction temperature can become a critical issue in the reliability of the conductive interconnections. ITRI has recently investigated a hightemperature stable joint using the solid–liquid inter-diffusion technology or silver sintering. Both processes of the technologies can be performed below 250 °C, and the resulting joint can remain stable at 400 °C or higher, providing a reasonable and reliable solution for power modules with high junction temperature. 4. Conclusions The overall area was decreased by integrating innovative package designs, including the embedded IGBT module introduced in this study. The results indicated a miniaturized, high-density integrated form of the modern inverter system. Power modules that use embedding technology can reduce the parasitic inductance based on the numerical simulations. The voltage spike also decreased during the direct electrical inspection. Meanwhile, power modules were compared with conventional modules, and the results suggested a low-loss and reliable application. A low-profile power module is beneficial in attaching an extra heat sink for heat dissipation. Process characteristics were also described in this study, and reliability issues were provided. A conductive joint with high-temperature stability is a major study area in the application of power modules. Dielectric materials with high thermal conductivity may also serve as key materials in developing innovative power modules in the future. Acknowledgments The authors would like to thank the Department of Industrial Technology, MOEA, Taiwan for supporting this research, as well as
Fig. 10. Cross-section view of the IGBT: (a) Die crack and (b) solder depletion were found in the failed sample after the reliability test.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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the Ministry of Science and Technology, Taiwan, ROC for providing the financial support under contract number MOST 103-2221-E033-005-MY3. References [1] D. Yang, M. Kengen, W.G.M. Peels, D. Heyes, W.D. van Driel, Reliability modeling on a MOSFET power package based on embedded die technology, Microelectron. Reliab. 50 (2010) 923–927. [2] H. Huang, P.A. Mawby, A lifetime estimation technique for voltage source inverters, IEEE Trans. Power Electron. 28 (2013) 4113–4119. [3] Z. Khatir, S. Lefebvre, Boundary element analysis of thermal fatigue effects on high power IGBT modules, Microelectron. Reliab. 44 (2004) 929–938. [4] C.C. Lee, K.S. Kao, L. Lin, et al., Investigation of pre-bending substrate design in packaging assembly of an IGBT power module, Microelectron. Eng. 120 (2014) 106–113. [5] M. Schoebel, W. Altendorfer, H.P. Degischer, et al., Internal stresses and voids in SiC particle reinforced aluminum composites for heat sink applications, Compos. Sci. Technol. 71 (2011) 724–733. [6] J.M. Thebaud, E. Woirgard, C. Zardini, S. Azzopardi, O. Briat, J.M. Vinassa, Strategy for designing accelerated aging tests to evaluate IGBT power modules lifetime in real operation mode, IEEE Trans. Compon. Packag. Technol. 26 (2003) 429–438. [7] O. Schilling, M. Schaefer, K. Mainka, M. Thoben, F. Sauerland, Power cycling testing and FE modelling focussed on Al wire bond fatigue in high power IGBT modules, Microelectron. Reliab. 52 (2012) 2347–2352. [8] A. Morozumi, K. Yamada, T. Miyasaka, S. Sumi, Y. Seki, Reliability of power cycling for IGBT power semiconductor modules, IEEE Trans. Ind. Appl. 39 (2003) 665–671.
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[9] D. Xiang, L. Ran, P. Tavner, S. Yang, A. Bryant, P. Mawby, Condition monitoring power module solder fatigue using inverter harmonic identification, IEEE Trans. Power Electron. 27 (2012) 235–247. [10] G. Feix, E. Hoene, O. Zeiter, K. Pedersen, Embedded very fast switching module for SiC power MOSFETs, PCIM Europe, May 19–21, 2015 (Nuremberg). [11] E. Hoene, A. Ostmann, L.B. The, C. Marczok, A. Müsing, J.W. Kolar, Ultra-low inductance power module for fast switching semiconductors, PCIM Europe, May 14–16, 2013 (Nuremberg). [12] Y.P. Hung, et al., Electrical characteristics and reliability performance of a novel MOSFETs-embedded power module for mobile applications, ICEP-IAAC, April 17–20, 2012 (Tokyo). [13] Preconditioning of nonhermetic surface mount devices prior to reliability test, JESD22-A113D, 2003. [14] Moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices, IPC/JEDEC J-STD-020D.1, 2008. [15] E. Özkol, F. Brem, C. Liu, Improving the power cycling performance of IGBT modules by plating the emitter contact, Microelectron. Reliab. 55 (2015) 552–557. [16] H. Oh, B. Han, P. McCluskey, C. Han, B.D. Youn, Physics-of-failure, condition monitoring, and prognostics of insulated gate bipolar transistor modules: a review, IEEE Trans. Power Electron. 30 (2015) 2413–2426. [17] K.B. Pedersen, P.K. Kristensen, V. Popok, K. Pedersen, Degradation assessment in IGBT modules using four-point probing approach, IEEE Trans. Power Electron. 30 (2015) 2405–2412. [18] D. Yang, M. Kengen, W.G.M. Peels, D. Heyes, W.D. Driel, Reliability modelling on a MOSFET power package based on embedded die technology, Microelectron. Reliab. 50 (2010) 923–927.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr
Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology Tao-Chih Chang b, Chang-Chun Lee a,⁎, Chia-Ping Hsieh c, Sheng-Che Hung b, Ren-Shin Cheng b a
Department of Mechanical Engineering, Chung Yuan Christian University, 200 Chung Pei Road, Chung Li District, Taoyuan City 32023, Taiwan, ROC 3D Stacking and Reliability Technology Department, Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, 195 Sec. 4, Chung-Hsing Road, Chutung, Hsinchu 31040, Taiwan, ROC c Department of Mechanical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei 10617, Taiwan, ROC b
a r t i c l e
i n f o
Article history: Received 22 May 2015 Received in revised form 23 September 2015 Accepted 4 October 2015 Available online xxxx Keywords: Insulated gate bipolar transistor Power module Reliability Chip embedding technology
a b s t r a c t With the current high demand for energy saving and low power consumption, numerous studies have been conducted to meet this requirement. Higher switch efficiency is one of the factors for power saving in power inverters and converters. Among the methods for improved switch efficiency, the modified package structure is one of the solutions. An embedded power module enables shortened transmitting routes and lower parasitic reactions, suggesting better power switching performance. Meanwhile, embedding allows the power devices to integrate active or passive devices above or beneath a component, leading to a three-dimensional packaging structure. This feature is also applicable in the integration of power devices because of its double side contact structure. Four dies that contain two insulated gate bipolar transistors and two diodes in this study were embedded and integrated in a carrier substrate to produce a next-generation power inverter module. The process began by attaching a die on a Cu lead frame by a SAC305 solder paste. This is followed by a lamination process to form a built-up dielectric layer on the Cu lead frame. The conducting vias and circuits were formed on the built-up dielectric layer by a UV laser and were metalized with sputtered seed layer and electroplating. The circuit layout can be revealed with subsequent etching processes by hatching another layer of electroplated Sn using UV laser. Finally, a layer of solder mask was printed to prevent electric shock on the surface layer. Structure and process features are discussed, and electrical testing and reliability tests are conducted in this paper. © 2015 Elsevier Ltd. All rights reserved.
1. Introduction In recent years, the solar industries are all committed to improving the PV system output power. The centralized inverters have been used in solar photovoltaic systems for a long time. However, any module defects may often lead to substantial decline in the overall system. During the repair period, the solar system cannot be connected to the grid and will result in a large output loss. Hence, introducing a micro-inverter can significantly improve the shortcomings of the traditional inverter and improve the efficiency and reliability of solar photovoltaic systems. The micro-inverter module enables the tracking of the maximum output individually. Meanwhile, device-embedded technologies using printed circuit board (PCB)-compatible processes, which form a system-in-package (SiP) structure, have played an important role in the IC packaging industry in recent years. Given that general power or communication components do not have as much I/O contacts as the logic or drawing devices, the embedded package structure that uses PCB technology can generate compact, high-density, and miniaturized
⁎ Corresponding author. E-mail address: [email protected] (C.-C. Lee).
products for modern, portable, and lightweight applications. Embedded technology allows a smaller form factor, a shorter signal transmission route and a reliable packaging structure; thus, it can be successfully used in the mass production of consumer electronics. Embedding discrete semiconductors into substrates can help achieve a high degree of miniaturization and a MOSFET power package based on the embedded die technology [1]. However, insulated gate bipolar transistor (IGBT) fault accident mostly occurs in the package process, wherein some components are prone to damage [2], thus causing thermal fatigue when the device operates, which then leads to solder cracking and peeling terminal [3]. Using pre-curved substrates can eliminate warpage and help achieve proper coplanarity [4]. Due to high power density-generated heat and dissipation by the heat sink through the wafer, metal composite substrate materials have been developed to increase structural stability [5]. Generally, the power cycle test is used to analyze the aluminum bonding wire fatigue of IGBT, the lead solder and tin-silver solder structure, and the contact failure [6–8]. The harmonic changes by the inverter output are also used to monitor the solder fatigue in IGBT [9]. A MOSFET-embedded technology is developed in this study using a PCB-compatible process. The study target is turned to the IGBT module using a similar approach. The details, including process flow, architecture and reliability performance, are also discussed in this paper.
http://dx.doi.org/10.1016/j.microrel.2015.10.004 0026-2714/© 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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2. Package structure and process The current trend in today's packaging materials is that it should be light, thin, short, and small. The electrical properties of a package can be improved when it has a small size; in relation to this, the use of shorter transmitting path and electrical power module is trending toward the SiP structure. The structure design and electrical simulation of an embedded power module are developed in this study. The specifications are as follows: 600 V/20 A IGBT and diode, two embedded IGBTs, and two diodes of power components forming a half-bridged power module. The power module can be applied to the final output of the power conversion of a PV inverter, in order to reduce the parasitic resistance and parasitic inductance of the original circuit design and enhance the efficiency of the system. Fig. 1(a) and (b) shows the former design of a photovoltaic micro-inverter system and the present design, and the circuit topology is given in Fig. 2. The power rating of the PV module is 200 W, which is very close to those manufactured by the other companies shown in the website of Sunlight Electric (http://www.sunlightelectric. com/pvmodules.php). 2.1. Packaging design Two IGBTs and two diodes were embedded in the package structure. The contact pins contain VCC (P), GND (N), output (O), and two gates (G1 and G2) that control the IGBTs. Thus, the distance between each die can be significantly shortened regardless of the space reserved for wire bonding. Meanwhile, the parasitic resistance and inductance can also be relieved because of the absence of wire bonding. The surge effect (e.g., voltage spike) can be reduced, thus generating a low-loss and reliable power module. The size of the module can also be miniaturized, and it can become a low-profile structure, thereby realizing the advantages of a SiP structure. The specific sizes of the vias were determined in the design of the embedded power module. Two IGBTs and two diodes were embedded using the built-up process. Circuit connection was achieved by blind vias with plated Cu forming the RDL. The thickness of the Cu RDL was 35 μm, and the diameters of the blind vias were 300 and 150 μm for vias from the RDL to the substrate and those from the RDL to the die, respectively. The subsequent simulation was conducted to generalize the parasitic resistance and inductance values of the module. Standard power electronic packages with wire interconnections provide high and unbalanced parasitic capacitances and inductances [10]. In order to acquire the benefit of high frequency switching and low parasitics, embedded technologies have been investigated to reduce the parasitic inductances of fast switching power modules [10–11]. Several package forms exist from commercially available power components, and some low power modules were used as a comparison in this study. For example, the parasitic inductances for SOP 8 were Ls = 1.5 nH, Ld = 3 nH, and Ls + Ld = 6.8 nH for TO-257AA. A power system module is formed by integrating two packages of the
Fig. 2. The circuit topology of the embedded power module.
power device. Therefore, the parasitic inductance may even be larger because the inductance of the metal wire that connects each device should also be considered. The structure profile and the values for comparison are shown in Fig. 3, the parasitic inductance of the embedded power module generalized by simulation is only 2.496 nH (Ls + Ld), which is attributed to a shorter transmission route. As can be seen, it is only one-third of the mentioned commercial modules, showing the potential advantage of the embedded power module. It has been found that the power module packaged by embedded technology show a 16% reduction of voltage spike, compared to that packaged by wire-bonding method [12]. 2.2. Manufacturing process The embedded power module package structure was designed and implemented based on the process flow shown in Fig. 4. The processes were separated to P0 (before process preparation), P1
Fig. 1. PV inverter systems of (a) the former design and (b) the present design using an embedded power module.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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Fig. 3. Embedded IGBT module structure and comparison of the parasitic inductance values with conventional power modules.
Fig. 4. Process flow of the embedded IGBT power module.
(die attach process), P2 (built-up process), P3 (redistribution layer forming), and P4 (surface finish and test). Details about these are provided below.
2.2.1. Before process preparation A 500-μm thick Cu lead frame with a special circuit design was used as a carrier to mitigate the warpage of the power module. The assembly
Fig. 5. Cu lead frames before and after oxidation treatment: (a) Formal and (b) half-etched Cu lead frame before and after chemical oxidation.
Table 1 Die information on the two different systems. Chip type
Chip information
Die size
Infineon IGBT SIGC10T60 Infineon IGBT SIDC06D60AC6 Renesas IGBT RJP60V3DWT Renesas IGBT RJU6053DWT
VCES = 600 V IC = 20 A VCES = 600 V IC = 20 A VCES = 600 V IC = 35 A VCES = 600 V IC = 20 A
Thickness
3.19 × 3.21 mm2
75 μm
2.85 × 2 mm2
75 μm
3 × 3 mm
2
80 μm
2 × 2 mm
2
240 μm
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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Table 2 Physical properties of the dielectric material. ABF GX-TH3 CTE (b150 °C) Young's modulus Elongation (%) Filler content
23 7.6 1.7 b68
CTE (N150 °C) Tensile strength Tg (TMA/DMA, °C)
57 90 155/184
process was initiated by oxidizing the Cu carrier by chemicals, and then removing the oxide layer using a Siemens UV laser to form solder pads for die attaching. Fig. 5 shows the Cu lead frames before and after oxidation treatment. Two different lead frames were used for different IGBT dies, and two IGBT and two diodes were integrated in the power module. If the thicknesses of the dies were not identical, the diameters of the drilled vias will not be the same and will lead to badquality electroplating. Therefore, in addition to a formally designed Cu lead frame, another half-etched Cu lead frame was prepared for the integration of dies with different thickness values. 2.2.2. Die attach process The processes involved solder printing, die placement, reflow, and final cleaning to remove the residual flux. At the solder printing status, the printing window for the device was shrunk to 80% of the original length and width to prevent the excess solder paste from allowing the dies to float during reflow. SAC 305 solder paste was used as the conductive adhesive, and Ag paste was dispensed for the half-etching area. The dies, which included IGBTs and diodes, were subsequently placed on the solder/Ag paste printed/dispensed area by die bonder using the pick-and-place process with high accuracy (b10 μm). The die information is listed in Table 1. Two die systems, Infineon and Renesas, were used in this process. The die size and die thickness were different from each other. The Infineon die system was used in the formal Cu lead frame to obtain better electroplating result, whereas the Renesas system was used in the halfetched Cu lead frame because the thickness of the diode was larger than the IGBT. The thick diode was also placed in the half-etched area on the Cu lead frame. The reflow process with the maximum peak temperature of approximately 260 °C was subsequently performed to conductively fasten the dies on the lead frame. The final cleaning process, which used IPA and DI water, was conducted to completely remove the residual flux in the solder. 2.2.3. Built-up process The dielectric material used in this process was ABF GX-TH3 (thickness = 200 μm). Information about the material is listed in Table 2. The process parameters were carefully evaluated to obtain the proper dielectric thickness. The dielectric thickness required was approximately 100 μm to fully cover the dies and form an RDL layer. The ABF material must flow into the gaps between each block of the lead frame and form insulation; hence, two layers of 200-μm thick ABF material were laminated to form a thicker material sheet before laminating to the lead
frame. After lamination and curing, the module was subsequently followed by laser drilling for blind vias. The via sizes on the dies and lead frames were 150 and 300 μm, respectively. Given that no preformed UBM existed on the dies, the laser parameters were carefully adjusted to prevent them from damaging the Al pad on the die. The drilled vias are shown in Fig. 6, which shows an un-damaged Al pad on the IGBT die. 2.2.4. Redistribution layer formation The general re-distribution layer forming process involves desmearing, electroless plating Cu (seed layer), photolithography and electroplating, followed by dry film (photo resist) stripping and seed layer etching. Given that no UBM is formed on the Al pad of the dies in this study, performing the de-smearing process before the electroless Cu plating is not possible. Meanwhile, the ABF material used in this study may not be compatible with the conventional semi-additive process. The seed layer was formed using sputtering Ti/Cu (approximately 0.1/0.3 μm) technique and direct Cu electroplating. The thickness of the plated Cu was approximately 35 μm. An additional 1 μm-thick Sn layer was subsequently plated as a patterning mask. The laser skiving process removes the Sn above the Cu layer and forms a circuit pattern. Thereafter, the etching of Cu, Sn, and Ti processes was performed to remove the metal on the dielectric layer, thus forming the required circuit pattern. 2.2.5. Surface finishing and testing After an additional insulation layer was deposited on the RDL, the Cu lead frame-based module was singularized to accomplish the whole package process. The final insulation layer can be created using the screening printing solder mask or by merely laminating an additional ABF layer. Both materials can meet the demand of insulation. The schematic of the whole package process, together with the photo of the module at the process stage, is shown in Fig. 7. Fig. 8 shows the top, back, and side views of the packaged power module, all of which indicate a low-profile integrated package form. The electrical property inspection of the embedded half-bridged 20 A IGBT-FWD power module was performed via the curve tracer. The values of Vces/Ices, Vges/Iges, Vge(th), Vce(sat)/Ic, and Vf/If were inspected to check whether the module can normally function. The curve tracer equipment used was Iwatsu CS3300 (shown in Fig. 7). The inspection method was conducted by connecting specific wires to the sample based on the pin assignment. Fig. 9 shows the wires welded to the back side of the embedded IGBT power module and the schematic of the circuit. The samples that passed the inspection of the curve tracer subsequently underwent a reliability test. 3. Early failure screened by preconditioning In order to learn the stability of the architecture and the possible root-causes of early failure, the preconditioning test [13] or so-called moisture sensitivity level 3 [14] was conducted on the embedded IGBT power module. Samples were stored in 30 °C/60% humidity for 192 h, and then experienced reflow (peak temperature = 260 °C) thrice. The
Fig. 6. Blind via formed by laser drilling. (a) Top view and (b) cross-section view, showing no damage to the Al pad.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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Fig. 7. Schematic of the whole package process.
total amount of the tested sample was 32, and only two among these samples failed. Failure analysis was conducted on the failed samples. The cross-section view of the IGBT die is shown in Fig. 10. Die cracks and uneven solder joints were found at the interface between the die and the Cu lead frame. The conductive connection was achieved by solder printing and reflow. However, when the sample experienced a pre-condition test, the solder interface may have been re-melted as viscous fluid. When it solidified after the final cooling stage of reflow, this
resulted in uneven interface and stress concentration, thus leading to die cracks. In the conventional power modules, lifting of bonding wires has been pointed out being one of the failure mechanisms of power modules [15–16], since there is no bonding wire within the embedded power module, it is believed that the electroplated Cu circuit shall give an opportunity to improve the power module instead of wire bonding interconnection. Furthermore, Pederson et al. [17] have disclosed an
Fig. 8. Package accomplishment in the (a) top view, (b) back view, and (c) side view.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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Fig. 11. Ag paste-sintered joint remains stable after the reliability test.
Fig. 9. Wires welded to the back side of the embedded IGBT: (a) Curve tracer Iwatsu CS3300, (b) wires welded to the module, and (c) schematic of the circuit.
efficient four-point probing approach to assess the degradation type, speed, and distribution through different components as a function of stress and time, as well as helps to optimize the module design. The test circuits can be easily designed-in the newly developed embedded power modules to predict the lifetime by real-time measurement. Thermal dissipation is a big concern for embedded power modules [18], that's why the technology is only adopted to package power devices with a rated current less than 50 A, such as Infineon's DrBlade series (a DC/DC solution for server's power management), and the die size is small. The aim of the present research is to use the so-called embedded technologies to package some high rated voltage/high rated current power devices and extend the application fields of the power modules. For this purpose, the die size of the power devices would get larger, which significantly impact the package yield and reliability of embedded power modules because of a larger warpage. In order to reduce the stress/strain concentrated at the interface, a new die attaching method shall be studied to acquire a level joint. Meanwhile, given that the joint of the diode was formed by Ag paste, the joint remained stable after the pre-condition test, as shown in Fig. 11. This condition is explained by the fact that the Ag joint has a high melting point, which allowed the interface to maintain its reliability even after reflow. With regards power modules, developing a hightemperature stable conductive joint is necessary to prevent hightemperature failure or creep. When the developing trend of power
devices moves toward the use of SiC-based components, the even higher junction temperature can become a critical issue in the reliability of the conductive interconnections. ITRI has recently investigated a hightemperature stable joint using the solid–liquid inter-diffusion technology or silver sintering. Both processes of the technologies can be performed below 250 °C, and the resulting joint can remain stable at 400 °C or higher, providing a reasonable and reliable solution for power modules with high junction temperature. 4. Conclusions The overall area was decreased by integrating innovative package designs, including the embedded IGBT module introduced in this study. The results indicated a miniaturized, high-density integrated form of the modern inverter system. Power modules that use embedding technology can reduce the parasitic inductance based on the numerical simulations. The voltage spike also decreased during the direct electrical inspection. Meanwhile, power modules were compared with conventional modules, and the results suggested a low-loss and reliable application. A low-profile power module is beneficial in attaching an extra heat sink for heat dissipation. Process characteristics were also described in this study, and reliability issues were provided. A conductive joint with high-temperature stability is a major study area in the application of power modules. Dielectric materials with high thermal conductivity may also serve as key materials in developing innovative power modules in the future. Acknowledgments The authors would like to thank the Department of Industrial Technology, MOEA, Taiwan for supporting this research, as well as
Fig. 10. Cross-section view of the IGBT: (a) Die crack and (b) solder depletion were found in the failed sample after the reliability test.
Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004
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Please cite this article as: T.-C. Chang, et al., Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.10.004