HfO2 gate stacks

Journal of Non-Crystalline Solids 351 (2005) 1902–1905 www.elsevier.com/locate/jnoncrysol

Electrical characteristics of Ge/GeOx(N)/HfO2 gate stacks M. Houssa

a,*

, B. De Jaeger a, A. Delabie a, S. Van Elshocht a, V.V. AfanasÕev b, J.L. Autran c, A. Stesmans b, M. Meuris a, M.M. Heyns a b

a IMEC, 75 Kapeldreef, B-3001 Leuven, Belgium Department of Physics, University of Leuven, B-3001 Leuven, Belgium c L2MP, UMR CNRS 6137, 13384 Marseille cedex 13, France

Available online 31 May 2005

Abstract The electrical properties of Ge-based metal–oxide–semiconductor devices with GeOx(N)/HfO2 gate stacks are investigated. The current–voltage characteristics of the structures are consistent with the tunneling effect, with a transition from Fowler–Nordheim tunneling to direct tunneling as the HfO2 layer thickness is decreased. The capacitance–voltage characteristics of the MOS structures with HF-last Ge surfaces show large frequency-dispersions, indicative of a high density (1013 cm 2) of interface states. Much reduced frequency dispersion in the capacitance–voltage characteristics is observed on capacitors with NH3 annealed surfaces. In this case, however, a bump appears near the flat-band voltage of the devices, which we attribute to interface defects and/or border traps related to nitrogen.
2005 Elsevier B.V. All rights reserved.

1. Introduction As the scaling of classical metal–oxide–semiconductor (MOS) devices is approaching its limits, new materials are needed to continue improving device performances. One of these materials is Ge, which is currently under investigation as a replacement of Si [1–5]. The main advantages of Ge are its electron and hole mobilities, which makes this semiconductor particularly interesting for high frequency applications. Besides, high-j (j > 10) dielectrics such as HfO2 are studied for the replacement of SiO2 as gate dielectric in advanced MOS field effect transistors [6,7] to reduce the tunneling current flowing through ultra thin SiO2 layers [8]. The lower processing temperature of Ge-based MOS devices (500–600 C) compared to Si (900–1000 C) also makes this material particularly interesting with respect to the integration of high-j dielectrics and metal gates in advanced MOS devices. *

Corresponding author. Tel.: +32 16 281 404; fax: +32 16 281 315. E-mail address: [email protected] (M. Houssa).

0022-3093/$ - see front matter
2005 Elsevier B.V. All rights reserved. doi:10.1016/j.jnoncrysol.2005.04.035

In this work, we have investigated the electrical properties of Ge-based MOS structures with atomic-layer deposited HfO2 layers, for different layer thicknesses and two different surface preparation conditions, i.e. HF-last cleaned surfaces and NH3 annealed surfaces.

2. Experimental details The (1 0 0) n-type Ge wafers (10 X cm resistivity) were first cleaned in a HF/H2O solution, leaving a 0.4 nm GeOx layer at the interface, as estimated from the GeO peak measured by X-ray photoelectron spectroscopy. Some of the wafers were annealed in NH3 at different thermal budgets to produce a 0.6 nm GeON interfacial layer with different N content (see Table 1). HfO2 was next deposited by atomic layer deposition (ALD) [9] at 300 C, using HfCl4 and H2O as sources. A typical cross-sectional transmission electron microscope, TEM, image of a Ge/GeOx/HfO2 stack is shown in Fig. 1. Both the GeOx and HfO2 layer appear to be uniform, with smooth Ge/GeOx and GeOx/HfO2

M. Houssa et al. / Journal of Non-Crystalline Solids 351 (2005) 1902–1905 Table 1 Thickness and N content of the GeOx(N) interfacial layers, obtained from X-ray photoelectron spectroscopy measurements, for the HF-last cleaned Ge surfaces and the different NH3 pre-anneal thermal budgets N content (at.%)

HF/H2O HF/H2O HF/H2O HF/H2O HF/H2O

– 500 C, 600 C, 600 C, 700 C,

4.1 5.7 5.9 5.7 5.4

– 2.1 4.0 5.9 6.1

1 min 30 s 1 min 1 min

10

-1

10

-3

10

-5

10

-7

25 cy

2

GeOx(N) ˚) thickness (A

G

NH3 anneal

n-Ge/GeO/HfO2/Au

1

Direct tunneling J (A/cm )

Cleaning

10

1903

80 cy 40 cy 200 cy

Fowler-Nordheim tunneling 0

1

2

3 V (V)

4

5

6

G

Fig. 2. Gate current density JG–gate voltage VG characteristics of ˚ GeOx layer and HfO2 layers deposited using MOS capacitors with 4 A different ALD cycles (corresponding to different layer thicknesses).

-9

2.5×10

(a)

n-Ge/0.4 nm GeOx /4 nm Hf O2 /Au 10 kHz 2×10

50 kHz C (F)

Fig. 1. High resolution cross-sectional transmission electron micro˚ GeOx interfacial scope image of a Ge/GeOx/HfO2 stack with a 4 A layer and 10 nm HfO2 layer.

-9

-9

1.5×10

100 kHz -9

1×10

interfaces. The HfO2 layer is also partly crystallize, as detected by the TEM image. MOS capacitors were fabricated by evaporating gold dots (400 lm · 400 lm area) on the gate stack. The wafer backside was also Au-metallized to improve the electrical contacts. Current as a function of voltage (I–V) and capacitance as a function of voltage (C–V) were measured using a parameter analyzer [Keithley 4200] and an inductance–capacitance–resistance [LCR] meter [HP 4284], respectively.

The I–V properties of MOS capacitors with different HfO2 layer thicknesses (HF-last cleaned Ge surfaces) are presented in Fig. 2. The gate current JG increased with decrease of the HfO2 layer thickness (corresponding to a reduced number of ALD cycles), as expected for the tunneling effect. We also observe the transition from Fowler–Nordheim tunneling for the thicker stacks (80 and 200 cycles HfO2) to the direct tunneling regime for the thinner stacks (25 and 40 cycles). The C–V properties of a MOS structure with 4 nm HfO2 layer (HF-last cleaned Ge), measured at different frequencies, are presented in Fig. 3(a). A frequency– dispersion in the capacitance is observed, in accumulation, depletion and inversion, indicating the presence

-0.5

0

0.5

1

1.5 V (V)

2

3

2.5

3.5

G

C (F)

3. Results and discussion

-10

5×10

3×10

-9

2.5×10

-9

2×10

-9

1.5×10

-9

1×10

-9

(b)

0.6 nm GeON/3 nm HfO2 NH3 pre-anneal @ 600 °C

5 kHz 10 kHz 100 kHz

-10

5×10

0 -1

-0.5

0

0.5 V (V)

1

1.5

2

G

Fig. 3. Capacitance–voltage characteristics of MOS capacitors with ˚ GeON/3 nm HfO2 stacks ˚ GeOx/4 nm HfO2 stacks and (b) 6 A (a) 4 A measured at different frequencies.

of a density of interface defects 1013 cm2 [10], which is the result of a poor Ge/GeOx interface passivation.

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M. Houssa et al. / Journal of Non-Crystalline Solids 351 (2005) 1902–1905

As shown in Fig. 3(b), a better Ge surface passivation is achieved by annealing the substrate in NH3 prior to HfO2 deposition. In this case, the frequency dispersion in the C–V properties is much reduced, indicating a reduced interface state density. However, a bump in the capacitance also appears near the flat-band voltage, presumably related to the NH3 treatment, as discussed below. The C–V properties of MOS capacitors with NH3 annealed Ge surfaces at different thermal budgets and 3 nm HfO2 layers are shown in Fig. 4(a); increasing the NH3 thermal budget causes an increase of the N content in the GeON interfacial layer (see Table 1). The bump near the flat-band voltage increases with increasing NH3 thermal budget, and we suggest that this bump could be related to a N-induced interface (or border) trap. Besides, the flat-band voltage is less positive with increasing NH3 thermal budget, indicating an increase in fixed positive charge density [11]. It should also

3×10

-9

2.5×10

-9

0.6 nm GeON/3nm HfO2

2×10

(a)

NH : 500 °C, 1' 3 NH 3 : 600 °C, 1' NH : 600 °C, 30s 3 NH : 700 °C, 1'

-9

C (F)

3

1.5×10 1×10

-9

-9

-10

5×10

f=100 kHz

0 -1

-0.5

0

0.5

1

1.5

2

be pointed out that the Ge surface annealed at 700 C is much degraded, as shown by the C–V data of the corresponding devices. The I–V properties of the NH3 annealed stacks are shown in Fig. 4(b), for the different thermal budgets. The devices with Ge surfaces annealed at 500 and 600 C have similar current densities, consistent with the almost constant GeON interfacial layer thicknesses for the different thermal budgets (cf. Table 1). Consistent with the data shown in Fig. 4(a), the device with Ge surface annealed at 700 C also has much degraded I–V properties. Consequently, the NH3 annealing temperature should be kept below 700 C to avoid degradation of the Ge/GeON interface.

4. Conclusions The I–V properties of these devices present a transition from Fowler–Nordheim to direct tunneling regime as the HfO2 layer thickness is decreased, similar to SiO2-based devices. The C–V properties of capacitors with HF-last cleaned Ge surfaces have a large frequency dispersion in the entire gate voltage range, indicating a density of interface states 1013 cm2, resulting from poor Ge surface passivation. Much improved C–V properties are observed on devices with NH3-annealed Ge surfaces. However, a bump appears near the flatband voltage of NH3-annealed surfaces, which amplitude increases with the N content in the GeON interfacial layer. Defects responsible for the bump are thus most probably N-related centers. From the data on the effects of NH3 annealing, we conclude that this thermal treatment should be lower than about 700 C to avoid degradation of the Ge/GeON interface.

VG (V) 10

2

Acknowledgements

JG (A/cm2)

(b) 10

0

10

-2

10

-4

10

-6

This work is financially supported by the IMEC Industrial Affiliation Program on Ge-devices. Fruitful discussions with W. Tsai and P. Zimmerman (Intel) are gratefully acknowledged.

NH3 : 500 °C, 1' NH3 : 600 °C, 1' NH3 : 600 °C, 30s NH3 : 700 °C, 1'

References

10

-8

-1

-0.5

0

0.5

1

1.5

2

VG (V) Fig. 4. High frequency capacitance–voltage characteristic (a) and gate current density–gate voltage characteristics (b) of MOS capacitors with 3 nm HfO2 layers and GeON interfacial layers obtained under NH3 anneals of the Ge surfaces at different thermal budgets.

[1] C. On Chui, S. Ramanathan, B.B. Triplett, P. McIntyre, K.C. Saraswat, IEEE Electron Dev. Lett. 23 (2002) 473. [2] H. Shang, H. Okorn-Schmidt, J. Ott, P. Kozlowski, S. Steen, E.C. Jones, H.S. Wong, W. Hanesch, IEEE Electron Dev. Lett. 24 (2003) 242. [3] A. Ritenour, S. Yu, M.L. Lee, N. Lu, W. Bai, A. Pitera, E.A. Fitzgerald, D.L. Kwong, D.A. Antoniadis, IEDM Tech. Dig., IEEE, Piscataway, 2003, p. 433. [4] A. Rahman, A. Ghosh, M. Lundstrom, IEDM Tech. Dig., IEEE, Piscataway, 2003, p. 471.

M. Houssa et al. / Journal of Non-Crystalline Solids 351 (2005) 1902–1905 [5] T. Low, Y.T. Hou, M.F. Li, C. Zhu, A. Chin, G. Samudra, L. Chan, D.L. Kwong, IEDM Tech. Dig., IEEE, Piscataway, 2003, p. 691. [6] G.D. Wilk, R.M. Wallace, J.M. Anthony, J. Appl. Phys. 89 (2001) 5243. [7] For a recent review, see M. Houssa (Ed.), High-j Gate Dielectrics, Institute of Physics Publishing, London, 2004.

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[8] S.H. Lo, D.A. Buchanan, Y. Taur, W. Wang, IEEE Electron Dev. Lett. 18 (1997) 209. [9] M. Ritala, M. Leskela, Appl. Surf. Sci. 75 (1994) 333. [10] L.J. Huang, K. Rajesh, W.M. Lau, S. Ingrey, D. Landheer, J.P. Noe¨l, Z.H. Lu, J. Vac. Sci. Technol. A 13 (1995) 792. [11] E.H. Nicollian, J.R. Brews, MOS Physics and Technology, Wiley, New York, 1982.