HfO2-based gate stacks transport mechanisms and parameter extraction

Solid-State Electronics 54 (2010) 972–978

Contents lists available at ScienceDirect

Solid-State Electronics journal homepage: www.elsevier.com/locate/sse

HfO2-based gate stacks transport mechanisms and parameter extraction J. Coignus a,b,*, C. Leroux b, R. Clerc a, R. Truche b, G. Ghibaudo a, G. Reimbold b, F. Boulanger b a b

IMEP-LAHC, MINATEC, Grenoble INP, 3 Parvis Louis Néel, F-38016 Grenoble Cedex 1, France CEA-LETI MINATEC, 17 rue des Martyrs, F-38054 Grenoble Cedex 9, France

a r t i c l e

i n f o

Article history: Available online 23 May 2010 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Direct Tunneling current Temperature dependency of tunneling current Interfacial layer HfO2 SiOx

a b s t r a c t Transport mechanisms through SiO2/HfO2 gate stacks have been investigated by means of Capacitance– Voltage (C–V), Current–Voltage (I–V) in a large range of temperature (80–400 K) and Transmission Electron Microscopy (TEM) measurements, on several nMOS transistors featuring different interfacial layer and HfO2 thicknesses. The temperature dependency of experimental gate leakage currents have been found to be very weak when plotted versus total charge, except on thicker stacks, in inversion regime, between 300 and 400 K. Experiments have been compared with Direct Tunneling current (DT) simulations in inversion regime, using as few as possible arbitrary assumptions and fitting parameters. This comparison has shown that ultra-thin interfacial layer differs from pure SiO2 only below 1 nm thickness, confirming previous theoretical works. Ó 2010 Elsevier Ltd. All rights reserved.

1. Introduction In an attempt to reduce gate leakage in advanced CMOS devices, the replacement of conventional SiO2 and SiON gate dielectrics by high-j materials, and especially HfO2 and its silicates, has received a considerable attention in the last 15 years [1,2]. Indeed, already introduced in the 45 nm node INTEL technology [3], high-j materials are likely to become integrated in both High-Performance and Low-Power 32 nm node CMOS technologies and beyond. In this context, the understanding of gate leakage mechanisms through HfO2-based gate stacks appears as a critical issue to accurately predict the leakages and investigate the future high-j materials requirements for the node 22 nm and 16 nm [4]. Although this topic has already been addressed in several previous works [5–13], a consensus on the nature of transport has not been reached yet. Indeed, many studies have assumed or concluded that experimental leakage current were due to pure Direct Tunneling (DT) [2,4–6], and can be reproduced by effective mass DT simulations, similarly to what has been found for ultra-thin SiO2 dielectrics [14]. However, this conclusion still remains controversial. First of all, in these works, the extraction procedure of dimensions and parameters of both HfO2 and interfacial layers (conduction band offsets /, tunneling effective masses, thicknesses and permittivities) is usually missing or * Corresponding author at: IMEP-LAHC, MINATEC, Grenoble INP, 3 Parvis Louis Néel, F-38016 Grenoble Cedex 1, France. E-mail address: [email protected] (J. Coignus). 0038-1101/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2010.04.016

incomplete, making suspicious any conclusion on the nature of transport in such stacks. In addition, the applicability of effective mass DT theory to HfO2 gate stacks is also challenged by the following facts: (1) previous reported extraction of HfO2 tunnel parameters have shown a large dispersion (see Fig. 1), (2) advanced tight binding simulations have questioned the physical meaning of these extracted parameters and the validity of conventional DT model [8,9], (3) extremely thin interfacial SiO2 layer (below 8 Å) has been shown to differ from thicker SiO2, for both fundamental and process reasons [10,23]. Moreover, other works have also reported that pure DT model cannot fully explain temperature dependence of gate currents, suggesting the existence of some thermally assisted additional mechanisms [11–13]. This lack of understanding can be partially attributed to the lack of a complete set of experimental results, allowing to reduce as much as possible the number of arbitrary assumptions needed to compare experiments and simulation. This work is an attempt to address this issue. Capacitance–Voltage (C–V), Current–Voltage (I–V) and Transmission Electron Microscopy (TEM) measurements have been performed on several samples featuring different Interfacial Layers (IL) or HfO2 thicknesses. In addition, the dependency of gate current has been measured versus temperature (from low (80 K) to high temperature (400 K)) in order to discriminate transport mechanisms. Finally, experimental results have been carefully compared with DT simulations, discussing the most relevant methodology to reach a consensus on the extraction of HfO2 tunneling parameters.

973

0.014

3.0 [16] 2.5 [11] [21]

2.0 [22] 1.5 1.0

[16] [15] [17]

[6]

[19]

[18] [20]

0.5 0.0 0.0

0.012

-2

Gate Capacitance [F.m ]

Si-HfO2 Cond. Band Offset [eV]

J. Coignus et al. / Solid-State Electronics 54 (2010) 972–978

0.1

0.2

0.3

0.010 0.008 0.006

T= 80K 150K 300K 400K

0.004 0.002

Simulations Experiments

0.000 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5

0.4

Electron Tunneling Mass in HfO2 [units of m0 ]

Long channel nMOS (10  10 lm and 100  100 lm) transistors have been processed on (1 0 0) in situ p-doped substrates, featuring different gate stacks. First of all, reference samples have been realized with a standard n+ Polysilicon gate, deposited on top of an ultra-thin SiO2 grown by Rapid Thermal Oxidation (RTO). In addition, several SiO2/HfO2/TiN metal gate transistors have been processed featuring different thicknesses. A first set of devices features SiO2 interfacial layers of various thicknesses grown by RTO (from 1.2 to 2 nm) with a constant 3 nm HfO2 layer. A second set of samples has been realized with various HfO2 thicknesses (from 2 to 4.5 nm), keeping constant the interfacial layer thickness (8 Å, grown by chemical wet cleaning). In both cases, metal gate is TiN (10 nm thick, deposited by Chemical Vapor Deposition), and the HfO2 has been deposited by Atomic Layer Deposition (ALD) and annealed at low temperature (600 °C). Main sample characteristics are summarized in Table 1. Both capacitance versus voltage (C–V) measurements and gate current versus voltage (I–V) have been performed in all samples, at four different temperatures: 80, 150, 300 and 400 K. C–V measurement frequencies and gate area have been carefully selected in order to prevent any distortion due to either gate leakage current (dissipation factor D < 1) [24,25], too long channel length [25] or series resistance parasitic effects. The Equivalent Oxide Thickness (EOT) and Flat Band voltage (VFB) have been extracted from C–V measurements versus temperature, according to a procedure described in more details in [26]. It mainly consists in fitting experiments by self-consistent Poisson– Schrödinger (PS) simulations, accounting for wave function penetration. Examples of experimental and simulated C–V curves are

Table 1 Sample characteristics.

Fig. 2. Gate to substrate capacitance versus gate bias for a nominal 1.5 nm SiO2/ 3 nm HfO2/TiN gate stack (sample iv). Measurements and simulations have been performed at different temperatures. VFB = 0.466/0.429/0.311/0.239 V and EOT = 2.30/2.30/2.29/2.28 nm have been extracted at 80, 150, 300 and 400 K respectively.

0.016 iii -2

2. Experiments and methodology

Gate Bias [V]

Gate Capacitance [F.m ]

Fig. 1. HfO2 tunneling parameters dispersion in literature data. (See abovementioned references for further information.)

tSiO2 = 1.5nm tHfO2 = 3.0nm (device iv)

0.014

iv

0.012

v

0.010 0.008 0.006

tIL = 1.2 nm 1.5 nm 2.0 nm

0.004 0.002

Simulations Experiments

tHfO2 = 3nm T = 300K

0.000 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5

Gate Bias [V] Fig. 3. Gate to substrate capacitance versus gate bias for various SiO2/HfO2/TiN gate stacks, with different tIL (samples iii, iv and v). Measurements have been performed at room temperature and indicated thicknesses are nominal values.

shown in Figs. 2 and 3. As expected, the extracted values of EOT do not show any significant dependency versus temperature. Moreover, the experimental flat band voltage temperature dependency has been found in good agreement with modeling, accounting for substrate Fermi level variation versus temperature [27] (not shown here). Finally, Transmission Electron Microscopy observations have been performed on a selected set of samples.

3. Results and discussion 3

Samples

tIL (nm)

tHfO2 (nm)

Gate

Na (m

)

i ii iii iv v vi vii viii

1.5 2.5 1.2 1.5 2.0 0.8 0.8 0.8

– – 3.0 3.0 3.0 2.0 3.0 4.5

n + poly n + poly TiN TiN TiN TiN TiN TiN

1  1024 1  1024 2  1023 2  1023 2  1023 2  1023 2  1023 2  1023

IL process conditions

3.1. Qualitative conclusions

RTO RTO RTO RTO RTO Chem. ox. Chem. ox. Chem. ox.

While direct tunneling current varies with temperature mostly via the dependency of semiconductor charge versus temperature (essentially due to flat band and threshold voltage variations), temperature-assisted mechanisms may exhibit an additional temperature contribution. In order to discriminate these two effects (charge variation versus temperature from temperature-assisted mechanism), gate currents have been plotted versus total charge

10

4

10

3

10

2

10

1

10

0

10

-1

10

-2

10

80K 300K 400K

tSiO2 = 1.5nm 2.5nm

i

iii

-3

ii

Experiments -4

10 -0.02

-0.01

0.00

0.01

10

2

10

1

10

0

-2

Experiments

10

-1

10

-2

10

-3

80K 300K 400K

tIL.nominal = 1.2nm 1.5nm 2nm

iii iv v

tHfO2 = 3nm

-4

10 -0.02

-0.01

0.00

0.01

0.02

-2

Charge [C.m ] Fig. 6. Gate current density versus substrate total charge for samples featuring different interfacial layer (IL) thicknesses. (samples iii, iv and v, the indicated thicknesses are nominal values). Temperature activation in inversion regime remains almost constant for different IL thicknesses (constant HfO2 layer thickness).

-2

-2

Gate Current Density y [A.m [ ]

(extracted from C–V measurements), and not versus gate voltage as usual (Figs. 4–6). As expected, gate currents through SiO2–Polysilicon gate stacks (Fig. 4) do not show any significant temperature activation in a SiO2 thickness range of 1.5–2.5 nm, in both accumulation and inversion regimes. In this case, and as reported in several previous works [14,28], the absence of any significant thermally and defect assisted transport mechanisms can reasonably be attributed to the good quality and thermal stability of Si/SiO2 gate stacks realized by RTO process. Considering now high-j-based gate stacks, gate currents activation with temperature can be observed in specific conditions (see Figs. 5 and 6). While current in accumulation regime only shows a small variation versus temperature, current in inversion (negative charge) can exhibit a significant temperature enhancement, but only at high temperature (300 and 400 K). Temperature activation is important on thick HfO2 stack (typically 4.5 nm) and decreases with tHfO2, leading to almost no activation in the case of ultra-thin HfO2 layer (2 nm case). To quantify this temperature activation, the excess of current referred to the low temperature measurement (80 K) has been

Gate Current Densityy [A.m ]

J. Coignus et al. / Solid-State Electronics 54 (2010) 972–978

Jg - Jg @80K [A.m ]

974

10

5

10

4

10

3

10

2

10

1

10

0

10

-1

10

-2

10

-3

10

-4

tHfO2 = 2.0 nm tHfO2 = 4.5 nm

Qsub = -0.02 C.m

-2

Qsub = -0.016 C.m 2

3

4

-2

5

6

7

-1

1000 / T [K ]

-2

Charge [C.m ]

-2

Gate Current Density [A.m ]

Fig. 4. Gate current density versus substrate total charge for reference samples featuring different SiO2 thicknesses (samples i and ii, the indicated thicknesses are nominal values) and Polysilicon gate. (Samples with different oxide thicknesses also feature different surface area, explaining the different level of noise at low voltage.)

10

5

10

4

10

3

10

2

10

1

10

0

Experiments

300K

80K

vi

10

-1

10

-2

10

-3 -4

tHfO2 = 2.0nm

vii

-0.02

tHfO2 = 3.0nm

tHfO2 = 4.5nm

-0.01

0.00

0.01

0.02

plotted in Fig. 7 versus 1000/T, for different total charges. This excess of current qualitatively follows an Arrhenius law. Finally, the amplitude of temperature variation has been found to be relatively independent of the interface layer thickness (see Fig. 6). All these observations suggest the existence of an additional transport mechanism in HfO2, volume limited and thermally enhanced. These observations are in good agreement with results presented in [11], in which the thermal enhancement of gate current has been attributed to the role of traps located below HfO2 conduction band. 3.2. Comparison with direct tunneling simulation

viii

tIL.nominal = 0.8nm

10 -0.03

400K

Fig. 7. Arrhenius plot of excess gate current density, for different HfO2 thicknesses (samples vi and viii) and substrate charges. Additional temperature activation is clearly shown for thick HfO2 layer (4.5 nm) in a large temperature range.

0.03

-2

Charge [C.m ] Fig. 5. Gate current density versus substrate total charge for samples featuring different HfO2 thicknesses (samples vi, vii and viii, the indicated thicknesses are nominal values). Only thicker stacks in inversion regime (negative charge) show significant temperature dependency.

Experiments have been compared with Direct Tunneling simulations in inversion regime (electrons transport from Silicon conduction band). This model consists in first solving self-consistent Poisson and Schrodinger (PS) equations to compute the subband structure of the charge density. These results are then used to compute the tunnel current (see II), using a transparency-based model, described in more details in [7]. This approach accounts for all relevant subbands, wave function penetration and double abrupt barriers. In this model, the barrier between Si and SiO2 has been

975

J. Coignus et al. / Solid-State Electronics 54 (2010) 972–978 6

10

5

3.0

10

4

2.5

10

3

10

2

0.5

10

1

10

0

0.0 -3

10

-1

10

-2

10

-3

10

-4

10

-5

10

-6

Potential [eV]

-2

Gate Current Density [A.m ]

10

2.0 1.5 1.0

-2

-1 0 1 Position [nm]

2

3

A : realistic EOT= 1.41nm / ttot= 3.9nm B : realistic EOT= 1.55nm / ttot= 4.04nm C : abrupt EOT= 1.55nm / ttot= 3.9nm

0.0

0.5

1.0

1.5

2.0

2.5

Gate Voltage [V] Fig. 8. Gate current simulations versus gate voltage through three different gate stacks differing by their EOT and/or their total physical thickness (see Table 2 for simulated samples description).

Table 2 Simulated devices. Device A B C

ttransition (nm)

tpure SiO2 (nm)

tHfO2 (nm)

EOT (nm)

Total physical thickness (nm)

0.3 0.3 0

0.6 0.74 9

3 3 3

1.41 1.55 1.55

3.9 4.04 3.9

EOT and respective physical thicknesses have been calculated according to the following formula:

EOTrealistic ¼ tpureSiO þ eSiO2  tHfO þ eSiO2  lnðeSiO2 Þ  t transition 2 2 eHfO2 eSiO2 eSi eSi e EOTabrupt ¼ tSiO2 þ e SiO2  tHfO2 : HfO2

3.2.2. Experiments – DT model comparison methodology First of all, the reference samples SiO2 – Polysilicon gate stacks have been compared with the DT model in inversion layer, accounting for gate polydepletion. As seen in Fig. 9, a good agreement between model and experiments has been obtained, for all

-2

3.2.1. Validity of abrupt potential barrier approximation in gate current modeling When considering aggressively scaled gate stacks, previous works have highlighted the key-role of structural changes at the interface between Silicon and the SiO2-like interfacial layer. Based on ab initio simulations [10], the band profile, permittivity and tunneling masses transitions over a few angströms at Si–SiO2 interface have been found to have a critical impact on quantization and gate leakage current, especially when the Interfacial Layer (IL) thickness reaches sub-nanometer values. A specific PS solver has been developed to account for the continuous transition of potential energy, effective mass and permittivity, in a region of typical thickness 3–4 Å. In this ‘‘SiOx” region, and following the approach proposed by Markov et al. [10], material parameters (permittivity, carrier masses, band profiles) are linearly and spatially distributed from Silicon to SiO2 values, as shown for instance in the inset of Fig. 8. As previously reported, the realistic tunnel barrier profile model leads to an increase of both its capacitance and carriers transmission probability at constant physical thicknesses. In consequence, tunnel current in the non-abrupt model (curve A) is higher than

its counter part, curve C, in the abrupt model (see Fig. 8). Parameters of stacks A and C are reported in Table 2. However, when investigating gate leakage in advanced devices, it is more relevant to compare these two approaches at same EOT (see Fig. 8, curves B (realistic) and C (abrupt)). In this case, it turns out that abrupt and realistic models do not show any significant differences. Indeed, permittivity transition (which tends to decrease the EOT) and realistic band profiles have opposite impact on gate leakage current. As the non-abrupt approach does not significantly modify tunnel current when the comparison is performed at same EOT, and as it introduces one extra fitting parameter (the transition region thickness), in the following, simulations have been performed assuming an abrupt interface.

Gate Current Density [A.m ]

treated as abrupt: the validity of this approximation is investigated in section B1. This model is then applied to analyze gate tunnel leakage at low temperature, and extract tunnel parameters in the further section.

10

4

10

3

10

2

10

1

10

0

10

-1

10

-2

10

-3

10

-4

10

-5

0.0

T= 80K - 400K EOT = 1.78nm (device i)

T= 80K - 400K EOT = 2.62nm (device ii) Experiments DT model 0.5

1.0

1.5

2.0

Gate Bias [V] Fig. 9. Experimental and simulated gate current density plotted versus gate bias for samples i and ii (SiO2 – Polysilicon gate stacks) at low and high temperature (80 K and 400 K). (mSiO2 = 0.5m0, uSiO2 = 3.1 eV, eSiO2 = 3.9e0).

J. Coignus et al. / Solid-State Electronics 54 (2010) 972–978

temperatures, using the well established SiO2 tunnel parameters (mSiO2 = 0.5m0, uSiO2 = 3.1 eV, eSiO2 = 3.9e0.) and EOT (i.e. SiO2 physical thickness) extracted from C–V measurements. The confrontation between model and experiments is less straightforward in the case of HfO2 stacks, as the parameters (including the respective thicknesses) of both the interfacial layer and HfO2 are not accurately known. Permittivity values are of great importance, as they link the main gate stack observable parameter (i.e. EOT) and the DT model inputs, i.e. physical thicknesses of both dielectric layers, according to:

EOT ¼ eSiO2 



t IL

eIL

þ

tHfO2

 ð1Þ

eHfO2

In the next, a methodology to compare simulations and experiments is discussed, taking advantage of the two main sets of experiments, featuring different HfO2 thicknesses tHfO2 at same IL thickness, or different IL thicknesses tIL at constant HfO2 layer thickness. Additional assumptions have been done in order to reduce the number of fitting parameters: (1) only experiments at 80 K have been considered, in order to suppress the thermally assisted contribution in thicker stacks; (2) the tunnel parameters of HfO2 have been assumed identical in all samples, as the HfO2 layers have been deposited using the same process; (3) the HfO2 thickness tHfO2 has been assumed equal to its nominal values, as the ALD process allows a good control of the deposited HfO2 thickness (confirmed by Transmission Electron Microscopy observations (TEM), as shown for instance in Fig. 12).

4.50 4.25 4.00

ε SiO2 = 3.9 ε 0

3.75 3.50 3.25

EOT = 2.05nm tHfO2 = 3nm ε HfO2 = 17ε 0

3.00 2.75 1.0

1.1

1.2

1.3

1.4

1.5

IL Thickness [nm] Fig. 11. Extracted eIL as a function of IL thickness input value (device iii).

2.0 ε HfO2 = 17 ε 0

viii

R²=0.999

1.5 vi

tH

1.0

fO2 =3 n

O

n =3

2

0.5

0

1

2

3

m

Various tHfO2 (tIL.nominal = 0.8nm) Linear Fit

0.0

m

nm

nm =2 t IL

tIL = 1.37

vii

t Hf

Equivalent Oxide Thickness [nm]

Once knowing the EOT (extracted by C–V) and tHfO2, the dielectric constants of both layers are needed to deduce tIL. According to Eq. (1), the dielectric constant of HfO2 (eHfO2) has been found equal to 17e0 (see Fig. 10), from the slope of the EOT versus tHfO2 curve (correlation coefficient R2 = 0.999), using samples featuring different tHfO2. Thanks to the confidence on HfO2 thicknesses, this extracted value is considered as relatively reliable and will be used in the following. The application of such a method to extract eIL from devices showing tIL variants is more controversial. Once knowing EOT and high-j thickness and permittivity, it appears that extracted eIL is highly sensitive to IL thickness input, as shown in Fig. 11. This uncertainty on extracted permittivity is increased by the lack of

confidence on thin interfacial layers thickness values, even in samples where SiO2 was realized by accurate and well-controlled RTO process. Previous works [23,29] have indeed highlighted the impact of high-j deposition and post-annealing on IL regrowth. Applied to our data, as shown in our previous work [30], the extraction of eIL leads to the value of 4.7e0 when considering tIL = tRTO–SiO2,deposited. This value is not very likely, for several reasons. First of all, it significantly differs from the pure SiO2 value of 3.9 e0, which is quite surprising for interfacial layer thicknesses tIL thicker than 1 nm. Moreover, this eIL value is not in agreement with what can be deduced from TEM observations. Indeed, TEM images have been performed on devices iii and v, on which the expected value of tIL are 1.2 and 2 nm respectively. Fig. 12 clearly indicates an IL regrowth from 1.2 up to 1.35 nm in device iii, while device v does not show any IL thickness increase. The absence of significant regrowth on the thicker IL is reasonable, as in this last case, Si–SiO2 interface is quite far away from the oxygen source (located at SiO2–HfO2 interface). Finally, using the two new values of tIL measured by TEM, the extracted eIL has been found of 3.8 e0, a very close value of the ideal SiO2 permittivity 3.9 e0. Previous conclusions indicate that, with thicknesses in the range of 1.2–2 nm, the RTO interfacial layer behaves more like pure SiO2, suggesting that the same tunnel parameters extracted from reference Polysilicon – SiO2 experiments of Fig. 9

Extracted εIL [Units of ε0]

976

4

5

HfO2 Thickness [nm] Fig. 10. Equivalent Oxide Thickness (EOT) extracted from C–V measurements plotted versus HfO2 thickness. Dielectric constant has been extracted from the EOT versus tnominal slope.

Fig. 12. TEM observations performed on devices iii and v showing constant ALDdeposited tHfO2 = 3 nm and tIL = 1.37 and 2 nm respectively.

977

10

1

10

0

DT Model Experiments

-2

Gate Current Density [A.m ]

10

-1

10

-2

10

-3

10

-4

iii

iv

v

-2

(mSiO2 = 0.5m0, uSiO2 = 3.1 eV) should be used in order to simulate gate currents through devices iii, iv and v gate stacks. Once knowing IL parameters (i.e. permittivity, barrier height and electron tunneling mass), the HfO2 tunnel parameters have been extracted by fitting the experiments of Fig. 13, featuring different tIL at same tHfO2 (devices iii, iv and v), leading to mHfO2 = 0.165m0, uHfO2 = 1.9 eV. These values are in good agreement with previously reported data (see Fig. 1). Once knowing ALD-deposited HfO2 parameters, DT model has been then compared with I–V measurements performed on the second set of sample, i.e. devices vi, vii and viii, featuring tHfO2 variants (using same process conditions as before) and a constant DDC–SiO2 interfacial layer of expected thickness of 0.8 nm. As previously, the interfacial layer has been extracted from TEM images, leading to the value of tIL = 1 nm (see Fig. 14). In this second set of samples featuring chemical-SiO2 interfacial layer, the permittivity value has thus be found equal to eIL = 5 e0. Finally, as shown in Fig. 15, using the previously extracted permittivity value, the I–V experiments can be nicely reproduced without any additional fitting procedure, i.e. using the same tunneling parameters for the interfacial layer (mIL = 0.5m0, uIL = 3.1 eV) and for the HfO2 (mHfO2 = 0.165m0, uHfO2 = 1.9 eV). The higher permittivity value and very close to SiO2’s tunneling parameters suggest that the interfacial layer in this case is more similar to SiOx (sub-stochiometric compound of SiO2). These final results suggest that, provid-

Gate Current Density [A.m ]

J. Coignus et al. / Solid-State Electronics 54 (2010) 972–978

10

5

10

4

10

3

10

2

10

1

10

0

DT Model Experiments

vi vii

viii

10

-1

10

-2

10

-3

10

-4

T = 80K 0.5

1.0

1.5

2.0

Gate Bias [V] Fig. 15. Experimental and simulated gate current density plotted versus gate bias for samples vi, vii and viii (various HfO2 thicknesses with the same IL, grown by chemical cleaning) at low temperature (80 K). Simulations have been done using the following parameters: mIL = 0.5m0, uIL = 3.1 eV, eIL = 5e0, mHfO2 = 0.165m0, uHfO2 = 1.9 eV, eHfO2 = 17e0.

ing a correct extraction of the interfacial layer thickness (i.e. by TEM measurement), experimental I–V curves can be nicely reproduced by effective mass Direct Tunneling model, using a unique set of tunnel parameters. This conclusion underlines the critical role of parameter extraction (and especially interfacial layer thickness) when analyzing transport mechanism through HfO2-based gate stacks.

4. Conclusions

T = 80K 0.5

1.0

1.5

2.0

2.5

Gate Bias [V] Fig. 13. Experimental and simulated gate current density plotted versus gate bias for samples iii, iv and v (various RTO IL thicknesses with a constant 3 nm HfO2 layer) at low temperature (80 K). Simulations have been done using the following parameters: mIL = 0.5m0, uIL = 3.1 eV, eIL = 3.9e0, mHfO2 = 0.165m0, uHfO2 = 1.9 eV, eHfO2 = 17e0.

tIL=1nm

Fig. 14. TEM observation performed on device vii showing tIL,DDC = 1 nm.

C–V and I–V measurements have been performed from low to high temperatures, on several samples, observed by TEM, and featuring various interfacial layers (IL) or HfO2 thicknesses. Such data provide a unique complete set of experiments, needed to carefully investigate transport mechanism through HfO2 stacks. Plotting the gate current as a function of the total charge allows discriminating the charge dependency versus temperature from other thermally assisted transport mechanism. It turns out that: (1) currents are almost identical at 80 and 150 K in all experiments and (2) a significant thermal activation has been observed at 300 and 400 K only on stacks featuring a HfO2 thicknesses of 3 and 4.5 nm, and in inversion regime. Finally, low temperature inversion currents have been compared with Direct Tunneling simulation. Taking advantage of experiments performed on samples featuring both HfO2 and IL thicknesses variations, it has been possible to show that all experiments can be reproduced by simulation, using the same set of tunnel parameters for both HfO2 and interfacial layer. To this aim, it has been necessary to extract IL thickness by TEM measurement, to avoid any tIL thickness uncertainty, due to IL regrowth during high-j deposition and post-annealing. Based on an important set of tested devices and following an accurate extraction methodology, mHfO2 = 0.165m0 and uHfO2 = 1.9 eV has been extracted, reaching a better consensus on HfO2 tunneling parameters. In addition, the value of extracted barrier height is in good accordance with Internal Photo Emission spectroscopy (IPE) results [31,32]. Requiring a large set of experiments at low temperature, coupled with physical characterization, this work also illustrates the challenge to carefully extract HfO2 tunnel parameters. Such difficulty is certainly one of the factors explaining the surprising wide diversity of HfO2 parameters reported in the literature.

978

J. Coignus et al. / Solid-State Electronics 54 (2010) 972–978

References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]

Iwai H et al. In: IEDM tech digest; 2002. p. 625. Toriumi et al. In: IEDM tech digest; 2007. p. 54. Auth C et al. In: Proc VLSI symposium; 2007. p. 128. Yeo YC, King TJ, Hu C. IEEE Trans Dev 2003;50:1027. Govoreanu B et al. Solid-State Electron 2004;48:617. Li F et al. IEEE Tran Elecron Dev 2006;53:1096. Coignus J et al. J Vac Sci Technol B 2009;27:338. Stadele M, Tuttle BR, Hess K. J Appl Phys 2001;89:348. Sacconi F et al. IEEE Trans Electron Dev 2007;54:3168. Markov S et al. Phys Status Solidi A 2008;205:1290. Campera A et al. IEEE Trans Electron Dev 2007;54:83. Mitrovic IZ et al. Micro Eng 2007;84:2306. Xu Z et al. Appl Phys Lett 2002;80:1975. Lo SH et al. IEEE Electron Dev Lett 1997;18:209. Palestri P et al. IEEE Trans Electron Dev 2007;54:106.

[16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32]

Kar S et al. IEEE Trans Electron Dev 2005;52:1187. Buckley J et al. In: Proc ESSDERC; 2005. Zhu WJ et al. IEEE Electron Dev Lett 2002;23:97. Govoreanu B et al. Solid-State Electron 2003;47:1045. Wu H, Zhao Y, White MH. Solid-State Electron 2006;50:1164. Hou YT et al. IEEE Electron Dev Lett 2003;24:96. Garros X, PhD thesis; 2004. Damlencourt J-F et al. Solid-State Electron 2003;47:1613. Clerc R et al. Micro Reliability 2001;41:1027. Ahmed KZ et al. IEEE Trans Electron Dev 1999;46:1650. Leroux C et al. Micro Eng 2007;84:2408. Green MA. J Appl Phys 1989;67:2944. Cai J, Sah CT. J Appl Phys 2001;89:2272. Cosnier V et al. Micro Eng 2007;84:1886. Coignus J et al. In: Proc ESSDERC; 2009. Charbonnier M et al. Micro Eng 2009;86:1740. Widiez J et al. Jpn J Appl Phys 2008;47:2410.