Microelectronic Engineering 109 (2013) 28–30
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Impact of metal gate electrodes on electrical properties of InGaAs MOS gate stacks C.-Y. Chang a,⇑, M. Yokoyama a, S.-H. Kim a, O. Ichikawa b, T. Osada b, M. Hata b, M. Takenaka a, S. Takagi a a b
Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan Sumitomo Chemical Corporation Ltd., Kitahara, Tsukuba, Ibaraki 300-3294, Japan
a r t i c l e
i n f o
Article history: Available online 26 March 2013 Keywords: InGaAs Metal gate electrodes High-k dielectrics Interface state density
a b s t r a c t Electrical properties of Al2O3 and HfO2/InGaAs metal–oxide–semiconductor (MOS) capacitors with Al, Au and Pd gate electrodes have been evaluated in order to study the impact of metal gate electrodes on gate dielectrics and interface properties. It is found that MOS capacitors with Pd gate electrode can provide thinnest capacitance-equivalent-thickness (CET) and better HfO2/InGaAs MOS interfaces than those with Al and Au. However, the Al2O3/InGaAs interface properties are better in Au and Al gate electrodes than in Pd. Thus, the combination of high-k and gate metals must be carefully examined for realizing optimum gate stacks. Ó 2013 Elsevier B.V. All rights reserved.
1. Introduction InGaAs has been regarded as one of promising n-channel materials to replace Si because of its low electron effective mass and thus high electron mobility [1]. Here, the development of high quality MOS gate stacks is of paramount importance in order to realize high-performance InGaAs MOSFETs. Many efforts have been devoted so far to gate insulator formation technologies on InGaAs and their interface properties [2]. However, impacts of metal gate electrodes on gate dielectrics and interface properties have not been fully studied yet in spite of the strong impact on the electrical properties, as often seen in high-k/Si gate stacks. In this study, gate electrode materials have been varied for Al2O3 and HfO2/InGaAs MOS capacitors among Au, Al and Pd formed by thermal evaporation, and the impacts of metal gate electrode on gate dielectrics and interface properties have been examined. Here, metal materials allowing us to deposit by thermal evaporation and the shadow mask process have been chosen in order to avoid any damages induced by plasma or electron beam processes. While Pd gate has recently been applied to self-aligned In0.53Ga0.47As MOSFETs [3], InGaAs MOS interface properties with Pd gate has not been fully studied yet in comparison with other gate metals.
2. Experiments A Si-doped n-In0.53Ga0.47As layer with doping concentration of ND 5 1015 cm 3 was epitaxially grown on a (1 0 0) InP substrate. After the wafers were cleaned in acetone, NH4OH and ⇑ Corresponding author. Tel.: +81 3 5841 6733; fax: +81 5841 8564. E-mail address:
[email protected] (C.-Y. Chang). 0167-9317/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2013.03.086
(NH4)2S solutions, Al2O3 or HfO2 was deposited at 200 oC by ALD using Al(CH2)3 and Hf[N(C2H5)CH3]4 as the precursors, respectively. Subsequently, Au, Al or Pd was deposited as the gate electrodes through shadow masks by thermal evaporation, and Al back contact was deposited on all the samples. Finally, post-metallization annealing (PMA) was performed in N2 for 30 min at 400 oC for Au and Pd on Al2O3 and HfO2, at 300 oC for Al on Al2O3, and at 200 oC for Al on HfO2. The PMA conditions have been optimized. The MOS capacitors structure and process flow were shown in Fig. 1.
3. Results and discussion Fig. 2(a) and (b) shows CET as a function of Al2O3 and HfO2 thickness, respectively. CET is determined by maximum capacitance values (Cmax) in C–V curves of as-deposited MOS capacitors. It is observed for both Al2O3 and HfO2 that the MOS capacitors with Pd provide the thinnest CET and the highest equivalent dielectric constant (k) value among the three metals, suggesting the superiority of Pd gate in terms of thinning CET. One possible reason for this thinnest CET with Pd may be any hydrogen catalytic effect of Pd, which can enhance any reaction or absorption of hydrogen with Al2O3 or HfO2 leading to the modification of these dielectric films and/or the interfacial layers [4–6]. On the other hand, the thickest CET of the Al2O3 and HfO2 MOS capacitors with Al gates is attributable to the reaction between Al and the gate dielectrics, which can cause the increase in the thickness of the gate dielectrics. As for the Al2O3 and HfO2 MOS capacitors with Au gates, there seems no reaction between Au and the gate dielectrics and, therefore, the CET value of the Au gate is medium. The C–V curves of the Al2O3 and HfO2/InGaAs MOS capacitors with Au, Al and Pd gate after PMA are shown in Fig. 3(a)–(f). In
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Fig. 1. MOS capacitor structures and process flow.
2
Al Au Pd
Pd k~9.3
1 0
HfO2 on InGaAs 7 As-deposited 6 Al Au 5 Pd 4 Al k~17.9 3 Au k~17.0 2 1
Pd k~23.7
0
0 2 4 6 8 10 0 2 4 6 8 10 (a) Thickness (nm) (b) Thickness (nm) Fig. 2. CET as a function of (a) Al2O3 thickness and (b) HfO2 thickness showing dependence of gate electrode metals (Au, Al, Pd) on Cmax and dielectric constant (k).
addition to CET and Cmax, it is also found that flat-band voltage shift (DVFB) and hysteresis differ among the three gate metals. These re-
0.8
Au/Al2O3/InGaAs 0.7 Al2O3 = 9.0 nm 0.6 PMA 400 oC 0.5
2
1 kHz 10 kHz 100 kHz 1 MHz
0.2
0.1 0 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 V (V) (a) g
0.4 1 kHz 10 kHz 100 kHz 1 MHz
0.3 0.2 0.1
0 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 V (V) (b) g
1.4
Au/HfO2/InGaAs 1.2 HfO2 = 8.7 nm o 1 PMA 400 C
Al/HfO2/InGaAs 1.2 HfO2 = 8.7 nm o 1 PMA 200 C
0.8 0.6
1 kHz 10 kHz 100 kHz 1 MHz
0.4 0.2
(d)
0 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 V (V) g
o
0.4 0.2
(e)
0.3 0.2
1 kHz 10 kHz 100 kHz 1 MHz
g
1.4
0.8 0.6
Pd/Al2O3/InGaAs 0.7 Al2O3 = 9.0 nm 0.6 PMA 400 oC 0.5 0.4
0.1 0 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 V (V) (c)
2
1.4
2
2
C' ( F/cm )
C' ( F/cm )
0.4 0.3
0.8
Al/Al2O3/InGaAs Al2O3 = 9.0 nm 0.6 PMA 300 oC 0.5 0.7
C' ( F/cm )
2
C' ( F/cm )
0.8
2
3
CET (nm)
CET (nm)
4
sults prove that gate electrode metals do have an impact on the electrical properties of MOS capacitors. Figs. 4 and 5 summarize the gate electrode metal dependence of DVFB and hysteresis, respectively. The larger hysteresis in the Al and Pd gate C–V curves shown in Fig. 5 indicates a large amount of slow traps generated during the reaction between the gate dielectrics and the Al or Pd gate metals. The C–V curve of Al/HfO2/InGaAs shown in Fig. 3(e) was severely degraded, indicating the generation of large amount of Dit. This is attributable to the diffusion of Al into HfO2 after PMA [7,8], which is also responsible for the decrease of Cmax. Dit was estimated by the conductance method using the surface potential fluctuation model [9]. The result is shown in Fig. 6. The interface quality of Al2O3/InGaAs has been confirmed to be better than HfO2/InGaAs [10,11]. Here, Dit of the HfO2 MOS capacitors with Al shown in Fig. 6 was evaluated by the Terman method [12] instead of the conductance method, because surface potential
8
C' ( F/cm )
Al2O3 on InGaAs As-deposited 6 Al k~6.6 5 Au k~8.2 7
C' ( F/cm )
8
1 kHz 10 kHz 100 kHz 1 MHz
0 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 Vg (V)
Pd/HfO2/InGaAs 1.2 HfO2 = 8.7 nm o 1 PMA 400 C 0.8 0.6
1 kHz 10 kHz 100 kHz 1 MHz
0.4 0.2
(f)
0 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 V (V) g
Fig. 3. C–V curves of 9.0 nm Al2O3/InGaAs by ALD at 200 C after PMA using (a) Au, (b) Al and (c) Pd as gate electrodes, and C–V curves of 8.7 nm HfO2/InGaAs by ALD at 200 oC after PMA using (d) Au, (e) Al and (f) Pd as gate electrodes.
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C.-Y. Chang et al. / Microelectronic Engineering 109 (2013) 28–30
1.2
HfO2 Al2O3
V FB (V)
1 0.8 0.6 0.4 0.2
out and large DVFB and hysteresis in Fig. 3(e) suggest that Dit of Al on HfO2 is much larger than the other samples, which is also confirmed by Dit of the HfO2 MOS capacitors with Al estimated by the Terman method shown in Fig. 6. It is found here that Dit of the HfO2 MOS capacitors with Pd is better than those with Au and Al, while the result is opposite for the Al2O3 MOS capacitors. These findings mean that InGaAs MOS interface properties are strongly affected by gate metal materials as well as gate insulators and that the choice of appropriate metal gate materials is also dependent on high-k materials. Attentions must be paid to any reaction of high-k films with gate metals or hydrogen for understanding these phenomena. 4. Conclusion
0
Al
Pd
Au
Fig. 4. The dependence of gate electrode metals (Au, Al and Pd) on DVFB for Al2O3 and HfO2 capacitors.
Hysteresis at V FB (V)
0.6
HfO2 Al2O3
0.5 0.4
We have found in InGaAs MOS capacitors that gate electrode metals have a strong impact not only on the gate dielectrics but also on the interface properties. While the Al2O3/InGaAs interface properties is better in Au and Al gate electrodes than in Pd ones, the Pd gate electrode provides lower CET and comparatively better MOS interface properties in HfO2/InGaAs than Au and Al. Judging from the thermal instability of the Al gate electrodes and the incompatibility of Au with the Si processing, Pd can be regarded as a promising metal gate material for thinning CET. On the other hand, it is necessary to further understand and control any reactions of Pd with the gate dielectrics and possible contributions of hydrogen.
0.3 Acknowledgements
0.2
This work was supported by Development Program for Innovative Energy Efficiency Technology from NEDO.
0.1 References
0
Al
Pd
Au
Fig. 5. The dependence of gate electrode metals (Au, Al and Pd) on hysteresis at VFB for Al2O3 and HfO2 capacitors.
14
10
-2
-1
Dit (cm eV )
Al on HfO2 by Terman
13
10
Au on HfO2 Pd on HfO2
Pd on Al2O3 Al on Al2O3 Au on Al2O3 0 0.05 0.1 0.15 0.2 Energy from midgap (eV)
12
10
Fig. 6. Dit evaluated by conductance method for MOS capacitors with Au, Al and Pd gate electrodes on Al2O3 and HfO2. Dit of Pd on HfO2 is lower than that of Au on HfO2, while the result is opposite for Al2O3 case.
may be pinned near the conduction band edge due to large Dit and, thus, the interface state response speed is too high to be detected by the conductance method [13,14]. However, the severe stretch-
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