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Electromagnetic optimization of an RF-MEMS wafer-level package
Available online at www.sciencedirect.com
Sensors and Actuators A 142 (2008) 434–441
Electromagnetic optimization of an RF-MEMS wafer-level package J. Iannacci a,b,∗ , M. Bartek b , J. Tian b , R. Gaddi a , A. Gnudi a a
b
ARCES-DEIS Universit`a di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy HiTeC-DIMES, Delft University of Technology, Mekelweg 4, 2628 CD Delft, The Netherlands Received 5 October 2006; received in revised form 7 August 2007; accepted 7 August 2007 Available online 19 August 2007
Abstract In this work, we present electromagnetic optimization of a wafer-level package (WLP) intended for RF-MEMS applications. The packaging solution presented is based on a high-resistivity silicon capping substrate containing recesses and copper-filled thru-hole vias. This pre-fabricated capping substrate is first wafer-level bonded to the RF-MEMS device wafer, then populated by solder spheres and finally singulated into individual packages. For the package electrical optimization, Ansoft HFSSTM electromagnetic simulator has been used in order to assess the RF-behaviour of packaged MEMS devices, including losses and mismatch due to inductive and capacitive couplings introduced by the cap. A fully parameterized model of a 50 coplanar waveguide (CPW) including all the degrees of freedom (DoFs) made available by the technological process is presented and extensively exploited for the electromagnetic optimization of the capping structure. Moreover, the measurement data obtained from the fabricated capped and uncapped test structures (50 Q CPWs and shorts) and their comparison with simulations are presented. © 2007 Elsevier B.V. All rights reserved. Keywords: Wafer-level package (WLP); RF-MEMS; Electromagnetic optimization; Ansoft HFSSTM
1. Introduction In the development of packaging techniques for RF-MEMS devices several key factors are involved. First of all, a suitable protection of the RF-MEMS devices from potentially harmful factors like mechanical shocks, moisture, dust particles, etc. is required. Moreover, the packaging should also facilitate cointegration of CMOS control circuitry (hybrid packaging) [1]. When dealing with radio frequency (RF) applications, further important issues tend to emerge. Indeed, the parasitic effects (i.e. capacitive and inductive couplings) introduced by the application of a capping substrate to the RF-MEMS devices can deteriorate rather considerably the RF performance [2]. In the worst case, this deviation can be so large that some device specifications fall outside the requirements of a certain application. In this scenario, the availability of a suitable methodology for
∗
Corresponding author at: ARCES-DEIS Universit`a di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy. Tel.: +39 051 20 93049; fax: +39 051 20 93779. E-mail addresses: [email protected], [email protected] (J. Iannacci). 0924-4247/$ – see front matter © 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.sna.2007.08.018
the prediction of the package influence on the RF-behaviour of MEMS devices is important. In this work we present a fully parametrized model of a capped coplanar waveguide (CPW) for the simulation in Ansoft HFSSTM . To this purpose, the Ansoft HFSSTM 3D electromagnetic simulator is first validated as an accurate tool in predicting the RF-behaviour of MEMS structures by comparing its results against experimental data of fabricated devices. During optimization, all the technology degrees of freedom (DoFs) allowed by the fabrication process have been parameterized within the model. Consequently, it is possible to launch an automated optimization of all these DoFs in order to reduce as much as possible the package-induced RF parasitics. 2. Technological details The packaging process, that is provided by the DIMES Technology Centre (Delft University of Technology, The Netherlands), is based on a high-resistivity silicon (HRS) substrate. The Bosch DRIE (deep reactive ion etching) process is exploited to etch recesses on the back side of the capping substrate in order to accommodate the MEMS devices. Afterwards,
J. Iannacci et al. / Sensors and Actuators A 142 (2008) 434–441
Fig. 1. Schematic view of the capping substrate showing both through vias and the etched recess.
vertical through-wafer vias are etched from the front side and the wafer is then grinded in order to reduce its thickness (Fig. 1). Subsequently, a seed-layer is sputtered on the top side and on the vias sidewalls in order to allow copper electrodeposition of pads on the substrate front side as well as via filling (from the back side). A cross-section of a vertical via aligned with the signal pad on the device wafer is shown in Fig. 2, while a SEM photograph of a vertical interconnect filled with copper after sample cutting is reported in Fig. 3. The final wafer-to-wafer or chipto-wafer bonding is performed by solder reflow or by means of ICA/ACA (isotropic/anisotropic conductive adhesive) [3,4]. In the first case AuSn bumps have to be electroplated on the substrate back side. The solution based on solder reflow allows maintaining hermeticity of the package. Nevertheless, it requires a higher thermal budget (about 300 ◦ C) compared to the solution that employs ICA/ACA (120–150 ◦ C). Most of the recently reported RF-MEMS technologies have recommended reliability thermal requirements falling below 180 ◦ C.
Fig. 2. Schematic cross-section of a vertical via that provides electrical contact and signal redistribution from the MEMS signal pad on the device wafer.
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Fig. 3. SEM photograph of a vertical via filled with copper after sample cutting.
3. Experimental results with non-optimized package Preliminary experimental data are available after the first bonding of a package chip onto a wafer containing test structures, i.e. 50 coplanar waveguides (CPWs) and shorts. The bonding solution in this case is based on the use of ICA (CE 3103 WLV made by Emerson & Cuming). In the experiment no bumps have been deposited on the capping substrate. A photograph of a gold evaporated CPW is reported in Fig. 4, while the top side of the package applied to it (and to other devices) is shown in Fig. 5 where copper pads for GSG (ground-signal-ground) probing are visible. Chip-to-wafer alignment was performed manually and ICA residues (i.e. dark stains in Fig. 4) after package de-bonding show that the vertical vias were correctly placed onto CPW lines. The comparison of the experimental S-parameters for a CPW with and without capping is shown in Fig. 6 (reflection parameter) and Fig. 7 (transmission parameter). The 50 CPW is 1350 m long. The signal line width is 116 m while the ground lines width is 300 m and the gap is 65 m. Via diameter is 50 m.
Fig. 4. Photograph of a gold evaporated matched coplanar waveguide (CPW). ICA residues after de-bonding (dark stains) prove that a good package-to-wafer alignment was reached.
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Fig. 5. Photograph of the package top side. Copper pads for GSG probe measurements are visible. These are connected to the capped test structure by means of vertical vias (see Fig. 3). Fig. 8. Smith chart of the reflection parameter for a capped and an uncapped short.
Losses and mismatch introduced by placing the capping part do not seem to be very large. For instance, the S11 parameter for the uncapped line is −26.8 dB at 17 GHz while it changes to −16.4 dB at 17 GHz for the line with package. The change of
the transmission parameter S21 is acceptable too, showing an increasing loss with frequency. The difference between the S21 parameter for the uncapped and capped CPW is within −0.24 dB up to about 20 GHz, whereas it is −0.4 dB at 30 GHz. The other type of test structure on the device wafer is a variety of shorts for 1-port measurements. The S11 parameter of a capped and uncapped short is shown in the Smith Chart of Fig. 8. The two curves for the capped and uncapped short are very close together. This means that the losses introduced by the package (top pad plus vias plus ICA joints) are quite small. The extra phase rotation of the capped short (curve labeled as “Capped short (S11)” in Fig. 8) is due to the increased electrical length through which the signal flows before reaching the actual packaged device. A better indication of the losses introduced by the packaging comes from the magnitude plot of the S11 parameter for the same short presented above (Fig. 9). The difference between the S11 parameter for the uncapped and capped short is within −0.25 dB up to about 13 GHz. In the higher frequency range (beyond 15 GHz) in spite of the spikes
Fig. 7. Transmission parameter for a CPW with and without silicon cap.
Fig. 9. Comparison of the reflection parameter for the short with and without cap.
Fig. 6. Reflection parameter for a CPW with and without silicon cap.
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Fig. 10. Comparison between experimental data and HFSSTM simulation results of a capped CPW (S11).
the two curves are still close together. The experimental comparisons shown in this section must be considered encouraging, especially since the design of the presented package does not take into account the results of the electromagnetic optimization (shown at the end of this paper) that was performed at a later time. Hence, the perspective is of achieving lower losses in the next design cycle of packaging structures. 4. Simulations versus experimental data In this section the comparison of the experimental data with simulations of the same structures in HFSSTM will be shown. The S-parameter plots for a CPW compared with the HFSSTM prediction are shown in Figs. 10 and 11. The 50 CPW is 2500 m long. The signal line width is 116 m while the ground lines width is 300 m and the gap is 60 m. By observing the reflection parameter plot of Fig. 10 it is noticeable a rather large offset between the measured and simulated curves. For instance, the difference between the experimental and simulated S11 ranges from −15 dB at 5 GHz to −12 dB at 18 GHz. However, it is also important to highlight that the HFSSTM predicted very well the qualitative behaviour of S11 over the whole fre-
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Fig. 12. Comparison between measured and simulated reflection parameter of a capped short.
quency range. In particular, the notch of the reflection parameter fits very sharply with the one that was measured at about 22 GHz. Concerning the transmission parameter (Fig. 11) in the lowfrequency range the largest difference is around 3 GHz where the simulated S21 parameter is about 0.4 dB higher than the measured one. Moreover, the transmission parameter value predicted by the HFSSTM is roughly 0.6 dB higher than the experimental one at 22 GHz and the difference raises to 0.85 dB at 30 GHz. Finally, the comparison of the measurements with the HFSSTM results for the short of the previous section is shown in Fig. 12. Besides, additional issues have to be taken into account in the interpretation of these results. Indeed, as mentioned before, a few process DoFs were not well-controlled in this first sample of packaged test structures. For instance, the height of the ICA and consequently the air gap between the two wafers is supposed to be around 10 m but the exact value is not known. Again, the thickness of the evaporated gold structures is expected to be several hundred nanometers (400–500 nm). However, because of the roughness of the wafer back side on which they have been processed, the actual thickness is not precisely known either [5]. After these considerations it is possible to conclude that the HFSSTM has shown to produce results which are in reasonable agreement with the experimental ones. 5. Validation of Ansoft HFSSTM simulator
Fig. 11. Comparison between experimental data and HFSSTM simulation results of a capped CPW (S21).
The Ansoft HFSSTM electromagnetic simulator needed to be validated in order to understand whether it represents a suitable tool to accurately predict the S-parameters of MEMS structures. Hence, the experimental data of a few devices fabricated in FBK-irst (Bruno Kessler Foundation) RF-MEMS technology (Trento, Italy) [6] have been compared with the corresponding HFSSTM simulations. An example is the suspended spiral inductor whose schematic view is shown in Fig. 13. The comparison of the S-parameters obtained from measurements and from HFSSTM simulations are shown in the plots depicted in Fig. 14. These show a very good agreement between experimental and simulated data. Indeed, the reflection parameter (S11) curves overlap in the whole frequency range. Concerning the transmission parameter (S21), its measurement is equal to −11.3 dB at
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Fig. 13. HFSSTM model of a suspended inductor fabricated in FBK-irst RFMEMS technology.
6 GHz while the HFSSTM predicts a value of −10.4 dB at 6 GHz (corresponding to a difference of about 8%). This proves that the Ansoft HFSSTM electromagnetic simulator is a suitable tool for the prediction of RF-behaviour of MEMS devices.
Fig. 15. HFSSTM model of a capped CPW. The capping substrate including the etched recess is not shown to get a plain view of the underneath device and of the through-wafer interconnects.
Fig. 15. In order to explain the approach, the top-right via in Fig. 15 is taken as an example. The coordinates (x, y, z) of the top-right via centre are parametrically written as (assuming the system origin at the left-lower corner of Fig. 16, left) x = 21 xbox + 21 xline − Xoffset
(1a)
6. Parameterized model of a capped transmission line
y = 21 ybox + Yoffset
(1b)
When dealing with several technological DoFs their parameterization allows fully automated optimization. In this work, we focus on the parasitics reduction of the package applied to CPWs instead of actual RF-MEMS devices. This choice is mainly due to the influence of the capping substrate being more easily interpreted when applied to structures with a very simple frequency response. Indeed, in this preliminary stage of development of the capping substrate process it would not be useful to focus directly on its influence on the RF performance of specific MEMS devices without knowing the general effect of each DoF variation. There is also a practical reason. In the package process optimization several trials at wafer-level are necessary. Consequently, it is preferable to use simplified test structures without the need of sacrificing actual RF-MEMS device wafers. In the HFSSTM parametrized model, suitable independent variables have been defined in order to describe all the technological DoFs (e.g. via diameter, capping substrate thickness, recess depth and so on). The HFSSTM schematic of a capped CPW is shown in
z = zSi + zOx + zline + Zbump
(1c)
where xbox , ybox , Xoffset , Yoffset and xline are defined in Fig. 16, left, and zSi , zOx , zline , Zbump in Fig. 16, right. In the previous formulas Xoffset , Yoffset and Zbump represent DoFs related to the capping part subject to optimization. The other parameters are necessary for defining of the structure geometry, but are not directly involved in the optimization of the package. 7. Electromagnetic optimization of the package The Ansoft HFSSTM simulator has been exploited in determining the influence of each DoF on the losses associated with the package [7] of a capped CPW, used as test structure. The CPW is 2000 m long, the signal line and ground lines width are 150 m and 900 m, respectively, while the gap is 30 m. The capping part height is 350 m and the frequency of the analysis was set to 15 GHz. The influence of one technological
Fig. 14. Comparison between experimental and simulated S-parameters of the suspended inductor shown in Fig. 13.
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Fig. 16. Parameterization of the center coordinates of the top-right via of Fig. 15. Left: in-plane coordinates; right: vertical coordinates.
and one geometrical DoF on the S-parameters is discussed here. The technological DoF is the resistivity of the silicon capping substrate. Wafers with various resistivities were on stock. It was possible to chose among a low-resistivity silicon (LRS) wafer (with resistivity of about 15 cm) and four high-resistivity silicon (HRS) wafers (with resistivity of 1 k cm, 2 k cm, 3 k cm and 4 k cm [8,9]). The geometrical DoF is via diameter that has been varied within the 10–100 m range. The 3D plot of Fig. 17 shows that low values of the reflection parameter S11 are achieved for low values of the via diameter with the LRS substrate, and also for large values of the via diameter (over 60 m) with the HRS substrates. For instance, S11 = −16.1 dB and S11 = −13.6 dB for via diameter values of 10 m and 40 m, respectively, with the LRS substrate, while, for the 2 k cm substrate, S11 ranges between −13.4 dB and −16.5 dB for via diameters between 60 m and 100 m. However, S21 must also be considered to monitor
the losses. From the 3D plot of Fig. 18 we verify that the poorest values of S21 are obtained for narrow vias etched in a LRS substrate. In particular, the 15 cm substrate must be avoided since, when used, S21 ≤ −8.10 dB. This can be explained with the presence of losses in the substrate due to eddy currents surrounding the vias. On the contrary, high values of the transmission parameter are achieved for HRS substrate in combination with large vias (above 60 m). For instance, S21 falls into the [−1.00,−0.64] dB interval for via diameters ranging between 50 m and 100 m, when a 2 k cm silicon substrate is employed. In conclusion, optimization of both reflection and transmission parameters shows that the best choice is represented by vias with a diameter of at least 60 m. Concerning the type of substrate, while the use of a LRS one is not an option, the choice of the proper HRS substrate brings up a possible trade-off between performance and the costs. In this respect, since the benefits achieved in terms of S-parameters with very
Fig. 17. Reflection parameter of the capped CPW as a function of the via diameter and of the capping silicon substrate resistivity at 15 GHz.
Fig. 18. Transmission parameter of the capped CPW as a function of the via diameter and of the capping silicon substrate resistivity at 15 GHz.
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Table 1 Effect on losses and mismatch of the variations of the most significant DoFs related with the package fabrication calculated with Ansoft HFSSTM simulations Capping silicon substrate resistivity Capping silicon substrate height Recess depth Via diameter GSG vias lateral distance Bumps height
+ − + + + +
The signs “+” and “−” indicate if the corresponding DoF has to be, respectively, increased or decreased in order to reduce losses and mismatch.
HRS substrates (3–4 k cm) are not that large with respect to the 1 k cm and 2 k cm silicon wafers, the best choice would probably fall on one of the latter two, the use of the 2 k cm being probably the most reasonable one. A similar analysis can be carried out for the other optimization parameters. In Table 1 the qualitative effects of the most significant technological DoFs on the losses and mismatch introduced by the capping part are reported. These results have been obtained with the parametric model of a capped CPW discussed in the previous section. 8. Conclusions In this work we have presented a new approach to the fabrication and electromagnetic optimization of a wafer-level package for RF-MEMS devices. The proposed approach is based on a capping high-resistivity silicon substrate that is wafer-level bonded to the RF-MEMS device wafer. The capping substrate contains electroplated through-wafer copper vias for signal redistribution and recesses for accommodating the RFMEMS devices. The proposed packaging solution is performed at wafer-level and the wafer-to-wafer (or chip-to-wafer) bonding is performed by means of ICA/ACA (isotropic/anisotropic conductive adhesive) or AuSn solder reflow. Experimental results of preliminary prototypes of nonoptimized capped test structures have been presented. They refer to a bumpless solution for the bonding that employs ICA. Comparisons between measured S-parameters for a CPW and a short with and without capping have been shown. In both cases the losses introduced by the capping part are below 0.4 dB. The results are promising taking into account that the package used in this first experiment was not yet optimized for the parasitics reduction through electromagnetic simulation. The experimental data have also been compared with Ansoft HFSSTM simulations of the same structures. Despite some quantitative differences between simulations and experimental data, the most important features observed in the measurements are successfully reproduced by simulations. In order to perform the electromagnetic optimization of all the degrees of freedom made available by the package fabrication process, a suitable parametric model has been implemented in HFSSTM . Optimization of capped 50 CPW is demonstrated, taking into account all the technology DoFs (via diameter, capping height, recess depth, etc.). The effects induced by variations of some DoFs (in particular via diameter and resistivity of the silicon capping substrate) have been discussed.
References [1] S. Sosin, J. Tian, M. Bartek, Hybrid wafer level packaging based on a capping substrate with cavities, in: Proceedings of the Eurosensors XX, Goteborg, Sweden, September 2006. [2] K.I. Kim, J. Mu Kim, J. Man Kim, G.C. Hwang, C.W. Baek, Y.K. Kim, Packaging for RF-MEMS devices using LTCC substrate and BCB adhesive layer, J. Micromech. Microeng. 16 (2005) 150–156. [3] R. Aschenbrenner, A. Ostmann, G. Motulla, E. Zakel, Flip chip attachment using anisotropic conductive adhesives and electroless nickel bumps, IEEE Trans. Compon. Pack. Manuf. Technol. C 20 (2) (1997). [4] R. Sihlbom, M. Dernevik, Z. Lai, J.P. Starski, J. Liu, Conductive adhesives for high-frequency applications, IEEE Trans. Compon. Pack. Manuf. Technol. A 21 (3) (1998) 469–477. [5] J. Iannacci, M. Bartek, J. Tian, S. Sosin, A. Akhnoukh, R. Gaddi, A. Gnudi, Hybrid wafer-level packaging for RF-MEMS applications, in: Proceedings of the IMAPS 2006 Conference, San Diego, CA, October 9–12, 2006. [6] R. Gaddi, M. Bellei, A. Gnudi, B. Margesin, F. Giacomozzi, Interdigitated low-loss ohmic RF-MEMS switches, in: Proceedings of the NSTI 2004 Nanotechnology Conference and Trade Show, Nanotech 2004, vol. 2, Boston, MA, March 7–11, 2004, pp. 327–330. [7] Y. Kwon Park, Y. Kooh Kim, C.J. Kim, B.K. Ju, J.O. Park, Innovation ultra-thin packaging for RF-MEMS devices, in: Proceedings of the 12th International Conference on Solid State Sensors, Actuators and Microsystems, Boston, June 8–12, 2003, pp. 903–906. [8] J. Iannacci, J. Tian, S.M. Sinaga, R. Gaddi, A. Gnudi, M. Bartek, Parasitic effects reduction for wafer-level packaging of RF-MEMS, in: Proceedings of the DTIP, Stresa, Lake Maggiore, Italy, April 26–28, 2006, pp. 25– 30. [9] J. Iannacci, J. Tian, S.M. Sinaga, R. Gaddi, A. Gnudi, M. Bartek, Electrical optimization of a wafer-level package for RF-MEMS applications, in: Proceedings of the EMPS, Terme Catez, May 22–24, 2006, pp. 79–84.
Biographies Jacopo Iannacci received the MSc degree in electronic engineering from the University of Bologna (Italy) in 2003 and the PhD in information technology from the ARCES Research Centre in 2007 (University of Bologna, Italy). From 2005 he is collaborating with the HiTeC-DIMES Technology Centre (Technical University of Delft, The Netherlands) in developing packaging solutions for RF-MEMS. Marian Bartek received his MSc degree in microelectronics and optoelectronics from the Slovak Technical University, Bratislava, Slovakia, in 1988 and a PhD degree in electrical engineering at the Delft University of Technology, The Netherlands, in 1995. From 1996 to 1999, he was a post-doctoral fellow in the Electronic Instrumentation Laboratory, Delft University of Technology, dealing with research on technological aspects of integrated silicon sensor systems. Presently, he is with the Laboratory of High-Frequency Technology and Components (HiTeC), Delft University of Technology, as an assistant professor, working in the area of microsystem interfacing and wafer-level packaging for RF applications. Jun Tian was born in Beijing, China. He received the BSc degree in applied physics from the University of Electronics Science and Technology of China in 1996. Afterwards, he joined SGNEC in Beijing as a plasma etch process engineer. In 2000, he joined SSMC, a joint venture of Philips and TSMC, in Singapore as a senior plasma etch process engineer. In 2002, he came to Delft University of Technology, The Netherlands, for master study in microelectronics, and in 2004 he received the MSc degree. He is currently pursuing the PhD degree in the Laboratory of High-Frequency Technology and Components, in DIMES, TU Delft. His research interests are mainly in hybrid packaging design and processing. Roberto Gaddi was born in Reggio Emilia, Italy, on 27 May 1972. He received the Laurea degree (cum laude) in electronic engineering from University of Parma, Italy, in 1997 and the PhD degree from the University of Wales, Cardiff,
J. Iannacci et al. / Sensors and Actuators A 142 (2008) 434–441 UK, in 2002. In October 1998, he joined as a PhD student in the Centre for High Frequency Engineering, Cardiff University, UK, working in collaboration with Nokia. His research work covered large-signal time-domain measurement techniques at radio and microwave frequencies and nonlinear characterization and modelling of high-power high-frequency transistors such as silicon LDMOSFETs for telecommunication applications. From 2002 he is with the RF-IC design group at the Advanced Research Centre for Electronics Systems E. De Castro (ARCES) of the University of Bologna, Italy, working on the design, characterisation and modelling of RF-MEMS devices and reconfigurable RF circuits for wireless telecommunications.
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Antonio Gnudi graduated in electrical engineering in 1983 from the University of Bologna and received the PhD degree in electrical engineering and computer science in 1989 from the same university. From 1989 to 1990 he has been a visiting scientist at the IBM T.J. Watson Research Center, NY, USA, engaged in the development of advanced physical models and numerical simulation tools for charge transport in semiconductor devices. He became research assistant in 1990 and associate professor of electronics in 1998 at the University of Bologna. His present research interests include the design of analog CMOS circuits for RF applications, and the modelling, design and characterization of RF-MEMS devices for wireless applications.
Sensors and Actuators A 142 (2008) 434–441
Electromagnetic optimization of an RF-MEMS wafer-level package J. Iannacci a,b,∗ , M. Bartek b , J. Tian b , R. Gaddi a , A. Gnudi a a
b
ARCES-DEIS Universit`a di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy HiTeC-DIMES, Delft University of Technology, Mekelweg 4, 2628 CD Delft, The Netherlands Received 5 October 2006; received in revised form 7 August 2007; accepted 7 August 2007 Available online 19 August 2007
Abstract In this work, we present electromagnetic optimization of a wafer-level package (WLP) intended for RF-MEMS applications. The packaging solution presented is based on a high-resistivity silicon capping substrate containing recesses and copper-filled thru-hole vias. This pre-fabricated capping substrate is first wafer-level bonded to the RF-MEMS device wafer, then populated by solder spheres and finally singulated into individual packages. For the package electrical optimization, Ansoft HFSSTM electromagnetic simulator has been used in order to assess the RF-behaviour of packaged MEMS devices, including losses and mismatch due to inductive and capacitive couplings introduced by the cap. A fully parameterized model of a 50 coplanar waveguide (CPW) including all the degrees of freedom (DoFs) made available by the technological process is presented and extensively exploited for the electromagnetic optimization of the capping structure. Moreover, the measurement data obtained from the fabricated capped and uncapped test structures (50 Q CPWs and shorts) and their comparison with simulations are presented. © 2007 Elsevier B.V. All rights reserved. Keywords: Wafer-level package (WLP); RF-MEMS; Electromagnetic optimization; Ansoft HFSSTM
1. Introduction In the development of packaging techniques for RF-MEMS devices several key factors are involved. First of all, a suitable protection of the RF-MEMS devices from potentially harmful factors like mechanical shocks, moisture, dust particles, etc. is required. Moreover, the packaging should also facilitate cointegration of CMOS control circuitry (hybrid packaging) [1]. When dealing with radio frequency (RF) applications, further important issues tend to emerge. Indeed, the parasitic effects (i.e. capacitive and inductive couplings) introduced by the application of a capping substrate to the RF-MEMS devices can deteriorate rather considerably the RF performance [2]. In the worst case, this deviation can be so large that some device specifications fall outside the requirements of a certain application. In this scenario, the availability of a suitable methodology for
∗
Corresponding author at: ARCES-DEIS Universit`a di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy. Tel.: +39 051 20 93049; fax: +39 051 20 93779. E-mail addresses: [email protected], [email protected] (J. Iannacci). 0924-4247/$ – see front matter © 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.sna.2007.08.018
the prediction of the package influence on the RF-behaviour of MEMS devices is important. In this work we present a fully parametrized model of a capped coplanar waveguide (CPW) for the simulation in Ansoft HFSSTM . To this purpose, the Ansoft HFSSTM 3D electromagnetic simulator is first validated as an accurate tool in predicting the RF-behaviour of MEMS structures by comparing its results against experimental data of fabricated devices. During optimization, all the technology degrees of freedom (DoFs) allowed by the fabrication process have been parameterized within the model. Consequently, it is possible to launch an automated optimization of all these DoFs in order to reduce as much as possible the package-induced RF parasitics. 2. Technological details The packaging process, that is provided by the DIMES Technology Centre (Delft University of Technology, The Netherlands), is based on a high-resistivity silicon (HRS) substrate. The Bosch DRIE (deep reactive ion etching) process is exploited to etch recesses on the back side of the capping substrate in order to accommodate the MEMS devices. Afterwards,
J. Iannacci et al. / Sensors and Actuators A 142 (2008) 434–441
Fig. 1. Schematic view of the capping substrate showing both through vias and the etched recess.
vertical through-wafer vias are etched from the front side and the wafer is then grinded in order to reduce its thickness (Fig. 1). Subsequently, a seed-layer is sputtered on the top side and on the vias sidewalls in order to allow copper electrodeposition of pads on the substrate front side as well as via filling (from the back side). A cross-section of a vertical via aligned with the signal pad on the device wafer is shown in Fig. 2, while a SEM photograph of a vertical interconnect filled with copper after sample cutting is reported in Fig. 3. The final wafer-to-wafer or chipto-wafer bonding is performed by solder reflow or by means of ICA/ACA (isotropic/anisotropic conductive adhesive) [3,4]. In the first case AuSn bumps have to be electroplated on the substrate back side. The solution based on solder reflow allows maintaining hermeticity of the package. Nevertheless, it requires a higher thermal budget (about 300 ◦ C) compared to the solution that employs ICA/ACA (120–150 ◦ C). Most of the recently reported RF-MEMS technologies have recommended reliability thermal requirements falling below 180 ◦ C.
Fig. 2. Schematic cross-section of a vertical via that provides electrical contact and signal redistribution from the MEMS signal pad on the device wafer.
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Fig. 3. SEM photograph of a vertical via filled with copper after sample cutting.
3. Experimental results with non-optimized package Preliminary experimental data are available after the first bonding of a package chip onto a wafer containing test structures, i.e. 50 coplanar waveguides (CPWs) and shorts. The bonding solution in this case is based on the use of ICA (CE 3103 WLV made by Emerson & Cuming). In the experiment no bumps have been deposited on the capping substrate. A photograph of a gold evaporated CPW is reported in Fig. 4, while the top side of the package applied to it (and to other devices) is shown in Fig. 5 where copper pads for GSG (ground-signal-ground) probing are visible. Chip-to-wafer alignment was performed manually and ICA residues (i.e. dark stains in Fig. 4) after package de-bonding show that the vertical vias were correctly placed onto CPW lines. The comparison of the experimental S-parameters for a CPW with and without capping is shown in Fig. 6 (reflection parameter) and Fig. 7 (transmission parameter). The 50 CPW is 1350 m long. The signal line width is 116 m while the ground lines width is 300 m and the gap is 65 m. Via diameter is 50 m.
Fig. 4. Photograph of a gold evaporated matched coplanar waveguide (CPW). ICA residues after de-bonding (dark stains) prove that a good package-to-wafer alignment was reached.
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Fig. 5. Photograph of the package top side. Copper pads for GSG probe measurements are visible. These are connected to the capped test structure by means of vertical vias (see Fig. 3). Fig. 8. Smith chart of the reflection parameter for a capped and an uncapped short.
Losses and mismatch introduced by placing the capping part do not seem to be very large. For instance, the S11 parameter for the uncapped line is −26.8 dB at 17 GHz while it changes to −16.4 dB at 17 GHz for the line with package. The change of
the transmission parameter S21 is acceptable too, showing an increasing loss with frequency. The difference between the S21 parameter for the uncapped and capped CPW is within −0.24 dB up to about 20 GHz, whereas it is −0.4 dB at 30 GHz. The other type of test structure on the device wafer is a variety of shorts for 1-port measurements. The S11 parameter of a capped and uncapped short is shown in the Smith Chart of Fig. 8. The two curves for the capped and uncapped short are very close together. This means that the losses introduced by the package (top pad plus vias plus ICA joints) are quite small. The extra phase rotation of the capped short (curve labeled as “Capped short (S11)” in Fig. 8) is due to the increased electrical length through which the signal flows before reaching the actual packaged device. A better indication of the losses introduced by the packaging comes from the magnitude plot of the S11 parameter for the same short presented above (Fig. 9). The difference between the S11 parameter for the uncapped and capped short is within −0.25 dB up to about 13 GHz. In the higher frequency range (beyond 15 GHz) in spite of the spikes
Fig. 7. Transmission parameter for a CPW with and without silicon cap.
Fig. 9. Comparison of the reflection parameter for the short with and without cap.
Fig. 6. Reflection parameter for a CPW with and without silicon cap.
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Fig. 10. Comparison between experimental data and HFSSTM simulation results of a capped CPW (S11).
the two curves are still close together. The experimental comparisons shown in this section must be considered encouraging, especially since the design of the presented package does not take into account the results of the electromagnetic optimization (shown at the end of this paper) that was performed at a later time. Hence, the perspective is of achieving lower losses in the next design cycle of packaging structures. 4. Simulations versus experimental data In this section the comparison of the experimental data with simulations of the same structures in HFSSTM will be shown. The S-parameter plots for a CPW compared with the HFSSTM prediction are shown in Figs. 10 and 11. The 50 CPW is 2500 m long. The signal line width is 116 m while the ground lines width is 300 m and the gap is 60 m. By observing the reflection parameter plot of Fig. 10 it is noticeable a rather large offset between the measured and simulated curves. For instance, the difference between the experimental and simulated S11 ranges from −15 dB at 5 GHz to −12 dB at 18 GHz. However, it is also important to highlight that the HFSSTM predicted very well the qualitative behaviour of S11 over the whole fre-
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Fig. 12. Comparison between measured and simulated reflection parameter of a capped short.
quency range. In particular, the notch of the reflection parameter fits very sharply with the one that was measured at about 22 GHz. Concerning the transmission parameter (Fig. 11) in the lowfrequency range the largest difference is around 3 GHz where the simulated S21 parameter is about 0.4 dB higher than the measured one. Moreover, the transmission parameter value predicted by the HFSSTM is roughly 0.6 dB higher than the experimental one at 22 GHz and the difference raises to 0.85 dB at 30 GHz. Finally, the comparison of the measurements with the HFSSTM results for the short of the previous section is shown in Fig. 12. Besides, additional issues have to be taken into account in the interpretation of these results. Indeed, as mentioned before, a few process DoFs were not well-controlled in this first sample of packaged test structures. For instance, the height of the ICA and consequently the air gap between the two wafers is supposed to be around 10 m but the exact value is not known. Again, the thickness of the evaporated gold structures is expected to be several hundred nanometers (400–500 nm). However, because of the roughness of the wafer back side on which they have been processed, the actual thickness is not precisely known either [5]. After these considerations it is possible to conclude that the HFSSTM has shown to produce results which are in reasonable agreement with the experimental ones. 5. Validation of Ansoft HFSSTM simulator
Fig. 11. Comparison between experimental data and HFSSTM simulation results of a capped CPW (S21).
The Ansoft HFSSTM electromagnetic simulator needed to be validated in order to understand whether it represents a suitable tool to accurately predict the S-parameters of MEMS structures. Hence, the experimental data of a few devices fabricated in FBK-irst (Bruno Kessler Foundation) RF-MEMS technology (Trento, Italy) [6] have been compared with the corresponding HFSSTM simulations. An example is the suspended spiral inductor whose schematic view is shown in Fig. 13. The comparison of the S-parameters obtained from measurements and from HFSSTM simulations are shown in the plots depicted in Fig. 14. These show a very good agreement between experimental and simulated data. Indeed, the reflection parameter (S11) curves overlap in the whole frequency range. Concerning the transmission parameter (S21), its measurement is equal to −11.3 dB at
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Fig. 13. HFSSTM model of a suspended inductor fabricated in FBK-irst RFMEMS technology.
6 GHz while the HFSSTM predicts a value of −10.4 dB at 6 GHz (corresponding to a difference of about 8%). This proves that the Ansoft HFSSTM electromagnetic simulator is a suitable tool for the prediction of RF-behaviour of MEMS devices.
Fig. 15. HFSSTM model of a capped CPW. The capping substrate including the etched recess is not shown to get a plain view of the underneath device and of the through-wafer interconnects.
Fig. 15. In order to explain the approach, the top-right via in Fig. 15 is taken as an example. The coordinates (x, y, z) of the top-right via centre are parametrically written as (assuming the system origin at the left-lower corner of Fig. 16, left) x = 21 xbox + 21 xline − Xoffset
(1a)
6. Parameterized model of a capped transmission line
y = 21 ybox + Yoffset
(1b)
When dealing with several technological DoFs their parameterization allows fully automated optimization. In this work, we focus on the parasitics reduction of the package applied to CPWs instead of actual RF-MEMS devices. This choice is mainly due to the influence of the capping substrate being more easily interpreted when applied to structures with a very simple frequency response. Indeed, in this preliminary stage of development of the capping substrate process it would not be useful to focus directly on its influence on the RF performance of specific MEMS devices without knowing the general effect of each DoF variation. There is also a practical reason. In the package process optimization several trials at wafer-level are necessary. Consequently, it is preferable to use simplified test structures without the need of sacrificing actual RF-MEMS device wafers. In the HFSSTM parametrized model, suitable independent variables have been defined in order to describe all the technological DoFs (e.g. via diameter, capping substrate thickness, recess depth and so on). The HFSSTM schematic of a capped CPW is shown in
z = zSi + zOx + zline + Zbump
(1c)
where xbox , ybox , Xoffset , Yoffset and xline are defined in Fig. 16, left, and zSi , zOx , zline , Zbump in Fig. 16, right. In the previous formulas Xoffset , Yoffset and Zbump represent DoFs related to the capping part subject to optimization. The other parameters are necessary for defining of the structure geometry, but are not directly involved in the optimization of the package. 7. Electromagnetic optimization of the package The Ansoft HFSSTM simulator has been exploited in determining the influence of each DoF on the losses associated with the package [7] of a capped CPW, used as test structure. The CPW is 2000 m long, the signal line and ground lines width are 150 m and 900 m, respectively, while the gap is 30 m. The capping part height is 350 m and the frequency of the analysis was set to 15 GHz. The influence of one technological
Fig. 14. Comparison between experimental and simulated S-parameters of the suspended inductor shown in Fig. 13.
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Fig. 16. Parameterization of the center coordinates of the top-right via of Fig. 15. Left: in-plane coordinates; right: vertical coordinates.
and one geometrical DoF on the S-parameters is discussed here. The technological DoF is the resistivity of the silicon capping substrate. Wafers with various resistivities were on stock. It was possible to chose among a low-resistivity silicon (LRS) wafer (with resistivity of about 15 cm) and four high-resistivity silicon (HRS) wafers (with resistivity of 1 k cm, 2 k cm, 3 k cm and 4 k cm [8,9]). The geometrical DoF is via diameter that has been varied within the 10–100 m range. The 3D plot of Fig. 17 shows that low values of the reflection parameter S11 are achieved for low values of the via diameter with the LRS substrate, and also for large values of the via diameter (over 60 m) with the HRS substrates. For instance, S11 = −16.1 dB and S11 = −13.6 dB for via diameter values of 10 m and 40 m, respectively, with the LRS substrate, while, for the 2 k cm substrate, S11 ranges between −13.4 dB and −16.5 dB for via diameters between 60 m and 100 m. However, S21 must also be considered to monitor
the losses. From the 3D plot of Fig. 18 we verify that the poorest values of S21 are obtained for narrow vias etched in a LRS substrate. In particular, the 15 cm substrate must be avoided since, when used, S21 ≤ −8.10 dB. This can be explained with the presence of losses in the substrate due to eddy currents surrounding the vias. On the contrary, high values of the transmission parameter are achieved for HRS substrate in combination with large vias (above 60 m). For instance, S21 falls into the [−1.00,−0.64] dB interval for via diameters ranging between 50 m and 100 m, when a 2 k cm silicon substrate is employed. In conclusion, optimization of both reflection and transmission parameters shows that the best choice is represented by vias with a diameter of at least 60 m. Concerning the type of substrate, while the use of a LRS one is not an option, the choice of the proper HRS substrate brings up a possible trade-off between performance and the costs. In this respect, since the benefits achieved in terms of S-parameters with very
Fig. 17. Reflection parameter of the capped CPW as a function of the via diameter and of the capping silicon substrate resistivity at 15 GHz.
Fig. 18. Transmission parameter of the capped CPW as a function of the via diameter and of the capping silicon substrate resistivity at 15 GHz.
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Table 1 Effect on losses and mismatch of the variations of the most significant DoFs related with the package fabrication calculated with Ansoft HFSSTM simulations Capping silicon substrate resistivity Capping silicon substrate height Recess depth Via diameter GSG vias lateral distance Bumps height
+ − + + + +
The signs “+” and “−” indicate if the corresponding DoF has to be, respectively, increased or decreased in order to reduce losses and mismatch.
HRS substrates (3–4 k cm) are not that large with respect to the 1 k cm and 2 k cm silicon wafers, the best choice would probably fall on one of the latter two, the use of the 2 k cm being probably the most reasonable one. A similar analysis can be carried out for the other optimization parameters. In Table 1 the qualitative effects of the most significant technological DoFs on the losses and mismatch introduced by the capping part are reported. These results have been obtained with the parametric model of a capped CPW discussed in the previous section. 8. Conclusions In this work we have presented a new approach to the fabrication and electromagnetic optimization of a wafer-level package for RF-MEMS devices. The proposed approach is based on a capping high-resistivity silicon substrate that is wafer-level bonded to the RF-MEMS device wafer. The capping substrate contains electroplated through-wafer copper vias for signal redistribution and recesses for accommodating the RFMEMS devices. The proposed packaging solution is performed at wafer-level and the wafer-to-wafer (or chip-to-wafer) bonding is performed by means of ICA/ACA (isotropic/anisotropic conductive adhesive) or AuSn solder reflow. Experimental results of preliminary prototypes of nonoptimized capped test structures have been presented. They refer to a bumpless solution for the bonding that employs ICA. Comparisons between measured S-parameters for a CPW and a short with and without capping have been shown. In both cases the losses introduced by the capping part are below 0.4 dB. The results are promising taking into account that the package used in this first experiment was not yet optimized for the parasitics reduction through electromagnetic simulation. The experimental data have also been compared with Ansoft HFSSTM simulations of the same structures. Despite some quantitative differences between simulations and experimental data, the most important features observed in the measurements are successfully reproduced by simulations. In order to perform the electromagnetic optimization of all the degrees of freedom made available by the package fabrication process, a suitable parametric model has been implemented in HFSSTM . Optimization of capped 50 CPW is demonstrated, taking into account all the technology DoFs (via diameter, capping height, recess depth, etc.). The effects induced by variations of some DoFs (in particular via diameter and resistivity of the silicon capping substrate) have been discussed.
References [1] S. Sosin, J. Tian, M. Bartek, Hybrid wafer level packaging based on a capping substrate with cavities, in: Proceedings of the Eurosensors XX, Goteborg, Sweden, September 2006. [2] K.I. Kim, J. Mu Kim, J. Man Kim, G.C. Hwang, C.W. Baek, Y.K. Kim, Packaging for RF-MEMS devices using LTCC substrate and BCB adhesive layer, J. Micromech. Microeng. 16 (2005) 150–156. [3] R. Aschenbrenner, A. Ostmann, G. Motulla, E. Zakel, Flip chip attachment using anisotropic conductive adhesives and electroless nickel bumps, IEEE Trans. Compon. Pack. Manuf. Technol. C 20 (2) (1997). [4] R. Sihlbom, M. Dernevik, Z. Lai, J.P. Starski, J. Liu, Conductive adhesives for high-frequency applications, IEEE Trans. Compon. Pack. Manuf. Technol. A 21 (3) (1998) 469–477. [5] J. Iannacci, M. Bartek, J. Tian, S. Sosin, A. Akhnoukh, R. Gaddi, A. Gnudi, Hybrid wafer-level packaging for RF-MEMS applications, in: Proceedings of the IMAPS 2006 Conference, San Diego, CA, October 9–12, 2006. [6] R. Gaddi, M. Bellei, A. Gnudi, B. Margesin, F. Giacomozzi, Interdigitated low-loss ohmic RF-MEMS switches, in: Proceedings of the NSTI 2004 Nanotechnology Conference and Trade Show, Nanotech 2004, vol. 2, Boston, MA, March 7–11, 2004, pp. 327–330. [7] Y. Kwon Park, Y. Kooh Kim, C.J. Kim, B.K. Ju, J.O. Park, Innovation ultra-thin packaging for RF-MEMS devices, in: Proceedings of the 12th International Conference on Solid State Sensors, Actuators and Microsystems, Boston, June 8–12, 2003, pp. 903–906. [8] J. Iannacci, J. Tian, S.M. Sinaga, R. Gaddi, A. Gnudi, M. Bartek, Parasitic effects reduction for wafer-level packaging of RF-MEMS, in: Proceedings of the DTIP, Stresa, Lake Maggiore, Italy, April 26–28, 2006, pp. 25– 30. [9] J. Iannacci, J. Tian, S.M. Sinaga, R. Gaddi, A. Gnudi, M. Bartek, Electrical optimization of a wafer-level package for RF-MEMS applications, in: Proceedings of the EMPS, Terme Catez, May 22–24, 2006, pp. 79–84.
Biographies Jacopo Iannacci received the MSc degree in electronic engineering from the University of Bologna (Italy) in 2003 and the PhD in information technology from the ARCES Research Centre in 2007 (University of Bologna, Italy). From 2005 he is collaborating with the HiTeC-DIMES Technology Centre (Technical University of Delft, The Netherlands) in developing packaging solutions for RF-MEMS. Marian Bartek received his MSc degree in microelectronics and optoelectronics from the Slovak Technical University, Bratislava, Slovakia, in 1988 and a PhD degree in electrical engineering at the Delft University of Technology, The Netherlands, in 1995. From 1996 to 1999, he was a post-doctoral fellow in the Electronic Instrumentation Laboratory, Delft University of Technology, dealing with research on technological aspects of integrated silicon sensor systems. Presently, he is with the Laboratory of High-Frequency Technology and Components (HiTeC), Delft University of Technology, as an assistant professor, working in the area of microsystem interfacing and wafer-level packaging for RF applications. Jun Tian was born in Beijing, China. He received the BSc degree in applied physics from the University of Electronics Science and Technology of China in 1996. Afterwards, he joined SGNEC in Beijing as a plasma etch process engineer. In 2000, he joined SSMC, a joint venture of Philips and TSMC, in Singapore as a senior plasma etch process engineer. In 2002, he came to Delft University of Technology, The Netherlands, for master study in microelectronics, and in 2004 he received the MSc degree. He is currently pursuing the PhD degree in the Laboratory of High-Frequency Technology and Components, in DIMES, TU Delft. His research interests are mainly in hybrid packaging design and processing. Roberto Gaddi was born in Reggio Emilia, Italy, on 27 May 1972. He received the Laurea degree (cum laude) in electronic engineering from University of Parma, Italy, in 1997 and the PhD degree from the University of Wales, Cardiff,
J. Iannacci et al. / Sensors and Actuators A 142 (2008) 434–441 UK, in 2002. In October 1998, he joined as a PhD student in the Centre for High Frequency Engineering, Cardiff University, UK, working in collaboration with Nokia. His research work covered large-signal time-domain measurement techniques at radio and microwave frequencies and nonlinear characterization and modelling of high-power high-frequency transistors such as silicon LDMOSFETs for telecommunication applications. From 2002 he is with the RF-IC design group at the Advanced Research Centre for Electronics Systems E. De Castro (ARCES) of the University of Bologna, Italy, working on the design, characterisation and modelling of RF-MEMS devices and reconfigurable RF circuits for wireless telecommunications.
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Antonio Gnudi graduated in electrical engineering in 1983 from the University of Bologna and received the PhD degree in electrical engineering and computer science in 1989 from the same university. From 1989 to 1990 he has been a visiting scientist at the IBM T.J. Watson Research Center, NY, USA, engaged in the development of advanced physical models and numerical simulation tools for charge transport in semiconductor devices. He became research assistant in 1990 and associate professor of electronics in 1998 at the University of Bologna. His present research interests include the design of analog CMOS circuits for RF applications, and the modelling, design and characterization of RF-MEMS devices for wireless applications.