- Email: [email protected]
Thermal optimization of GaN-on-Si HEMTs with plastic package
Microelectronics Reliability 51 (2011) 1788–1791
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Thermal optimization of GaN-on-Si HEMTs with plastic package R. Liu a,b,⇑, D. Schreurs a, W. De Raedt b, F. Vanaverbeke b, R. Mertens a,b, I. De Wolf b,c a
Department of Electrical Engineering, K.U. Leuven, Kasteelpark Arenberg 10, 3001 Leuven, Belgium imec vzw, Kapeldreef 75, 3001 Leuven, Belgium c Department of Metallurgy and Materials Engineering, K.U. Leuven, Kasteelpark Arenberg 44, 3001 Leuven, Belgium b
a r t i c l e
i n f o
Article history: Received 25 May 2011 Received in revised form 23 June 2011 Accepted 28 June 2011 Available online 22 July 2011
a b s t r a c t In this paper, the degradation of a GaN-on-Si based RF power amplifier is investigated by means of electrical characterization. The reliability issues identified during this work are clearly related to the high thermal resistance between the device and the heat sink, which causes gate-leakage current and output power degradation. Moreover, we have demonstrated a low cost thermal optimization approach by increasing the thermal dissipation area and reducing the device carrier thickness. Measurement results show that the saturated output power can be increased from 1 W up to 5 W without device degradation at 3.8 GHz. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction AlGaN/GaN based high electron mobility transistors (HEMTs) are promising devices for high power and high frequency applications [1]. Recent research efforts are focused on improving the GaN growth quality on large scale Si substrate as well as the reliability [2,3]. Since the use of silicon as substrate is economical and well developed in semiconductor industry, the resulting GaN-on-Si HEMTs can offer a significant cost reduction as compared to their counterparts such as sapphire and silicon carbide (SiC) [4]. Up to now, a high power density (>10 W/mm) with high thermal stability at 325 °C has been reported [3]. Moreover, a plastic overmold packaging solution is being used for GaN-on-Si HEMTs, offering >10 cost reduction compared to a typical ceramic packaging solution [5]. However, most of the reported reliability studies on GaN-on-Si HEMTs are mainly done at wafer level [3,6–8] and without taking the practical assembling and packaging effects into account. In this paper, we experimentally study the thermal effects on the GaN-onSi power amplifier (PA) performance degradation by means of DC and RF characterizations. Moreover, we demonstrate a practical thermal optimization approach with a low cost plastic packaged GaN-on-Si PA module to further improve the RF performance. 2. Failure analysis The employed GaN-on-Si HEMTs have been grown by metal–organic chemical vapor deposition (MOCVD) on a high ⇑ Corresponding author at: imec vzw, Kapeldreef 75, 3001 Leuven, Belgium. Tel.: +32 16 28 82 26; fax: +32 16 28 85 00. E-mail address: [email protected] (R. Liu). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.06.033
resistive silicon substrate. The device die has a dimension of 0.5 mm 0.6 mm, and is grounded using vias after wafer thinning down to 150 lm [2]. The total gate length is 2 mm. A previous reliability study shows that the processing technology has a MTTF > 107 hours at 150 °C and a high temperature operating life of 1000 h with 28 V drain voltage and 150 °C junction temperature [5]. In contrast to the promising on-wafer results, we experienced serious device degradation even at a small drain voltage after die-attachment. Fig. 1a shows the mentioned GaN-on-Si HEMT attached on a low temperature co-fired ceramic (LTCC) carrier with silver-filled epoxy. All the matching circuits are implemented with fully embedded passives in the LTCC substrate (772 lm thickness). Thermal management underneath the epoxy is addressed by adding thermal vias filled with Au which connect through the LTCC substrate to the heat sink at the backside. However, the output power is reduced with increasing the drain voltage and it collapses under high voltage, as shown in Fig 2. Furthermore, the device exhibits a surface change after a RF large signal measurement with a drain voltage of 20 V, and some samples are burned out at a high drain voltage of 30 V (Fig. 1b and c). It should be noted that although the thermal vias are used for heat dissipation, this dissipation is still limited by the device size and practical design rules such as via size, spacing, and thickness. In our case, the highest temperature area is along the device fingers, which are relatively large compared to the small thermal vias (150 lm diameter) underneath. Consequently, the heat cannot spread efficiently to the heat sink. Table 1 lists the thermal conductivity of the various involved materials at room temperature. It further confirms that the heat spread is mainly limited between the device die and the LTCC carrier fixture.
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R. Liu et al. / Microelectronics Reliability 51 (2011) 1788–1791 Table 1 Thermal property of different materials. Material
Thermal conductivity (W/mK)
AlGaN GaN SiC Silver filled epoxy High resistive Si Ferro A6M (LTCC) Cu (heat sink) Rogers 4003C (PCB) Au SnPb (63/37)
19 130 430 3–29 159 2–5 370 0.64 318 50
Fig. 1. Photograph of device degradation on LTCC substrate (a) before RF large signal measurement; (b) at Vds = 20 V and (c) at Vds = 30 V.
3. Thermal optimization 3.1. Horizontal optimization In order to address the degradation of LTCC-PA, we employ the above GaN-on-Si HEMTs with a commercially available plastic package PSOP [9]. Fig. 3 illustrates the cross section of the fabricated PA module on a PCB. The device die is attached to a thin Cu flange with silver filled epoxy. In order to enhance the heat spread dissipation efficiently, the Cu flange area is fixed to 3 mm 2 mm in this package which is around 20 times larger than the device die. Wire bondings are then encapsulated in a low cost plastic overmold. Based on this configuration, further measurement results show that the saturated output power deviates less than 1 dB after the DC stress under a high junction temperature of 200 °C and a drain voltage of 28 V over 168 h [5]. In order to enhance the heat spread effetely, SnPb solder paste is used in the vias for heat dissipation between the packaged device and the heat sink at the PCB backside. Fig. 4 shows the fabricated PCB-PA module with a low cost plastic packaged GaN-on-Si HEMT. All the matching circuits are implemented with transmission lines on the top Cu layer of the board. The material of the selected PCB is Rogers 4003C with a thickness of 1.5 mm. In our case, the thermal vias’ diameter and minimum spacing are set to 500 lm and 250 lm, which is the trade-off between the PCB design rules and manufacturing cost. Moreover, the simulation results show that further increasing the via diameter has limited effects on thermal optimization [10]. Fig. 5 depicts the measured large signal performance of the proposed PCB-PA and the comparison with LTCC-PA under the same
Fig. 2. Measured CW power transfer characteristics with different drain voltages at Ids = 50 mA, f0 = 3.8 GHz.
Fig. 3. Cross section of plastic packaged PA module.
bias condition. It shows that the gain of the LTCC-PA is quite similar to that of the PCB-PA under low power regions, but it reaches compression earlier than the PCB-PA due to the thermal effects, as shown in Fig. 5a. As a result, the proposed PCB-PA can deliver a higher drain current as well as a higher output power and efficiency (Fig. 5b). Further measurements in Fig. 6 indicate that the PCB-PA can exhibit a maximum output power of 3.2 W together with a drain voltage of 25 V, and no evidence is seen showing device degradation. Based on the above results, it is clear that the output power can be improved by increasing the heat spread area. 3.2. Vertical optimization Besides increasing the heat spread area, one practical approach is to decrease the thickness of the PCB and to use high thermal conductive metal layers. Fig. 7 shows the improved PCB-PA design. The PCB material is still Rogers 4003C but with a reduced thickness
Fig. 4. Photograph of PCB-PA module.
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Pout (dBm), Gain (dB), Drain efficiency (%)
a 60 Pout 50
Gain Drain efficiency
40 30 20 10 0 -5
0
5
10 Pin (dBm)
15
20
25
b 0.25 PCB-PA 1.5mm thickness LTCC-PA
Ids (A)
0.2
Fig. 7. Photograph of the improved PCB-PA module with a reduced thickness of 0.8 mm (a) top view and (b) bottom view.
0.15 0.1 0.05 0
-5
0
5
10 Pin (dBm)
15
20
25
Fig. 5. Measured CW power transfer characteristics of LTCC-PA (dashed) and PCBPA (thick), at Ids = 50 mA, Vds = 15 V, f0 = 3.8 GHz.
Fig. 8. Output power comparison between two PCB-PA modules at Ids = 50 mA, f0 = 3.8 GHz.
Fig. 6. Output power comparison between LTCC-PA and PCB-PA at fixed Ids = 50 mA, f0 = 3.8 GHz.
of 0.8 mm. Under this configuration, the width of typical 50 X microstrip line can be reduced to 1.8 mm and can still fit well with the device soldering pad as well as the RF sub miniature version (SMA) connectors. All the matching networks are re-designed correspondingly. Furthermore, the PCB is electroplated with Ni/Au to further reduce the thermal resistance. Again, dedicated vias (500 lm diameter) are filled with SnPb to act as thermal vias underneath the packaged device. Fig. 7 illustrates the improved PCB-PA module and Fig. 8 shows the output power comparison at each drain voltage. It shows that the output power of 1.5 mm PCB-PA module decreases significantly beyond 25 V, and similar phenomena was also observed during the initial load-pull measurement at 1 GHz. Nevertheless, reducing the PCB thickness to 0.8 mm can further improve the output power by 18% at the same drain voltage of 25 V, and it can boost the output power up to 5 W together with a higher operating voltage of 30 V. One could also expect that replacing the thermal vias with a Cu pedestal will further reduce the thermal resistance between the
Fig. 9. Thermal scan comparison between using Cu pedestal and thermal vias at Vds = 28 V.
active devices and the heat sink. Fig. 9 shows the infrared thermal scan results of using thermal vias and Cu pedestal [10]. It shows that the peak junction temperature can be reduced only by 15 °C at a dissipated power of 4.2 W, and such small contribution (7%) is negligible in practice. Moreover, using the Cu pedestal approach will increase the heat sink design complexity as well as the device assembly cost, yielding a cost comparable to classical ceramic packaging solutions. 4. Conclusion We have investigated a failure mechanism which occurs in low cost GaN-on-Si HEMTs, and which is observed after attaching the HEMTs on LTCC substrate and PCBs. Failure analysis demonstrated that the performance degradation is mainly due to thermal effects.
R. Liu et al. / Microelectronics Reliability 51 (2011) 1788–1791
Practical thermal optimization is carried out by increasing the thermal dissipation area within a low cost plastic package, and by reducing the PCB thickness. The measured results at 3.8 GHz show that the maximum output power can be improved by 500 % compared with the LTCC-PA, and by 153 % by reducing PCB thickness. All the results are very encouraging and confirm that the plastic packaged GaN-on-Si HEMTs are very promising for low-cost and high performance RF applications. Acknowledgment The authors like to thank imec assembly team for their help with die attachment and wirebonding. References [1] Mishra UK et al. AlGaN/GaN HEMTs an overview of device operation and application. Proc IEEE 2002;90(6):1022–31.
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[2] Johnson JW et al. 12 W/mm AIGaN–GaN HFETs on silicon substrates. IEEE Electron Dev Lett 2004;25(7):459–61. [3] Medjdoub F et al. GaN-on-Si HEMTS above 10 W/mm at 2 GHz together with high thermal stability at 325 °C. In: European microwave conf, 2010. p. 37–40. [4] Liu R et al. A low cost compact LTCC-based GaN power amplifier module. In: IEEE workshop on integrated nonlinear microwave and millimetre-wave circuits, 2011. p. 53–6. [5] Nitronex Corporation. NPTB00004D qualification document; 2009. [6] Jungwoo J et al. Gate current degradation mechanisms of GaN high electron mobility transistors. In: IEEE int electron devices meeting, 2007. p. 385–8. [7] Zanoni E et al. A review of failure modes and mechanisms of GaN-based HEMTs. In: IEEE int electron devices meeting, 2007. p. 381–4. [8] Marcon D et al. A comprehensive reliability investigation of the voltage-, temperature- and device geometry-dependence of the gate degradation on state-of-the-art GaN-on-Si HEMTs. In: IEEE int electron devices meeting, 2010. p. 472–5. [9] Amkor Technology. PSOP2 & PSOP3 data sheet; 2009. [10] Nitronex Corporation. Thermal considerations for GaN technology; 2008.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Thermal optimization of GaN-on-Si HEMTs with plastic package R. Liu a,b,⇑, D. Schreurs a, W. De Raedt b, F. Vanaverbeke b, R. Mertens a,b, I. De Wolf b,c a
Department of Electrical Engineering, K.U. Leuven, Kasteelpark Arenberg 10, 3001 Leuven, Belgium imec vzw, Kapeldreef 75, 3001 Leuven, Belgium c Department of Metallurgy and Materials Engineering, K.U. Leuven, Kasteelpark Arenberg 44, 3001 Leuven, Belgium b
a r t i c l e
i n f o
Article history: Received 25 May 2011 Received in revised form 23 June 2011 Accepted 28 June 2011 Available online 22 July 2011
a b s t r a c t In this paper, the degradation of a GaN-on-Si based RF power amplifier is investigated by means of electrical characterization. The reliability issues identified during this work are clearly related to the high thermal resistance between the device and the heat sink, which causes gate-leakage current and output power degradation. Moreover, we have demonstrated a low cost thermal optimization approach by increasing the thermal dissipation area and reducing the device carrier thickness. Measurement results show that the saturated output power can be increased from 1 W up to 5 W without device degradation at 3.8 GHz. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction AlGaN/GaN based high electron mobility transistors (HEMTs) are promising devices for high power and high frequency applications [1]. Recent research efforts are focused on improving the GaN growth quality on large scale Si substrate as well as the reliability [2,3]. Since the use of silicon as substrate is economical and well developed in semiconductor industry, the resulting GaN-on-Si HEMTs can offer a significant cost reduction as compared to their counterparts such as sapphire and silicon carbide (SiC) [4]. Up to now, a high power density (>10 W/mm) with high thermal stability at 325 °C has been reported [3]. Moreover, a plastic overmold packaging solution is being used for GaN-on-Si HEMTs, offering >10 cost reduction compared to a typical ceramic packaging solution [5]. However, most of the reported reliability studies on GaN-on-Si HEMTs are mainly done at wafer level [3,6–8] and without taking the practical assembling and packaging effects into account. In this paper, we experimentally study the thermal effects on the GaN-onSi power amplifier (PA) performance degradation by means of DC and RF characterizations. Moreover, we demonstrate a practical thermal optimization approach with a low cost plastic packaged GaN-on-Si PA module to further improve the RF performance. 2. Failure analysis The employed GaN-on-Si HEMTs have been grown by metal–organic chemical vapor deposition (MOCVD) on a high ⇑ Corresponding author at: imec vzw, Kapeldreef 75, 3001 Leuven, Belgium. Tel.: +32 16 28 82 26; fax: +32 16 28 85 00. E-mail address: [email protected] (R. Liu). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.06.033
resistive silicon substrate. The device die has a dimension of 0.5 mm 0.6 mm, and is grounded using vias after wafer thinning down to 150 lm [2]. The total gate length is 2 mm. A previous reliability study shows that the processing technology has a MTTF > 107 hours at 150 °C and a high temperature operating life of 1000 h with 28 V drain voltage and 150 °C junction temperature [5]. In contrast to the promising on-wafer results, we experienced serious device degradation even at a small drain voltage after die-attachment. Fig. 1a shows the mentioned GaN-on-Si HEMT attached on a low temperature co-fired ceramic (LTCC) carrier with silver-filled epoxy. All the matching circuits are implemented with fully embedded passives in the LTCC substrate (772 lm thickness). Thermal management underneath the epoxy is addressed by adding thermal vias filled with Au which connect through the LTCC substrate to the heat sink at the backside. However, the output power is reduced with increasing the drain voltage and it collapses under high voltage, as shown in Fig 2. Furthermore, the device exhibits a surface change after a RF large signal measurement with a drain voltage of 20 V, and some samples are burned out at a high drain voltage of 30 V (Fig. 1b and c). It should be noted that although the thermal vias are used for heat dissipation, this dissipation is still limited by the device size and practical design rules such as via size, spacing, and thickness. In our case, the highest temperature area is along the device fingers, which are relatively large compared to the small thermal vias (150 lm diameter) underneath. Consequently, the heat cannot spread efficiently to the heat sink. Table 1 lists the thermal conductivity of the various involved materials at room temperature. It further confirms that the heat spread is mainly limited between the device die and the LTCC carrier fixture.
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R. Liu et al. / Microelectronics Reliability 51 (2011) 1788–1791 Table 1 Thermal property of different materials. Material
Thermal conductivity (W/mK)
AlGaN GaN SiC Silver filled epoxy High resistive Si Ferro A6M (LTCC) Cu (heat sink) Rogers 4003C (PCB) Au SnPb (63/37)
19 130 430 3–29 159 2–5 370 0.64 318 50
Fig. 1. Photograph of device degradation on LTCC substrate (a) before RF large signal measurement; (b) at Vds = 20 V and (c) at Vds = 30 V.
3. Thermal optimization 3.1. Horizontal optimization In order to address the degradation of LTCC-PA, we employ the above GaN-on-Si HEMTs with a commercially available plastic package PSOP [9]. Fig. 3 illustrates the cross section of the fabricated PA module on a PCB. The device die is attached to a thin Cu flange with silver filled epoxy. In order to enhance the heat spread dissipation efficiently, the Cu flange area is fixed to 3 mm 2 mm in this package which is around 20 times larger than the device die. Wire bondings are then encapsulated in a low cost plastic overmold. Based on this configuration, further measurement results show that the saturated output power deviates less than 1 dB after the DC stress under a high junction temperature of 200 °C and a drain voltage of 28 V over 168 h [5]. In order to enhance the heat spread effetely, SnPb solder paste is used in the vias for heat dissipation between the packaged device and the heat sink at the PCB backside. Fig. 4 shows the fabricated PCB-PA module with a low cost plastic packaged GaN-on-Si HEMT. All the matching circuits are implemented with transmission lines on the top Cu layer of the board. The material of the selected PCB is Rogers 4003C with a thickness of 1.5 mm. In our case, the thermal vias’ diameter and minimum spacing are set to 500 lm and 250 lm, which is the trade-off between the PCB design rules and manufacturing cost. Moreover, the simulation results show that further increasing the via diameter has limited effects on thermal optimization [10]. Fig. 5 depicts the measured large signal performance of the proposed PCB-PA and the comparison with LTCC-PA under the same
Fig. 2. Measured CW power transfer characteristics with different drain voltages at Ids = 50 mA, f0 = 3.8 GHz.
Fig. 3. Cross section of plastic packaged PA module.
bias condition. It shows that the gain of the LTCC-PA is quite similar to that of the PCB-PA under low power regions, but it reaches compression earlier than the PCB-PA due to the thermal effects, as shown in Fig. 5a. As a result, the proposed PCB-PA can deliver a higher drain current as well as a higher output power and efficiency (Fig. 5b). Further measurements in Fig. 6 indicate that the PCB-PA can exhibit a maximum output power of 3.2 W together with a drain voltage of 25 V, and no evidence is seen showing device degradation. Based on the above results, it is clear that the output power can be improved by increasing the heat spread area. 3.2. Vertical optimization Besides increasing the heat spread area, one practical approach is to decrease the thickness of the PCB and to use high thermal conductive metal layers. Fig. 7 shows the improved PCB-PA design. The PCB material is still Rogers 4003C but with a reduced thickness
Fig. 4. Photograph of PCB-PA module.
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R. Liu et al. / Microelectronics Reliability 51 (2011) 1788–1791
Pout (dBm), Gain (dB), Drain efficiency (%)
a 60 Pout 50
Gain Drain efficiency
40 30 20 10 0 -5
0
5
10 Pin (dBm)
15
20
25
b 0.25 PCB-PA 1.5mm thickness LTCC-PA
Ids (A)
0.2
Fig. 7. Photograph of the improved PCB-PA module with a reduced thickness of 0.8 mm (a) top view and (b) bottom view.
0.15 0.1 0.05 0
-5
0
5
10 Pin (dBm)
15
20
25
Fig. 5. Measured CW power transfer characteristics of LTCC-PA (dashed) and PCBPA (thick), at Ids = 50 mA, Vds = 15 V, f0 = 3.8 GHz.
Fig. 8. Output power comparison between two PCB-PA modules at Ids = 50 mA, f0 = 3.8 GHz.
Fig. 6. Output power comparison between LTCC-PA and PCB-PA at fixed Ids = 50 mA, f0 = 3.8 GHz.
of 0.8 mm. Under this configuration, the width of typical 50 X microstrip line can be reduced to 1.8 mm and can still fit well with the device soldering pad as well as the RF sub miniature version (SMA) connectors. All the matching networks are re-designed correspondingly. Furthermore, the PCB is electroplated with Ni/Au to further reduce the thermal resistance. Again, dedicated vias (500 lm diameter) are filled with SnPb to act as thermal vias underneath the packaged device. Fig. 7 illustrates the improved PCB-PA module and Fig. 8 shows the output power comparison at each drain voltage. It shows that the output power of 1.5 mm PCB-PA module decreases significantly beyond 25 V, and similar phenomena was also observed during the initial load-pull measurement at 1 GHz. Nevertheless, reducing the PCB thickness to 0.8 mm can further improve the output power by 18% at the same drain voltage of 25 V, and it can boost the output power up to 5 W together with a higher operating voltage of 30 V. One could also expect that replacing the thermal vias with a Cu pedestal will further reduce the thermal resistance between the
Fig. 9. Thermal scan comparison between using Cu pedestal and thermal vias at Vds = 28 V.
active devices and the heat sink. Fig. 9 shows the infrared thermal scan results of using thermal vias and Cu pedestal [10]. It shows that the peak junction temperature can be reduced only by 15 °C at a dissipated power of 4.2 W, and such small contribution (7%) is negligible in practice. Moreover, using the Cu pedestal approach will increase the heat sink design complexity as well as the device assembly cost, yielding a cost comparable to classical ceramic packaging solutions. 4. Conclusion We have investigated a failure mechanism which occurs in low cost GaN-on-Si HEMTs, and which is observed after attaching the HEMTs on LTCC substrate and PCBs. Failure analysis demonstrated that the performance degradation is mainly due to thermal effects.
R. Liu et al. / Microelectronics Reliability 51 (2011) 1788–1791
Practical thermal optimization is carried out by increasing the thermal dissipation area within a low cost plastic package, and by reducing the PCB thickness. The measured results at 3.8 GHz show that the maximum output power can be improved by 500 % compared with the LTCC-PA, and by 153 % by reducing PCB thickness. All the results are very encouraging and confirm that the plastic packaged GaN-on-Si HEMTs are very promising for low-cost and high performance RF applications. Acknowledgment The authors like to thank imec assembly team for their help with die attachment and wirebonding. References [1] Mishra UK et al. AlGaN/GaN HEMTs an overview of device operation and application. Proc IEEE 2002;90(6):1022–31.
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[2] Johnson JW et al. 12 W/mm AIGaN–GaN HFETs on silicon substrates. IEEE Electron Dev Lett 2004;25(7):459–61. [3] Medjdoub F et al. GaN-on-Si HEMTS above 10 W/mm at 2 GHz together with high thermal stability at 325 °C. In: European microwave conf, 2010. p. 37–40. [4] Liu R et al. A low cost compact LTCC-based GaN power amplifier module. In: IEEE workshop on integrated nonlinear microwave and millimetre-wave circuits, 2011. p. 53–6. [5] Nitronex Corporation. NPTB00004D qualification document; 2009. [6] Jungwoo J et al. Gate current degradation mechanisms of GaN high electron mobility transistors. In: IEEE int electron devices meeting, 2007. p. 385–8. [7] Zanoni E et al. A review of failure modes and mechanisms of GaN-based HEMTs. In: IEEE int electron devices meeting, 2007. p. 381–4. [8] Marcon D et al. A comprehensive reliability investigation of the voltage-, temperature- and device geometry-dependence of the gate degradation on state-of-the-art GaN-on-Si HEMTs. In: IEEE int electron devices meeting, 2010. p. 472–5. [9] Amkor Technology. PSOP2 & PSOP3 data sheet; 2009. [10] Nitronex Corporation. Thermal considerations for GaN technology; 2008.