- Email: [email protected]
Thermal studies of a plastic dual-in-line package
World Abstracts continued from page 39
IBM multichip multilayer ceramic modules for LSI chips - design for performance and density B. T. CLARK and Y. M. HILL IEEE Trans. Components, ttybrids Mfg Technology. Chmt-3(1), 89 (March 1980). The design objectives and features of two modules are outlined which, with their LSI chips, give significant advantages of performance, power reduction, logic gate density, and reliability in their IBM 4300 processor applications. In these applications an average module gate density of 196 gates/cmz is achieved. This is 30 times the density achieved in IBM's monolithic systems technology (MST). Even larger density improvements are realised at the card level. A ULA is more than silicon J. A. VERNON, N. R. CROCKER and J. P. SINGLETON
Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Publn. 178, 51. For many years now the computer indhstry has been building systems with a large number of printed circuit boards which may contain many hundreds of gates. These boards have been well supported by Design Automation in the areas of coding, electrical loading rules, automatic tracking, logic simulation and automatic test pattern generation. Since LSI offers the advantages of cost, performance and reliability, how should the LSI be structured to take full advantage of Design Automation? The LSI parts must also have a short development time and hence low development cost, be error free and have a fast turnround from the logic diagram to the samples. It is the purpose of this paper to show that these objectives for LSI can be achieved by using the Uncommitted Logic Array, ULA approach to LSI design.. VLSI directions and impact B. T. M U R P H Y
Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Publn. 178, 70. The roots of VLSI technology are embedded in the fertile soll of the silicon transistor technology of the 1950s. In fact, the conjunction of the 'printable' transistor and the digital computer may prove to have been one of the most profound events in history. Its impact on our lifestyle has already reached major proportions. The symbol of the engineer is no longer the slide rule - it is the computer terminal. Society in general has been in a state of future shock over the ever more pervasive influence of transistor intelligence. The full implications of even state-of-the-art technology will take another decade or so to work out. The printed silicon transistor alone is capable of taking another few orders of magnitude further in VLSI chip performance. Small wonder that the awareness of changes coming from the impact of VLSI has now extended well beyond the ranks of engineers. Visions of the future conjured up by VLSI range from wrist watch computers through anthropomorphic robots to two dimensional 'brains' with the transistor as the cell. In this digest, I will deal with some general issues. In the talk itself, I plan to use this as a frame of reference for dealing with some specific topics in more detail.
1.2
MOS
ltigh density uncommitted arrays using an advanced CMOS technology W. T. ALEXANDER, S. J. BOARDMAN, P. KREBS and A. T. P. MacARTHUR Fifth Solid State Circuits Conference- ESSCIRC 79, IEE Publn. 178, 76. A CMOS Uncommitted Logic Array is presented based on a symmetrical cell design allowing connection efficiencies of over 90% and complexities of up to 800 gates. Each new circuit requires the design of only one interconnection mask, assisted by a cell library backed by decals. This gives short turn round times and few errors for custom and customer design. Furthermore, with a small investment, the design house can carry out the final commitment stage. Design aspects and reliability ofa synchronlser made in MOS technology H. J. M. VEENDRICK Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Publn. 178, 8. In asynchronous communication between digital systems signals may occur that are not logically defiined[1]. An example is a multimicroprocessor system of which the microprocessors do not share a common clock. This means that signals are 40
generated random in time. Especially it can happen that an input signal is changing during a sample clock edge. This situation can cause a system failure. The usual treatment of this problem is to design a synchroniser (most commonly a flip-flop), which has to take care of reliable communication between asynchronous subsystems. Therefore, the time a flip-flop needs to recover from a metastable stage (Fig. la) must be as small as possible. Synchronisers have already been the subject of some papers [1]-[6]. This paper deals with the design aspects and reliability of a synchroniser made in MOS technology.
C-MOS multiplier speeds task for microprocessors K. SMITH Electronics. 7E (April 1980). Chip can generate 16-bit product in 3ms; typical power consumption is 20row at 5V.
2.
Memories
A high speed 64 × 4 bit 100 K-compatible ECL-RAM ~ith 6 NS access time H. v. WITSCH and H. ERNST Fifth Solid State CircuitsConference- ESSCIRC 79, lEE Publn. 178, 102. The design of bipolar static memories is mainly tailored to attain a fast access time. In many applications, this access time contributes directly to the cycle time of the computer CPU. Therefore, for high-performance computers, the fastest memory components available are the obvious choice of the system designer. The organisation of the memory is an additional feature to be considered in optimising system performance. In our contribution, we discuss the design and performance of 64×4 bit ECL-RAM compatible with the ECL 100k logic family. This memory was developed for scratchpad and cache appIication in highperformance systems.
Simple process propels bipolar PROMs to 16-K density and beyond R. K. WALLACE and A. J. LEARN Electronics. I47 (March 1980). Double-level metalisation and polysilieon fuses guarantee dense highspeed memories and cleanly burned links that don't grow back.
3.
Hybrids
Thermal studies of a plastic dual-in-line package C. MITCHELL and H. M. BERG 1EEE Trans. Components, Hybrids Mfg Technology. Chmt-2(4), 500 (December 1979). The major factors affecting heat flow in a 16 pin plastic dual-in-line package (DIP) are investigated using thermal resistance measurements of packages with various materials and design permutations. Factors explored include the molding compound material, leadframe material and design, die size, wire size, and die bond material. Of these, the leadframe material and molding compound most dramatically impact 0].4 while the leadframe design plays a secondary role. Other factors are of minor importance. The user's external cooling conditions are very important to properly utilising a package's thermal capabilities. By optimising material selection in a standard 16 pin plastic DIP while using natural convection cooling, its thermal performance can be potentially increased by a factor of three. A factor of seven improvement is possible when using both optimum cooling conditions and superior packaging materials. Circuit-board packing considerations for optimum utilisatlon of chip carriers D. I. AMEY and J. W. BALDE IEEE Trans. Components, Hybrids Mfg Technology. Chmt-3(1), 105 (March 1980). Effective utilisation of large-scale integration (LSI) silicon technology requires efficient packaging of the non-LSI portions of the circuit. Low density hybrids of four to six chips can be packaged in the same chip carriers as the LSI chips. This not only offers minimal initial costs, but the best chance for subsequent cost redaction as silicon technology permits conversion of the hybrids to chip devices.
IBM multichip multilayer ceramic modules for LSI chips - design for performance and density B. T. CLARK and Y. M. HILL IEEE Trans. Components, ttybrids Mfg Technology. Chmt-3(1), 89 (March 1980). The design objectives and features of two modules are outlined which, with their LSI chips, give significant advantages of performance, power reduction, logic gate density, and reliability in their IBM 4300 processor applications. In these applications an average module gate density of 196 gates/cmz is achieved. This is 30 times the density achieved in IBM's monolithic systems technology (MST). Even larger density improvements are realised at the card level. A ULA is more than silicon J. A. VERNON, N. R. CROCKER and J. P. SINGLETON
Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Publn. 178, 51. For many years now the computer indhstry has been building systems with a large number of printed circuit boards which may contain many hundreds of gates. These boards have been well supported by Design Automation in the areas of coding, electrical loading rules, automatic tracking, logic simulation and automatic test pattern generation. Since LSI offers the advantages of cost, performance and reliability, how should the LSI be structured to take full advantage of Design Automation? The LSI parts must also have a short development time and hence low development cost, be error free and have a fast turnround from the logic diagram to the samples. It is the purpose of this paper to show that these objectives for LSI can be achieved by using the Uncommitted Logic Array, ULA approach to LSI design.. VLSI directions and impact B. T. M U R P H Y
Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Publn. 178, 70. The roots of VLSI technology are embedded in the fertile soll of the silicon transistor technology of the 1950s. In fact, the conjunction of the 'printable' transistor and the digital computer may prove to have been one of the most profound events in history. Its impact on our lifestyle has already reached major proportions. The symbol of the engineer is no longer the slide rule - it is the computer terminal. Society in general has been in a state of future shock over the ever more pervasive influence of transistor intelligence. The full implications of even state-of-the-art technology will take another decade or so to work out. The printed silicon transistor alone is capable of taking another few orders of magnitude further in VLSI chip performance. Small wonder that the awareness of changes coming from the impact of VLSI has now extended well beyond the ranks of engineers. Visions of the future conjured up by VLSI range from wrist watch computers through anthropomorphic robots to two dimensional 'brains' with the transistor as the cell. In this digest, I will deal with some general issues. In the talk itself, I plan to use this as a frame of reference for dealing with some specific topics in more detail.
1.2
MOS
ltigh density uncommitted arrays using an advanced CMOS technology W. T. ALEXANDER, S. J. BOARDMAN, P. KREBS and A. T. P. MacARTHUR Fifth Solid State Circuits Conference- ESSCIRC 79, IEE Publn. 178, 76. A CMOS Uncommitted Logic Array is presented based on a symmetrical cell design allowing connection efficiencies of over 90% and complexities of up to 800 gates. Each new circuit requires the design of only one interconnection mask, assisted by a cell library backed by decals. This gives short turn round times and few errors for custom and customer design. Furthermore, with a small investment, the design house can carry out the final commitment stage. Design aspects and reliability ofa synchronlser made in MOS technology H. J. M. VEENDRICK Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Publn. 178, 8. In asynchronous communication between digital systems signals may occur that are not logically defiined[1]. An example is a multimicroprocessor system of which the microprocessors do not share a common clock. This means that signals are 40
generated random in time. Especially it can happen that an input signal is changing during a sample clock edge. This situation can cause a system failure. The usual treatment of this problem is to design a synchroniser (most commonly a flip-flop), which has to take care of reliable communication between asynchronous subsystems. Therefore, the time a flip-flop needs to recover from a metastable stage (Fig. la) must be as small as possible. Synchronisers have already been the subject of some papers [1]-[6]. This paper deals with the design aspects and reliability of a synchroniser made in MOS technology.
C-MOS multiplier speeds task for microprocessors K. SMITH Electronics. 7E (April 1980). Chip can generate 16-bit product in 3ms; typical power consumption is 20row at 5V.
2.
Memories
A high speed 64 × 4 bit 100 K-compatible ECL-RAM ~ith 6 NS access time H. v. WITSCH and H. ERNST Fifth Solid State CircuitsConference- ESSCIRC 79, lEE Publn. 178, 102. The design of bipolar static memories is mainly tailored to attain a fast access time. In many applications, this access time contributes directly to the cycle time of the computer CPU. Therefore, for high-performance computers, the fastest memory components available are the obvious choice of the system designer. The organisation of the memory is an additional feature to be considered in optimising system performance. In our contribution, we discuss the design and performance of 64×4 bit ECL-RAM compatible with the ECL 100k logic family. This memory was developed for scratchpad and cache appIication in highperformance systems.
Simple process propels bipolar PROMs to 16-K density and beyond R. K. WALLACE and A. J. LEARN Electronics. I47 (March 1980). Double-level metalisation and polysilieon fuses guarantee dense highspeed memories and cleanly burned links that don't grow back.
3.
Hybrids
Thermal studies of a plastic dual-in-line package C. MITCHELL and H. M. BERG 1EEE Trans. Components, Hybrids Mfg Technology. Chmt-2(4), 500 (December 1979). The major factors affecting heat flow in a 16 pin plastic dual-in-line package (DIP) are investigated using thermal resistance measurements of packages with various materials and design permutations. Factors explored include the molding compound material, leadframe material and design, die size, wire size, and die bond material. Of these, the leadframe material and molding compound most dramatically impact 0].4 while the leadframe design plays a secondary role. Other factors are of minor importance. The user's external cooling conditions are very important to properly utilising a package's thermal capabilities. By optimising material selection in a standard 16 pin plastic DIP while using natural convection cooling, its thermal performance can be potentially increased by a factor of three. A factor of seven improvement is possible when using both optimum cooling conditions and superior packaging materials. Circuit-board packing considerations for optimum utilisatlon of chip carriers D. I. AMEY and J. W. BALDE IEEE Trans. Components, Hybrids Mfg Technology. Chmt-3(1), 105 (March 1980). Effective utilisation of large-scale integration (LSI) silicon technology requires efficient packaging of the non-LSI portions of the circuit. Low density hybrids of four to six chips can be packaged in the same chip carriers as the LSI chips. This not only offers minimal initial costs, but the best chance for subsequent cost redaction as silicon technology permits conversion of the hybrids to chip devices.