Electromigration challenges for advanced on-chip Cu interconnects

Microelectronics Reliability 54 (2014) 712–724

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Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel

Introductory Invited Paper

Electromigration challenges for advanced on-chip Cu interconnects Baozhen Li a,⇑, Cathryn Christiansen a, Dinesh Badami a, Chih-Chao Yang b a b

IBM Systems and Technology Group, Essex Junction, VT 05452, United States IBM Research Division, Albany, NY 12203, United States

a r t i c l e

i n f o

Article history: Received 3 January 2014 Accepted 6 January 2014 Available online 1 February 2014

a b s t r a c t As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures taken by the interconnect process development, circuit design and chip integration to overcome this challenge. While innovative process integration schemes, especially direct and indirect Cu/cap interface engineering, have proven effective to suppress Cu diffusion and enhance the EM performance, the strategies for circuit/chip designs to take advantage of specific layout and EM failure characteristics are equally important to ensure overall EM reliability and optimized performance. To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration. Ó 2014 Elsevier Ltd. All rights reserved.

1. Introduction Electromigration (EM) has been one of the major reliability concerns for ULSI circuit design and applications. With the aggressive technology scaling, the concern of EM reliability has attracted more attention from circuit and chip designers, interconnect developers, integrators and reliability engineers. Electromigration is a mass transport process due to electric current passing through a fine metal line. The momentum exchange between the current carrying electrons and the metal atoms results in the migrating of the metal atoms with the electrons. This causes the depletion of metal atoms at the cathode and the accumulation at the anode. As the semiconductor chip ages, the depletion of metal atoms at the cathode can lead to void formation and growth, and eventually to the interconnect resistance increase. When the resistance increases to a certain degree, it can decrease the chip performance and/or even cause malfunction. At the extreme, the void growth can result in the interconnect becoming completely impassible for electric current to cause open circuit failures. At the other end of the interconnect (the anode), the pile up of the metal atoms can lead to extrusion or hillocks, i.e., metal atoms being squeezed out of the metal lines, to cause short circuit to the neighboring lines. To prevent EM failures during product lifetime, semiconductor fabricators provide guidelines to circuit and chip designers to limit how much current each metal line and via can carry for a given product application (i.e. for a pre-defined operating temperature and lifetime). With the aggressive technology scaling, the electric current limit provided by the semiconductor fabricators keeps ⇑ Corresponding author. E-mail address: [email protected] (B. Li). 0026-2714/$ - see front matter Ó 2014 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2014.01.005

decreasing. On the other hand, to compete for performance and profitability, more compact chip designs are needed to provide faster speed and perform more complicated functions. This usually requires higher electric current limits for circuit and chip designs. The gap between the maximum allowed current limit and the current limit needed is rapidly growing, this is the so-called EM crisis for technology scaling [1–3]. In this paper, we will review why the EM lifetime decreases with technology scaling, and what actions have been taken to meet these challenges from all sides (semiconductor fabrication, circuit/chip design and product applications). In Section 2, we will discuss EM challenges from technology scaling on interconnect capability as well as from circuit and chip design demands. In Section 3, we will go through some of the interconnect integration schemes to make the advanced Cu interconnects more reliable for EM. In Section 4, we will review precautions and approaches taken by the circuit designers to make the circuits less prone to EM failures. In Section 5, we will discuss EM budgeting, checking and monitoring to manage the chip level EM reliability. Before concluding the paper, we will make a few general remarks in Section 6 on the future challenges and suggestions to integrate all efforts from fabricators, circuit and chip designers to meet these challenges.

2. EM challenges from technology scaling The overall EM challenges due to technology scaling come from the widening of the gap in current density limits for metal lines between the design needs and the technology capability. This issue was highlighted in the ITRS roadmap [3], as shown in Fig. 1. The current limit needed by the circuit/chip design increases rapidly from technology node to node, while the metallization process

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scaling aspects will aggravate the EM reliability will be discussed in the follows paragraphs. From the circuit/chip design side, to keep the performance scaling following the so called Moore’s law, on one hand, the circuits and chips need to be smaller in size, or aggressively shrinking in dimensions both horizontally and vertically. On the other hand, the operating voltage scales at a much slower rate. The current density to flowing through a metal line may be computed as follows [6]:

j¼

Fig. 1. Projected evolution of jmax (from device requirement) and JEM (from targeted lifetime from ITRS road map [3].

struggles to maintain the constant current carrying capability for the metal lines without invoking major innovations. The major driving forces for technology scaling include enhancing the chip performance and reducing the cost per device. Technology scaling includes physical scaling, material scaling, electrical scaling and new integration schemes. Physical scaling refers to dimensional shrink. One obvious benefit of the physical scaling is to allow smaller devices and denser designs (more devices per chip area). This is essential to packing more functions, and more importantly to have more chips per wafer. The technology scaling has a direct undesirable consequence – the increase of overall process cost. To counter this cost increase for processing, packing in more functions per chip and producing more chips per wafer allows the cost per function and the cost per chip to keep decreasing, though the cost per wafer may increase from technology node to node. Materials scaling refers to using materials which are more efficient or preferable for performance enhancement. One example from front end of line (FEOL) is to replace SiO2 based material with materials having higher dielectric constant (K), such as HfO2 based material for gate dielectric. In back end of line (BEOL), the latency from the interconnect RC effect has become a major contributor to the overall performance degradation. To lower the conductor resistance, the Al based metallization has been replaced with Cu based (higher electric conductivity) metallization since the 180nm technology node. Materials with lower K values have been introduced as inter- and intra- metal dielectrics (ILD) since the 130nm technology node to alleviate the interconnect capacitance effect. Electrical scaling refers to the operating voltage (VDD) and power reduction. Lowering the power at chip level has become a major desire for advanced applications. Lower VDD can directly result in lower power, lower electric field, and lower current, which has major benefits for time dependent dielectric breakdown (TDDB) and EM reliability. However, due to device leakage concerns, and driving for faster speed (performance), VDD has not been scaled as fast as the dimensional scaling. Integration scaling refers to the new integration schemes or innovations to enhance performance and pack more devices. This includes two very different integration aspects: (1) the interconnect fabrication/processing integration innovation driven by the scaling, which will be discussed in Section 3; and (2) chip or system level integration. The trend for the chip and system level integration scaling is growing from 2-D to 3-D schemes. The examples include adopting FinFets in FEOL [4], and chip stacking with through silicon vias (TSV) [5] for BEOL and packaging. Most of these scaling aspects are not in favor of the technology reliability, they bring various new reliability challenges. How these

CV DD fp WH

ð1Þ

where C stands for capacitance, W and H are the metal line width and height; VDD is the supply voltage to devices, f is the clock frequency and p is the device switching factor. Generally, W and H scale by a factor of 0.7, or the electric current conducting cross sectional area (W  H) reduces by about 50% from each technology node. For Cu interconnects, from 180nm node to 14nm node, the Cu cross sectional area for minimum width metal lines has reduced from 0.03 lm2 to 0.0015 lm2, a 95% reduction. On the other hand, the operating voltage (VDD) is only scaled down from 1.8 V to 0.9 V, a merely 50% reduction. The net effect is a 10 times increase of (VDD/ WH) ratio. Scaling for performance also drives higher and higher clock frequency f, and switching factor p. All these factors point to that higher and higher j is needed for circuit and chip design. In addition to the physical scaling (dimensional shrink), the material scaling impact on EM reliability can also be significant. There are two aspects of this impact – direct impact from the new material properties and the indirect impact from the process integration changes driven by accommodating the new material properties. Replacing Cu with Al gave a significant boost to the interconnect EM capability [7], due to Cu’s higher melting point (1083 °C vs 660 °C of Al) and higher EM activation energy (0.9 eV for Cu vs 0.8 eV for Al). However, the subsequent aggressive dimensional shrink from technology scaling has led to rapid EM performance degradation for Cu interconnects. This is because the decrease of the critical void volume to cause EM failure and the increase of the Cu drift velocity. EM failure time may be expressed as a function of the critical void volume and Cu drift velocity [8,9]:

tfail ¼

V critical smd

ð2Þ

where tfail is the time to EM failure. Vcritical is the critical void volume at the EM failure, it is related to (or approximately proportional to) metal line dimensions (W, H) and via size. s is the Cu diffusion cross sectional area, proportional to metal line width, W. md is the Cu drift velocity. Eq. (2) may be further approximated as:

tfail /

WH

md

ð3Þ

With constant md, tfail should decrease 50% for each technology node when W and H each shrinks by a factor of 0.7. However, with minimum line width, W, scales to <100nm (beyond 65nm technology node), the Cu gain size changes from bamboo type dominated structures to mixtures of bamboo and polycrystalline structures [9,10], as shown in Fig. 2. Fewer bamboo type grains exist with smaller line width dimensions. This grain structure change results in the increase of Cu mass flow rate (Nmd, N is the atomic density). For Cu lines with bamboo-like structures, the EM failure time was dominated by the Cu drift along the interface between Cu top surface and the dielectric cap layer. The presence of the polycrystalline structures introduces additional fast Cu drift paths along the grain boundaries (GB). Fig. 3 shows the trend of median EM failure time (t50) variation with technology scaling. The actual t50 does not follow the predicted trend exactly. This is because the process

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(a) Ideal Bamboo structure

(b) Bamboo dominated structure

(c) Polycrystalline dominated structure

(d) An TEM cross section showing polycrystalline dominated structures of a 50nm wide Cu line Fig. 2. Schematic illustration of Cu grain size distribution evolution with technology scaling. Finer grains in the Cu lines for newer technologies.

Fig. 3. The normalized median EM failure time (t50) evolution with technology scaling – approximately 50% degradation for each technology node scaling.

integration scheme and material changes accompanying the technology scaling. For instance, from 180nm to 130nm, the actual EM failure time did not decrease much, because the cap layer deposition condition modifications. The EM challenges with technology scaling may be further illustrated through the jmax variation. To quantify the metallization EM resistance and provide a definitive guideline to circuit designers, a number of merit, jmax, (some time also called Juse) is defined as below [11]:

jmax

 i  1 h 1  1 t 50stress ðnÞ ZnrþDnkH T use T Stress ¼ jstress e t lifetime

ð4Þ

where jstress and Tstress are the stress current density and temperature (in K); tlifetime and Tuse are the target product lifetime (in power on hours, POH) and use (or junction) temperature (in K). Z is the Z-score, determined by the cumulative failure probability (CDF) at tlifetime. t50stress is the median failure time of samples at stress conditions and r is the standard deviation of the lognormal distribution of the EM failure times. n is a constant for electric current density acceleration, and DH is the activation energy for the thermal acceleration of EM. k is Boltzmann’s constant. During technology qualification, various via/line constructs are stressed with both electric current and temperature accelerations to generate t50stress and r. Representative via/line constructs are then selected to characterize the EM behavior at different stress conditions (jstress and Tstress) to derive the two EM acceleration constants, n and DH. Details of the EM stress and characterization procedures are given in

JEDEC standards [11]. Other than the stress condition values (they are also adjusted with technology scaling), most of the parameters in Eq. (4) are affected by technology scaling, and subsequently pass these impacts to the jmax value derivation. As discussed above, under the same stress conditions, t50stress can decrease by 50% from technology node to node, corresponding to a 30–50% jmax decrease if other parameters keep unchanged. Variability is one of the major concerns for technology scaling, especially with the dimensional shrink. The smaller line and via dimensions aggravate the challenges of within a chip and cross a wafer uniformity, in dimensions, Cu fill quality and grain structure characteristics. Wider variation (or non-uniformity) leads to broader EM failure time distributions, and is reflected by the increase in r value of Eq. (4). Fig. 4 shows the impact of r variation on jmax. The typical r values of 0.3–0.4 were observed in the 90nm - 65nm technology nodes. While r values of 0.4–0.5 became more typical for 32nm - 22nm technology nodes. This variability increases alone can cause 70% of jmax degradation if r increases from 0.3 to 0. 5. If r increases from 0.4 to 1.0, to project to the same jmax, the median EM failure time needs to increase by a factor of 100 to compensate this r degradation. The maximum allowed use current density, jmax is a very sensitive function of the EM activation energy (DH) as well. Similar to the discussions on the technology scaling impact on the Cu drift velocity, md, smaller line dimensions can cause the decrease of the EM activation energy. Major efforts have been made to enhance the EM activation energy through innovative process integrations. Owing to its importance, this topic will be further discussed in Section 3. Another technology scaling impact is on the metal line temperature T (Tuse in Eq. (4)). The actual metal line temperature Tuse may differ from the nominal junction temperature at use conditions if there is joule heating in the metal line itself or in the neighboring lines. In addition to the increase in power and current density, the material and physical scaling can also result in more joule heating in the metal lines [12]. First, the Cu resistivity increases rapidly with dimensional shrink when the Cu line dimension scales close to or below the Cu electron mean free path due to the surface and grain boundary scattering [10]. In fact, the rapid Cu resistivity increase has become one of the bottle necks for technology scaling. Fig. 5 exhibits the Cu resistivity impact on the line temperature rise due to joule heating at various current densities. For 90–65nm technology nodes, the typical Cu electric resistivity is in the range of 2–2.3 lX cm, while it increases to >4 lX cm for 14nm node [10]. Furthermore, the material scaling by using lower K materials as ILD also aggravates the joule heating effect. Generally the dielectric materials with lower K have lower thermal conductivity. Fig. 6 shows the joule heating caused temperature rise variation with ILD thermal conductivity. For fluorine doped SiO2 ILD, the effective

Fig. 4. Variability (r) impact on EM performance. The solid line is for a constant projected jmax target.

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A

B

D

C

E F

Fig. 5. An example of Cu resistivity impact on joule heating and lifetime degradation for a metal line of 0.5 lm wide, 0.2 lm tall embedded in a dielectric with effective thermal conductivity of 0.59 W/m K. The resistivity ratio for A, B and C as 0.2:0.3:0.4.

thermal conductance is >1 W/m K, while for porous organic ILD, the effective thermal conductivity can be as low as 0.32 W/m K [13]. The joule heating effect on EM reliability may not be as straightforward as shown in Figs. 5 and 6. First, for the narrow metal lines, the allowed Irms (root mean square current) and jmax may not cause any significant joule heating to itself, however, the thermal interaction of the tightly packed signal and power lines can have a significant impact on the metal line temperature. This issue will be further discussed later in Section 5. In Eq. (4), Z is the measure of how many via/line connections designed close to, at and above the jmax limits [14]. The technology scaling can result in negative feedback between jmax and Z. The lower jmax may force the designers to have more via/line elements run closer, at or above the jmax to result in higher Z and degrade the chip level EM reliability. The effect of Z in Eq. (4) will be discussed in details in Section 5. Other factors not apparent in Eq. (4) include the Blech effect [15]. The Blech effect refers to the phenomenon that the shorter metal lines have longer EM lifetime than long lines at same current density and temperature, when the line length falls in the range that the backflow stress can effectively slow down the Cu migration. Taking advantage of the Blech effect, i.e. using short interconnects wherever possible, has been one of the effective measures in circuit design to counter the jmax decrease with technology scaling. However, as the aggressive shrink of line and via dimensions with the technology scaling, the Blech effect becomes weaker and may completely diminish beyond 10nm or 7nm technology nodes projected by Oates [16], based on two major factors. Firstly, technology scaling leads to thinner liners at trench and via sidewalls and bottom, resulting in smaller backflow stresses. Secondly, smaller via/line dimensions lead to larger relative variations, and smaller critical void size to cause EM failures. The net result will be much shallower EM failure time distributions. Though the lifetime is longer for the shorter lines at high percentiles of the EM failure time distributions, the failure times approach to that of the long metal lines at low percentiles. Since these early fails at low percentiles are the dominating EM reliability concerns, it may become harder to predict EM benefit for the shorter lines at future technology nodes. To summarize, the gap between the maximum allowed current density and that of circuit design needs is widening with the technology scaling. Higher current densities are needed to keep the performance scaling following the Moore’s law. The decrease in current carrying capability of metal lines/vias due to EM concerns results from (1) critical void volume reduction due to dimensional scaling; (2) fast Cu mass flow due to the grain structure change from bamboo like dominated to polycrystalline dominated; and (3) integration scheme changes driven by material scaling. In the following sessions, we will discuss, on one hand, how to enhance the metal line/via EM resistance through process integration

Fig. 6. An example of dielectric thermal conductivity impact on joule heating and lifetime degradation for a metal line of 0.5 lm wide, 0.2 lm. The effective dielectric thermal conductivity for D, E and F is 1.0, 0.59 and 0.32 W/m K respectively.

innovation; and on the other hand, how to minimize the product EM risk through innovative circuit and chip designs. 3. Process integration innovations for interconnect EM reliability In the past decades, extensive activities have been published on how to make reliable interconnects for advanced semiconductor chips [2,17]. To overcome the negative impact on the interconnect EM capability from technology scaling, various innovations in the metallization integration schemes were developed. In this section, we will focus on the Cu/cap interface engineering and liner modifications. The heart of the EM enhancement is to slow down the Cu transport (mass flow) along the fast path in the interconnect. There are many ways known to be effective to slow down the Cu diffusion, however, the following trade-offs will have to be considered when deciding if they can be actually implemented in the process integration: (1) the impact on Cu resistivity; (2) the compatibility with the existing metallization material sets and integration schemes; (3) manufacturing cost and management; and (4) impact on other reliability failure mechanisms, such as ILD TDDB and stress migration (SM). As discussed in the previous section, rapid Cu resistivity increase due to physical scaling will become a major limiting factor for performance scaling. Unfortunately, most of the measures to suppress Cu diffusivity also lead to higher Cu resistivity. Minimizing the Cu electric resistivity increase is one of the primary considerations for process integration scheme selections. 3.1. Fast Cu mass transport path The Cu migration leading to EM failures can be characterized by the Cu drift velocity through the Nernst – Einstein equation [15]:

md ¼

  D0;eff DH  Dr e kT Z eqj  X kT DL

ð5Þ

The first term in the parentheses of Eq. (5) is the EM driving force involving the mobile species’ effective charge (Z ⁄ e) and the current density (j). The second term in the parentheses is the backflow stress gradient due to Cu accumulation at the anode. The term outside the parentheses in Eq. (5) is the effective Cu diffusivity involving thermal acceleration (activation energy DH and thermal energy kT). The process integration has very little control over the EM driving force term, it is primarily determined by the circuit design and applications. Though the process integration has some means to modify the backflow stress gradient term by using stronger ILD and thicker liner, these approaches are often not compatible with the technology scaling for RC reduction. That leaves the Cu diffusivity term as the only parameter for the process integration to manipulate. To be more specific, getting lower D0,eff and higher DH are the

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focuses of process integration for EM performance improvement. There are a few paths for Cu to diffuse from cathode to anode during EM process: through Cu surfaces at the Cu/Cap interface or at the Cu/liner interface, through Cu grain boundaries, or through the bulk of the Cu grains, as shown in Fig. 7. For the Cu lines dominated by bamboo like grain structures, the fast Cu diffusion path during EM was determined to be along the Cu and the dielectric cap interface [18]. Most of the process integration efforts in the last a few years have been focused on strengthening the Cu/cap interface to reduce the Cu drift velocity, md. 3.2. Cu/cap interface engineering The advantage of Cu/cap interface engineering is two fold, slowing down the Cu diffusion along the fast path while minimizing the impact on Cu resistivity. Ideally, the material used for Cu surface modification should be stable and stay at the Cu top surface only. The deeper the modification material penetrates into the bulk Cu, the more impact will it have on the Cu resistivity. The Cu/cap interface modification can be done directly on the Cu top surface, or indirectly, i.e. via intermediate process steps. A few examples are given in the following sessions. 3.2.1. Direct Cu/cap interface modification There are a few ways to directly modify the Cu top surface to strengthening the Cu/cap interface and slow down the Cu migration. In the earlier stages of Cu interconnect development, the most popular method was to conduct aggressive Cu surface cleaning with H2 or NH3 before cap layer deposition [19]. While this can be effective to improve the Cu EM performance, it can also cause severe damage to the Cu surface and often deep into the Cu bulk to cause significant Cu resistivity increase and sometimes, even a negative effect on stress migration. With the introduction of porous low K ILD materials into the advanced interconnect stack, the aggressive Cu surface cleaning before cap deposition was further limited to avoid the damage on the low K dielectric surface. The next approach is to coat a thin layer of metallic film on top of the Cu surface. In addition to being effective to substantially slow down or virtually stop the Cu diffusion, other basic requirements for this thin metallic film coating include (1) being stable, that is, staying where it is deposited, not diffusing into the bulk Cu to cause further Cu resistivity increase, or agglomerating to become non-continuous film; (2) having very low or no solubility in Cu, and having very low potential to form compound with Cu; (3) a selective deposition method is readily available. Ideally, it should only be deposited on Cu surface, not on the dielectric surface. If it is deposited on dielectric surface, it should be very easy to be

Cap Layer

cleaned off without affecting the film quality on the Cu surface. And finally, it should be compatible with the main dual damascene Cu integration process and the existing material sets. These requirements narrow down the material selection to only a few elements. The most popular one is the Co based metallic films. CoWP was identified as a good candidate for direct interface engineering [20]. A fairly thin layer of CoWP (1–10nm) can be selectively deposited on Cu surface using a wet process, and the residues on the ILD surface can be cleaned off relatively easily. Fig. 8 shows that a thin layer of CoWP at the Cu/cap interface can extend the EM failure time for >100 times. The EM activation energy can be increased from 0.9 eV to above 1.4 eV [21]. In fact, it is so effective that for the samples with good base line integration process and blocking bamboo grains, it is very hard to stress them to fail even under very highly accelerated EM stress conditions. One of the disadvantages using CoWP is the wet deposition to add process complexities. Though the process has been developed for more than a decade, it has yet to become a popular choice for mass production. Another example is coating a thin layer of pure Co on Cu surface. This can be done via a chemical vapor deposition (CVD) method [22,23]. Fig. 9 is an example of EM performance enhancement using a thin CVD Co layer at the Cu and dielectric cap interface [23]. The CVD co cap can enhance the EM lifetime by 5 to >100 times, depending on the Co thickness and process details. 3.2.2. Indirect Cu/cap interface modification A typical example of indirect Cu/cap interface engineering is doping Cu seed layer with alloy elements, such as Mn or Al. The Cu/cap interface modification or strengthening relies on the dopant segregating to and then staying at the top Cu surface. This dopant diffusion or segregation control is critical for the process to be effective for Cu EM performance enhancement. First, the process conditions need to be right to drive the dopant, such as Mn, diffusing to the top surface of Cu, rather than diffusing to the Cu/liner interface or staying in the seed layer. Secondly, the dopant should arrive at the Cu top surface after the pre-clean of the Cu surface before cap deposition to avoid the dopants being removed from cleaning. The belief is that during the high temperature cap deposition process, higher oxygen potential and point defect concentration at the Cu top surface drives the dopants (Mn or Al) to the Cu top surface [24]. Fig. 10 gives an example of Cu EM performance improvement with the Mn doped seed layer. Though the Mn is doped in the Cu seed layer, Fig. 11 clearly shows that Mn segregated on the Cu top surface [25]. 3.2.3. Comparison of direct vs indirect Cu/cap interface modification While both direct and indirect Cu/cap interface modifications can achieve significant EM performance enhancement, there are

Grain Boundary CoWP Cu

> 100x

e- flow direction: left to right

Liner

diffusion along Cu/cap interface diffusion along grain boundaries diffusion across grain bulk diffusion along Cu/liner interface Fig. 7. Schematic illustration of Cu diffusion/migration paths in Cu lines.

Fig. 8. An example of EM performance improvement with CoWP on top of Cu surface. Symbols: A & C without CoWP, B & D with CoWP. A & B for V1 ? M2 and C & D for V2 ? M2 electron flow directions.

B. Li et al. / Microelectronics Reliability 54 (2014) 712–724

CVD Co Cu

Fig. 9. An example of EM performance enhancement by CVD Co on top of Cu surface. A – No Co. B, C and D with different Co thickness (B < C < D).

>10x

Fig. 10. An example of EM performance improvement with doping Mn into Cu seed. Symbols: A & C without Mn doping, B & D with Mn doping. A & B for V1 ? M2 and C & D for V2 ? M2 electrons flowing direction.

Cu Mn Si O N

Counts

10

717

as CoWP and Co, is a true surface modifier. They virtually do not diffuse down into the Cu. Though they are very effective to suppress the Cu diffusion along the Cu/cap interface, they have low tolerance to the baseline defects, such as poor liner coverage. On the other hand, for the indirect modification, such as Mn-doped Cu seed, though it may not be as effective as CoWP to suppress the Cu surface diffusion, it can better accommodate some of the baseline defects. One example is given in Fig. 12 [25], showing that Mn can actually patch some of the liner defects. Due to the higher oxygen potential at the liner defect areas, some of the doped Mn in the seed segregated to those places to act almost like a self formed barrier. To further illustrate this difference, Fig. 13 shows the comparison of EM performance enhancement difference for via and line depletion mode and baseline sensitivity. The Cu/cap interface modified directly by a thin layer of CoWP is much more sensitive to the baseline health. Thirdly, the direct Cu/cap interface modification relies on the selectivity of the deposition process to deposit the modification layer only on the Cu surface, however, some residues or deposits on the dielectric surface between Cu lines are not completely avoidable. A post-deposition clean is needed to prevent line to line shorting or TDDB issues. For indirect Cu/cap interface modification, a special cleaning process is not needed to prevent shorting or TDDB issues. Another difference between the two Cu/cap interface modification methods is the EM failure time distribution shape factor (r). As discussed in section 2, r is an important factor when projecting to low failure targets. Comparing Figs. 8–10 and 13, the failure time distributions with CoWP tend to have much higher r than those for CuMn. This difference was believed resulting from the different effect on Cu mass flow via grain boundaries. Since CoWP was deposited at the Cu surface and then stayed there, it had virtually no impact on Cu diffusion along grain boundaries. Due to the distribution of polycrystalline and bamboo like grains in the metal line, the large difference in effective Cu diffusion in the bamboo grain region and in the polycrystalline region can result in shallow failure time distributions with CoWP, as discussed in Refs. [26,27]. It was believed that some low concentration Mn might have diffused to the Cu gain boundaries and caused some Cu diffusion suppression along the grain boundaries as well [28,29]. Combining with its less effectiveness in suppressing Cu diffusion along the Cu surface, less r degradation was expected with CuMn.

5

3.3. Liner coverage improvement

0 0.000

0.005

0.010

0.015

0.020

0.025

0.030

Position (um)

Mn Cu

Cu

Fig. 11. An example of Mn profile on Cu surface. The top plot shows the elemental concentration distribution across the cap/Cu interface. The bottom plot highlights segregation of Mn on Cu top surface.

some differences in the details of EM performance improvements. Firstly, from process simplicity point of view, the indirect Cu/cap interface modification does not need to add any extra process steps or new tools. The only change is to replace the pure Cu seed target with an alloy doped (for instance, Mn-doped or Al-doped) target. The direct Cu/cap interface modifications with either CoWP or CVD Co all need extra process steps and tools. Secondly, for the direct modification, the thin layer deposited on Cu surface, such

Though Cu migration along the interface between Cu and well deposited TaN/Ta liner is believed much slower than that along the Cu/dielectric cap interface, liner quality is also extremely important for EM behavior. First, good liner is essential for good Cu fill in the trench and vias to minimize the pre-existing defect or voids. Good liner coverage in the trench and via sidewalls can also provide redundancy for electric current flow after cross line voids are formed. Furthermore, the liner at the via bottom can serve as a blocking layer for Cu diffusion which can be very important when the Blech effect is needed for circuit designs. Two EM failure modes were often seen from dual damascene Cu interconnect – weak (or early fail) mode with void in or under the via and strong mode with void in the trench away from via [30,31]. Liner quality and characteristics in the via are critical factors to modulate or improve the weak mode. For line depletion EM, i.e. when electrons flow from a via down to a metal line, the weak failure mode is often observed as being caused by thin slit void underneath the via, characterized with sudden open circuit failures, i.e. showing no gradual electric resistance increase during EM stress. It has been found difficult to completely remove this failure mode, but with appropriate integration process, the weak mode failure time can be extended. One way is to ensure good

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Cu

Liner Defect

Cu: Red Mn: Green O: Blue Fig. 12. An example of Mn doped Cu line showing Mn accumulation at the liner defect area to patch the liner defect there [25].

(a) - CoWP

(b) - Cu(Mn)

Fig. 13. EM performance enhancement comparison for via depletion and line depletion. A & B for via depletion (electrons flow: V1 ? M2); C & D for line depletion (electrons flow: V2 ? M2). A & C for base line process I and B and D for base line process II.

electric contact between the via bottom liner to line sidewall liner below. This will allow the void to grow deeper and a period of gradual resistance increase before open circuit failure occurs [32]. The other ways to improve the weak mode of the line depletion EM failure include minimizing the damage on the Cu during via opening [30], and making the via gouge into a certain depth of the line below [33]. For via depletion EM, i.e. when electrons flow from a via up to a metal line, the weak mode was often observed as thin void formed within the via either at the via bottom [34–36], or at the mid height of the via [31] near the chamfering area. The common cause for these fails was the poor liner coverage in those areas. For later technologies, via chamfering and liner etch back process were often applied. Due to the surface roughness and the angle at the via chamfering area, the liner is usually thin, or sometimes even not continuous there, which forms the preferred spots for void nucleation. The weak mode can be removed from the failure time distribution with improved liner deposition processes. As will be discussed in the next section, taking advantage of the Blech effect (often referred as the short length effect) has been one of the measures taken by the circuit designs. Since all current conducting nets are connected with vias to levels above or below, the via bottom liner constitutes as the physical barrier to define line lengths in the sense of Cu diffusion, that allows the backflow stress building up. As the technology scales down, the via resistance increase has become one of the factors impacting the circuit performance. The via bottom liner is a major contributor to the high via resistance, and thinning it down has been the scaling trend. The concern with very thin, or even non-continuous liner

at via bottom is the permeability to Cu diffusion [34,37,38]. Fig. 14 gives examples of EM failure time distributions for different liner processes and Fig. 15 shows the corresponding resistance increase characteristics during EM stress [34]. Due to the design feature of the testing structure with a very wide feeding line, the EM for the liner permeable to Cu diffusion becomes ‘‘immortal’’, that is, a constant Cu mass flows through the via bottom liner to prevent void formation in the via to result in EM failures. Since a vast volume of Cu exists in the feeding line, the void needed to cause an observable resistance increase in the feeding line is huge. In actual circuit designs, the feeding line could be a very small line/ via segment, and a very small void is needed in the feeding line to cause an EM failure. To prove that those ‘‘immortal’’ samples indeed were the results of the Cu diffusion through the permeable liner at the via bottom, a thin layer of CoWP was coated on the surface of the feeding line only to suppress the Cu supply into the via. As shown in Figs. 14 and 15, the immortal portion in ‘‘B’’ now becomes the early fail portion in ‘‘A’’, after the constant Cu flow from the feeding line into the via is substantially eliminated by CowP. The non-blocking liner to Cu diffusion at via bottom is detrimental to Blech effect, since permeable liner cannot now effectively separate the lines into short segments [34]. 3.4. Overall integration improvement The EM damage may be considered to take place in two steps: void nucleation and growth. Local process defects can serve as Cu diffusion divergence sites or preferred void nucleation sites. These defects can cause early EM fails which do not follow the

B. Li et al. / Microelectronics Reliability 54 (2014) 712–724

719

99.9

Percentile

99

A – Process 1 B – Process 2

Strong mode

90

Weak mode

50

A A AA A A A A A

10 1

A A A A A A AA A AA B B B B B B B

Time, A.U Fig. 14. An example of the impact of permeable via bottom liner to EM failure time distributions [34]. ‘‘B’’: a constant Cu flow from feeding line through the via bottom liner into the via. ‘‘A’’: the Cu flow in the feeding line was suppressed by CoWP.

Resistance

1000

(b)

(a)

900

Fig. 16. An example of process integration optimization to improve EM failure time distributions. Process 2 reduced the Cu fill defects in the line and resulted in much improved EM failure time distributions over process 1.

800

“immortal”

700 600 500 10

20

30

Time, A.U

40

50

50

100

150

200

Time, A.U

Fig. 15. Resistance variation with stress time for the 2 cases in Fig. 14. Plot(a) is for case ‘‘A’’ and (b) for ‘‘B’’ in Fig. 14.

main EM failure time distributions, as discussed in Ref. [30]. More severe defects can even form extra Cu migration paths, to significantly reduce overall EM failure times. Any process step that minimizes the defectivity in Cu line and via can result in better EM performance. Fig. 16 shows an example of EM failure time distribution improvement for a Cu interconnect from the improvement of Cu plating recipes. In this example, the plating recipe in process 2 improved the Cu fill quality, and eliminated the early EM fails seen from process 1. Again, this demonstrates that a healthier baseline is critical to improve the EM failure time distribution and performance. While various integration schemes have proven that they each can improve the advanced Cu interconnect EM performance, the overall interconnect (via/line) health is essential, not only to improve the base line (pure Cu) EM performance, but also to make those EM enhancing integration schemes (direct or indirect interface engineering) more effective. Fig. 17 gives one example how the overall integration process can make the interface engineering (CoWP for Fig. 17) more effective. In this example, the overall integration improvement can produce an accumulated EM performance enhancement by >50. To summarize, to counter the EM performance decrease caused by technology scaling, various integration schemes have been developed. The most commonly adopted approach has been Cu/ cap interface modification. While these modifications are proven effective, the health of the base line is critical to ensure their effectiveness be optimized. 4. EM aware designs for circuit level reliability To pass more current through a metal line, the obvious options would be using wider metal lines, or enhancing the current density or both. Using wider metal lines goes the opposite direction as the technology scaling, it will cause circuit and/or chip size expansion, rather than shrink. As discussed in the previous section, the

Fig. 17. An example of overall integration process improvement to make the CoWP more effective to suppress Cu electromigration.

process and integration issues resulting from technology scaling may prevent enhancing the maximum current density allowed passing through the metal lines in order to maintain the product reliability target. While the innovative process and integration schemes are actively pursued to increase the interconnect current carrying capabilities by the chip fabricators, various creative design approaches have been taken by the circuit and chip designers to ease the EM burden on the interconnects. In this section, we will highlight a few of such circuit design strategies. In the era of striking for full circuit design automation, it is important to incorporate EM aware circuit design strategies in the design, checking and verification tools. Not all circuits have EM concerns and not all the circuits with EM concerns are critical. It is imperative for the electronic design automation (EDA) tools to be able to recognize and identify those circuits with critical EM implementations. In reality, this task is so complicated, none of the existing EDA tools can perform and optimize EM analysis on all the layouts and connections. To take more advantage of different layouts with different EM benefits, it often needs human intervention to avoid having too aggressive designs or keeping too much EM margins by the EDA tools. 4.1. Narrow/wide line combinations As discussed in Section 3, technology scaling has resulted in different grain structure evolution in the narrow Cu lines from bamboo like dominated structures to polycrystalline dominated structures. This grain structure change renders the narrow lines with higher Cu mass flow rate, and lower maximum allowed current density than the wider lines. The lower current carrying capability of the narrow lines put severe challenges on the designs

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of high power circuits, such as high speed inverters and buffers. It forces to limit the utilization of the narrow lines to only in size sensitive cells or in the circuits requiring low DC current, and to transition to wider wires whenever possible. Hau-Riege and Klein [39] studied the EM failure characteristics when transitioning from a narrow wire to a wide wire or vice versa. The failure times were found typically following bimodal distributions, with the early mode mimicking the narrow line characteristics and the late mode following the wide line features. The ratio between the early failure mode and late failure mode was affected by the length ratio between the wide and narrow segments. This observation provides a guidance for circuit designs using narrow line in the cell and then transitioning to wide lines to connect outside the cell.

4.2. Redundancy benefits for critical circuits The vias have been recognized as the weakest link for interconnect reliability. Most early EM failures are associated with vias, with void either in the via or underneath the via, depending on the electron flow direction. This is especially true for the connections with a single via. The situation can be improved dramatically when redundant vias are used [32]. Recommendations are usually provided in the design guidelines to apply redundant vias wherever possible. However, for the advanced technologies, the minimum required via to via spacing does not always scale with the via size and line width. To maintain the design track density scaling, the metal lines may not be wide enough to accommodate multiple vias along the line width. One of the solutions for this problem is to offer multiple via size options in addition to the regular square via, like large square via and rectangular bar via. In lieu of the redundant vias, large or bar vias can be used to enhance the EM reliability, as shown in Fig. 18. While the large and bar via options are very helpful and efficient for circuit designs with better reliability and scaling, they also bring in challenges and complexities to the manufacturing process control. Instead of optimizing the integration process window to single size via, now a balance is needed for all via sizes. Applying redundant vias wherever possible is certainly a good circuit design practice, how to arrange those redundant vias can also impact the circuit EM reliability. We reported the effect of different via arrangements on EM failure characteristics in Refs. [32,40], including redundant vias aligning along the line length vs along the line width, different via arrays, vias with and without contact with the line liner below. In general, any arrangement that will result in larger critical void volume to fail will lead to longer EM failure times. For instance, aligning the 2-via row along the line

Fig. 18. EM performance variation with different via sizes. A – 2 regular square vias along line width; B – 1 rectangular bar via with 2 the cross sectional area of a regular square via; C – 1 larger square via with 4 the cross sectional area of a regular square via.

length has shown resulting in longer EM failure times than aligning the 2-via row along the line width, when connecting to lines just wide enough to allow 2 parallel vias along the line width. Another observation is that a good contact between the via bottom and the line liner below is in general a good practice for minimizing the sudden open circuit failures, but it may not necessarily extend the overall failure times depending on the current density and the number of vias and line width, and via/line contact arrangement. However, considering the line/via critical dimensional and alignment control variations, the interconnect fabricators may require designs to set the vias within the line for a certain range to make the vias fully landed on the metal below. In addition to the redundant vias, some circuits are naturally having heavy redundancies, such as power grids, and local device connections with fingers [41,42]. Such heavily redundant circuits not only can carry much higher current, but also can tolerate higher EM failure probability per critical feature. Due to the nature of the networking in these circuits, electric resistance increase in any given knot or finger caused by EM will result in current redistribution and EM process rate reduction from that knot or finger. From a practical application point of view, such heavily redundant circuits can tolerate one, two or more connections from EM failure without impacting the chip normal operations. Taking advantage of these features can be important for circuit designs. 4.3. Short length benefits Another important factor to increase the interconnect current carrying capability is to take advantage of the short length benefit. From Eq. (5) in Section 3, as the EM process proceeds, a higher and higher backflow stress gradient (X DDrL ) will be built up at the anode to slow down the Cu drift rate, md. When this backflow stress gradient becomes sufficiently high, it can completely balance the driving force (Z  eqj), and makes the net Cu mass flow to zero. At this steady state, Eq. (5) can be rewritten as:

ðjLÞc ¼

XDr Z  eq

ð6Þ

(jL)c is called the threshold jL product [15]. In theory, if the jL in the interconnect is below the threshold product (jL)c, the interconnect should not suffer EM damage. Even when the jL product is somewhat higher than (jL)c, the EM damage can occur but with longer time to fail, based on the following modified Black equation [43]:

MMTF ¼

A DH e KT ðj  jc Þ

ð7Þ

where MMTF is the median time to fail (i.e. t50), A is a geometry and material related constant, jc is the threshold current density from Eq. (6), and the rest have the usual meanings as described for Eq. (4). Eqs. (6) and (7) serve as the basis why shorter lines can have higher maximum allowed current densities. Taking advantage of this feature, i.e. making short interconnections, has proven powerful in circuit design to solve some of the EM challenges. Another advantage of utilizing short length benefit for EM is the low temperature sensitivity [44]. If some devices are known having high power, high frequency and high activity factors, the local interconnect temperature has a potential to be much higher than the nominal junction temperature due to joule heating. As shown in Eqs. (4) and (7), the maximum allowed current density decreases exponentially with the interconnect temperature for the regular EM process. A severe jmax de-rating may be needed for such circuits to account for the local temperature rise. Using wider metal lines, which only increase the current linearly with line width, may not provide sufficient relief to compensate for the jmax de-rating. Under such circumstances, taking advantage of the short

B. Li et al. / Microelectronics Reliability 54 (2014) 712–724

length benefit becomes essential to overcome the local high temperature issues. Since (jL)c has very low sensitivity to temperature [44], as long as the jL is sufficiently below (jL)c, the EM reliability will not decrease much with the local joule heating. Breaking the long interconnect into short segments to take advantage of the short length benefit may not always be feasible due to spacing limitations and resistance sensitivity. To allow the backflow stress to build, physical barriers at both cathode and anode of the interconnect is required. There are alternative ways to establish some pseudo-barriers to enable local backflow stress build up, and form some short length effects [45,46]. One example is to have blocking islands on top of a metal line or using multiple levels of metal lines with period of vias or bar vias connecting them, as shown in Fig. 19 [45]. Those blocks on the Cu surface may not create a complete physical barrier for Cu diffusion, since they have a direct metal to metal interface in the blocking islands, the Cu diffusion along those local interface areas will be much slower, and some degree of backflow stress gradient will be built up to create partial short length effects. One of the major challenges for short length EM benefit applications is the line length definition [45]. Actual circuits are often more complicated than the simple metal line segment with vias at each end. They often have fingers, branches/wings, passive reservoirs, passing vias, dropdowns, width transitions, etc. In such cases, what line length and (jL)c to use for the short length benefit calculations become very challenging, not only to the EDA tools, but also for the design engineers. Appropriate engineering judgments are often sought to solve these issues. As stated in earlier sections, the short length effect is deteriorating with technology scaling [16]. Due to the variability control and the liner thinning, lower (jL)c values are expected for the future technologies. Furthermore, the distribution complexity should be closely watched as well when applying short length benefits for circuit designs.

4.4. EM repair and refueling The previous sessions have focused on the EM aware circuit design through physical layouts to incorporate different EM characteristics. There are also many innovative approaches to control potential EM damages through workload management. Workload management through sharing and rebalancing the activities can be implemented at the chip or system level. This usually requires spare or redundant circuits or functional blocks. The basic idea is that through on-line monitoring the system activities or simply by accumulated operation hours, reassign the workloads/activities from those circuits or functional blocks that have been heavily utilized to those less utilized.

A

Percentile

90 No fail for G after 950hrs stress

No fail for H after 650 hrs stress

50

10

A F A F

FF FF F F

F

FFF

G

I

H

500

I

I

1 100

Failure Time, hrs Fig. 19. Line and via layout impacts on Blech effect and EM performance [45]. The arrows indicate the electron flow directions. The green square at the right represents via below the line, and the brown squares represent vias above the line. The Cu diffusion blocking islands between via bottom and line below provide local Blech effects for G, H and I. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

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EM lifetime can also be extended through microarchitectural circuit designs, for instance, changing the metal lines from carrying unidirectional to carrying bi-directional electric currents [6]. This can be done through time sharing of the same metal lines by different directional DC currents. Any EM damage caused by the current flowing in one direction may be fully or partially recovered by the current flowing in the other direction. This is the so-called EM repair or refueling. The advantage for the EM workload management and refueling is apparent. The issue could be the design complexity and may require extra circuit to control and manage these algorithms. To summarize for the EM aware of circuit designs, it is important to understand EM failure characteristics for different via/line connections, and take advantage of these characteristics in circuit designs, such as different redundant via arrangements and short line benefits. Wherever feasible, implementing redundant vias in the circuit design will reduce the overall EM risks. 5. EM budgeting for chip level reliability Chip level EM reliability relies on the appropriate circuit level designs and assembly, in combination with a robust manufacturing process. To ensure no circuit will suffer EM damage during chip operation lifetime, semiconductor fabricators provide generic design guidelines to circuit designers, in terms of the maximum allowed current density (jmax, or Juse) for metal lines and vias. The ultimate goal of defining jmax is to control the circuit (or element) level EM failure probabilities to achieve chip level EM reliability. For design rule generation, jmax limit is derived based on Eq. (4) in Section 2. In Eq. (4), the parameters can be divided into 3 categories: (1) acceleration parameters from reliability stresses, including jstress and Tstress; (2) metallization EM characteristic parameters derived from the stress data, including DH, n, r, and t50stress; and (3) product application parameters, including, Tuse, tlifetime and Z. Z is the key factor to link element level EM failure probability to chip level EM reliability. It is derived from the chip level EM failure target (a business target) and the total number of equivalent critical EM elements (circuits) per chip, through the weakest link statistics given in Eq. (8) [14,47,48]:

F Chip ðtÞ ¼ 1 

K Y

ð1  F i ðtÞÞ

ð8Þ

i¼1

where K is the total number of elements with EM concerns in a chip. An element may be understood as a simple line segment or line/via connection, in the sense of EM failure probability. To normalize these elements with EM concerns to a reference EM failure probability Fe, i.e., converting the K elements into M equivalent critical EM elements (details provided in Ref. [14]), Eq. (8) may be simplified as:

F Chip ðtÞ ¼ 1  ð1  F e ðtÞÞM

ð9Þ

It is almost impossible to know exactly what M would be for a given chip before the design is assembled and properly checked. Considering that the maximum design current limit, jmax, has to be provided to the circuit designers before the design can even start, an estimated envelop value of M is assumed, based on the experience and historical data, to ensure that it will cover essentially all designs. FChip is set as a business target based on the product applications, then Fe is computed based on Eq. (9), and will be used to calculate Z in Eq. (4) for jmax derivation. For example, if the end of life (EOL) EM failure target at chip level (Fchip) is set as 1 ppm, and M is assumed to be 100,000 (the number of critical EM circuits), then Fe, i.e. the end of life EM failure probability at element/circuit level, is 1011.

B. Li et al. / Microelectronics Reliability 54 (2014) 712–724

1.7

Current Relief

The purpose of above discussions is to elaborate the statistical nature of chip level EM failure probability. It should be noted that even the EM design guidelines are strictly followed for circuit designs, the chip level EM failure probability may not be known unless the total number of equivalent critical EM elements/circuits (i.e. M in Eq. (9)) is assessed. M has its own statistical meaning, it may not be a simple sum of the physical circuits/elements with EM concerns from a given chip. Typically there are millions or billions of metal line segments or line/via connections per chip, most of them have different EM characteristics, such as different local temperature, carrying different percentage of average DC current limits, different length, redundancy and via/line connection arrangements. All these differences lead to different EM failure probabilities. To evaluate each element’s contribution to the chip level EM failure, each element is ‘‘normalized’’ against a reference, typically an element with the EM failure probability of Fe [14]. For example, an element with EM failure probability of 0.1Fe will be counted as 0.1 equivalent critical EM element. M is a sum of the equivalent critical EM element numbers. The heart of the so-called EM budgeting is to assess M from the real chip design (denoted as Mactual) against M from the design guideline assumptions (denoted as Mnominal). If Mactual is greater than Mnominal, the actual chip level EM failure probability (Fchip) will be higher than the target. To maintain the chip level EM failure target, decisions need to be made if some of the designs should be modified to lower the value of Mactual. Instead of fixing the issue at chip level, this may also be managed at system level, such as smart workload management to lower the operating voltage and/or the activities of the functional blocks with critical EM concerns (lower Tuse and jEM), similar to what discussed in Section 4.4. If Mactual is smaller than Mnominal, the actual chip level EM failure probability (Fchip) will be lower than the targeted chip EM failure probability, i.e. the design has margins. Decisions may then be made to keep this margin, to allow some overdrive for the chip applications, or trade this margin for other failure mechanisms. Three examples are provided in Figs. 20–22 on the trade off relations between jmax, interconnect temperature (Tuse) and projected lifetime with the equivalent number of critical EM elements (Mactual). Above discussions have focused on the post design EM reliability verification and management. It is more important to keep the chip level EM reliability statistical nature in mind and take advantage of it during circuit designs. For chips requiring high reliability and long lifetime, it is always a good idea to keep the Mactual low. While this can be achieved by designing most of the circuits with current densities below the EM limits, a well thought out balance should be planned between safety margins, chip performance, and size/real-estate considerations. The major advantage of Mactual aware design and chip integration is the flexible management for circuit level designs for different functional blocks. For example, for some cells with high sensitivity in size, smaller metal wires may be used to help control the cell size, even though doing so may result in some cases that the jdesign exceeds the value in the design guidelines, jmax, (after exhausted the precautions discussed in Section 4). To compensate this local over-budget design, for the areas that can fit larger metal wires should be designed well below the EM limit (i.e. using larger wires and redundant vias) to make sure overall Mactual will be within the target. Caution must be taken for such practices. Based on the weakest link statistics for the chip level EM failure budgeting, the extend of the jmax limit violation determines how much those cells contribute to the early lifetime EM fails. Chip level EM budgeting relies on extensive circuit modeling and design checking activities [14,47,48]. Accurate modeling of circuit and interconnect characteristics is essential to extract the parameters correctly. Since different constructs have different EM characteristics (due to different physical and electrical features)

Relief on maximum use current density, jmax

1.6 1.5 1.4 1.3 1.2

σ =0.3

1.1 1 100K

10K

1K

100

10

1

Mactual Fig. 20. An example of maximum current density relief based on the number of critical EM elements at chip level [14].

8

Temp Overdriv,K

722

Relief on junction temperature, Tuse

6

4

2

0 100K

σ =0.3 10K

1K

100

10

1

M actual Fig. 21. An example of use temperature relief based on the number of critical EM elements at chip level [14].

Fig. 22. An example of product EM lifetime adjustment with the number of critical EM elements at chip level [14].

and different jmax limits, the circuit modeling and checking in the design tools need to recognize them and then treat each of them accordingly. Local hot spots can have significant impact on Mactual. In fact, for some chips, those local hot spots, though may only count for a small fraction of the total chip area, can contribute to the major portion of Mactual. The temperature rise in these local hot spots can come from the joule heating of the FEOL devices underneath, or interactions among the neighboring metal lines. One example of the neighboring line interactions is illustrated in Fig. 23. Fig. 23(a) shows a hypothetical layout block with signal lines only carrying AC current and power lines carrying DC current. Fig. 23(b) illustrates the joule heating effect on the center signal line (line #1) with different number of signal lines carrying AC currents to its Irms limit, which is defined to cause a 5 °C temperature rise if the line is isolated. When all the signal lines carrying currents to

B. Li et al. / Microelectronics Reliability 54 (2014) 712–724

14 12 10 8 6 4 2 1 3 5 7 9 11 13 15

GND

Signal lines

VDD

23(a) Center Signal Line (#1) 23(b)

Center VDD Line

Fig. 23. An example of local joule heating interactions caused metal line temperature rise. The numbers used in the x-axis in 23(b) start from the closest neighbors of the subject line (#1 signal line or the center (circled) VDD line).

their Irms limits, the temperature rise from joule heating (itself and its neighbors) of the central signal line can be greater than 25 °C, way above that if it is isolated. Similarly, the interaction of the signal lines with the central VDD line can cause significant temperature rise in the VDD line as well. Though the current passing through the VDD line itself causes minimal joule heating, the neighboring signal lines acting together can heat the VDD line to higher than 10 °C, which could shorten its EM lifetime by almost 50%. This 10 °C joule heating on the center VDD line will increase its equivalent critical EM count from 1 (assuming it was designed to its jmax limit at the nominal use temperature) to 180,000. Evaluating the Idc and Irms interactions and local temperature from joule heating (i.e. identifying hot spots) is an important part of the chip level EM budgeting. This is especially true for the local areas tightly packed with actively switching signal and power lines. While detailed discussions on burn in and real time product EM monitoring are out of the scope of this paper, a few words are devoted here to these two topics. For products with critical applications, burn in is usually conducted to weed out the infant (defective) fails. With the technology scaling, EM concerns have become a more important factor in determining the burn in conditions. With very densely packed devices and local interconnects, the joule heating during burn in can cause significant interconnect EM lifetime consumption. It is essential to ensure that the burn in will not cause any permanent damage to the metal lines and vias. And sufficient amount of EM lifetime should be allocated to account for the burn in consumptions. In the era of the connected world, extremely highly reliable servers are needed. Incorporating the system level redundancy and build-in reliability precautions, real time EM monitoring on critical functional blocks of highly integrated chips has been adopted for critical applications. This not only predicts how much EM lifetime remains for the critical circuits, but also contains the functions for smart workload management. The feedback from these activities can greatly help the future circuit and chip designs on EM margin management. 6. Discussion The solutions to the EM challenges due to technology scaling have relied on various innovations from all aspects, including process development, circuit design and chip/system integrations. Though these innovations have proven successful, they have been projected more and more difficult for the future technologies. From

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process development point of view, any innovative schemes to enhance the EM performance will have to overcome the challenges of line/via electrical resistance, Cu grain growth and variability. The rapid resistance increase of the interconnect has become one of the bottle necks and diminished the performance gain from technology scaling. For the advanced Cu interconnect, historically, all process integration schemes to boost EM reliability came with a certain degree of sacrifice of the electrical resistance. To slow down the resistance increase trend with scaling, new integration measures are needed not only to minimize the Cu resistivity deterioration, but also to maximize the Cu volume fraction in the trenches and vias. While the former faces the challenges of the fundamental physics (size effect from electron diffraction), the later has significant potential implications with reliability and manufacturability. Certain liner thickness in the trenches and via has proven critical for good Cu fill and slow Cu mass flow along the sidewalls. A new liner deposition process is needed to overcome these challenges. Cu grain size control has drawn significant attention for the last a few technology nodes. The larger Cu grains will lead to lower electrical resistivity due to less grain boundary electron diffractions, and more importantly will also result in less grain boundary diffusion contribution to electromigration. Promoting Cu grain growth from post plating anneal has severe limits, especially for the line dimensions down to tens of nanometers. A method to produce fine Cu lines with the ideal bamboo like or bamboo dominated grain structures has yet to be developed. Variability may become the primary concern for reliability with the future technology nodes. Variability includes process variations (various process step tolerances) and the resulted via/line dimension, profile, characteristic (such as grain size distribution) and quality variations (liner coverage, Cu fill, dopant distribution, etc.). It also covers the variations within a given device or a simple via/line connection, within a functional block, within a chip, within a wafer, within and across multiple lots. As the technology scales down, in order to have a manufacturable process window, the absolute tolerances for the critical process steps must be tightened very aggressively. This often requires introducing more costly integration schemes and tooling, and results in a smaller process window. Though the absolute tolerances decrease from technology node to node, the relative tolerances actually become larger, i.e. a deterioration in variability. The most obvious impact of variability on EM reliability is the shape factor (r) of the EM failure time distributions, as discussed in Section 2. Most of the EM statistical models were built on the basic assumptions of sample randomness. As the variability grows, the validity of sample randomness within a chip or within a wafer becomes questionable. New statistical models will have to be developed to deal with such distributions for lifetime and failure target projections. Though technological solutions can and will be developed to meet these challenges discussed above, the real potential wall ahead of the technology scaling could be the economics, i.e. whether these technology solutions can still provide viable economical benefits. Rather than developing costly technology solutions to cover ‘‘universal’’ applications, an approach to tailor the technology for specifically targeted applications and reliability may have to be adopted. Therefore, a co-optimization of process development along with circuit and chip design becomes essential. Circuit and chip designers will need to actively participate in the technology definition and process window evaluations. On one hand, the circuit and chip design teams need to understand the process capability and take advantage of the process strength and avoid the process weakness. On the other hand, the process development team knows what the critical needs are from circuit and chip designs and optimize the process windows around those critical constructs of circuit and chip designs.

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