low dielectric constant interconnects

Microelectronics Reliability 46 (2006) 213–231 www.elsevier.com/locate/microrel

Introductory Invited Paper

Electromigration of Cu/low dielectric constant interconnects C.-K. Hu *, L. Gignac, R. Rosenberg IBM T.J. Watson, Research Center, Yorktown Heights, NY 10598, United States Received 4 May 2005 Available online 2 August 2005

Abstract Electromigration in damascene Cu/low dielectric constant interconnects with overlayers of CoWP, Ta/TaN, SiNx or SiCxNyHz and Cu(Ti) interconnects capped with SiNx was studied. The results showed that the migration fast path in the bamboo-like lines primarily occurred at the interface. Cu lines fabricated with various forms of TaN/Ta liner including PVD TaN, ALD TaN, and PVD body centered cubic a- or tetragonal b-Ta liners were also investigated. Both thin surface layers of CoWP or Ta/TaN and the addition of Ti in the Cu lines significantly reduced the Cu/cap interface diffusivity and remarkably improved the electromigration lifetime when compared with Cu lines capped with SiNx or SiCxNyHz. Activation energies for electromigration were found to be 1.9–2.4 eV, 1.4 eV, 0.85–1.1 eV, and 1.3 eV for the bamboo-like Cu lines capped with CoWP, Ta/TaN, and SiNx or SiCxNyHz, and Cu(Ti) bamboo lines capped with SiNx, respectively. The structural phase of the Ta was found to have an insignificant effect on the Cu mass flow rate. A large via size, thicker liner and/or stable connected exposed liner can provide a longer lifetime and tighter lifetime distribution, at the expense of chip density or effective Cu line conductivity.
2005 Elsevier Ltd. All rights reserved.

1. Introduction Cu wiring in integrated circuit (IC) chips was developed several years ago [1–4]. The number of chips manufactured with Cu interconnects has increased every year since the initial commercialization in 1997 by IBM [5]. Cu interconnects can improve wiring conductivity and reduce RC time delays for interconnections, where R is resistance and C is capacitance. In addition, Cu interconnections have longer electromigration lifetimes compared to chips with conventional Al(Cu) metallization [5–13]. Electromigration is defined as the movement of atoms under an electric field and current.

* Corresponding author. Tel.: +1 914 945 2378; fax: +1 914 945 2141. E-mail address: [email protected] (C.-K. Hu).

The imbalance of atomic flux at some critical sites in metal lines results in the formation of voids or extrusions, resulting in failure of the chips. Commercial Cu IC chips, which usually contain 6–9 levels of Cu interconnections, are fabricated by single and/or dual damascene processes [5,6]. A typical single-damascene level is fabricated by the deposition of a planar dielectric stack, which is then patterned and etched using standard lithographic and dry-etch techniques to produce the desired wiring or via pattern. In dual-damascene processing, both the vias and the trenches are patterned in the dielectric before depositing the metal. The metals consist of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) of a metal liner, followed by a PVD or CVD Cu seed layer, and then Cu over-fills the remaining structures using an electroplating deposition technique [7]. The excess metal in the field region is then removed using a Cu

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2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2005.05.015

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chemical– or electro/chemical–mechanical polishing (CMP or eCMP) process, leaving planarized wiring and vias embedded in an insulator. Subsequent levels are fabricated by repeated application of these processes. In the damascene process, all wiring levels are planar at every level, which typically results in enhanced wafer yield over a nonplanar structure. Cu interconnections require metal liner and insulator adhesion/diffusion barrier layers to form the multilevel lines and vias [4,14]. In these structures, the top surface of the Cu damascene line is covered with a thin dielectric diffusion barrier layer, e.g. SiNx, and the bottom surface and two sidewalls are covered with a metal liner, e.g. Ta-based layer [4]. The metal adhesion/diffusion barrier liner creates material dissimilarities at level-to-level interfaces and is often the cause for electromigration flux divergence, as long as Cu mass transport through the liner is negligible. For the 90 nm technology node and beyond, inter-level dielectric SiO2 (e = 4) and high dielectric constant SiNx (e = 7) Cu cap have been replaced by lower dielectric constant materials such as SiCOH [15] with e = 2.9 and an amorphous a-SiCxNyHz cap layer with e = 5, respectively. The material change is required to enable a lower effective dielectric constant for on-chip Cu interconnections. The electromigration lifetimes of Cu interconnections are determined by the Cu void growth rate which will be influenced by the interconnect structures, the Cu interface diffusivity, the Cu microstructure and the divergence location of mass flow. The critical void volume induced by electromigration, which causes the line failure, is correlated to the liner resistance and redundancy. The liner redundancy is defined as a liner that can withstand the applied current when a void forms and the exposed liner must provide a stable metal electrical connection. The electromigration mass flow is described by (Deff/kT)Fe, where Deff is the effective Cu diffusivity, k is the Boltzmann constant, T is the absolute temperature, and Fe is the electromigration driving force. The fast diffusion paths in the Cu interconnections were found to be at interfaces and varied depending on the fabrication process and materials used [4–14]. The variation in the reported fast Cu diffusion paths is probably due to significant differences in the various integration processes, such as degas, liner deposition, CMP slurry, and precleaning Cu surface steps before depositing a capping layer on Cu. A range of activation energies for Cu electromigration have been reported from 0.7 to 1.2 eV [6–26]. These results suggest that the physical Cu/dielectric and/or Cu/liner interface properties can vary from one laboratory to another, even when similar types of SiNx or Ta are used. Identifying the dominant interface diffusion path in Cu interconnections is not only important for scientific interest but also it is a critical factor for improving Cu interconnect reliability.

Since Cu interface diffusion controls the mass flow, the electromigration flux is constrained to the interface areas of either dNw or 2dIh + dIw, where dN and dI are the effective thickness of the interfaces at Cu/dielectric and Cu/liner, respectively, and w and h are the line width and thickness, respectively. The relative amount of flux, at constant line current density, flowing through the interface region is proportional to the ratio of the interface area to the line area, dNw/(wh), or (2dIh + dIw)/(wh) [26]. The fractions of atoms at interfaces dN/h and (2dI/ w + dI/h) are increased in conjunction with smaller vias to decrease the critical void length to cause line failure as the dimension of the interconnection is scaled down. These two factors can result in the reduction of Cu electromigration lifetime causing a reduction in the allowed current density specification in Cu conductors. The present Cu interconnect structures may have to be modified to enhance Cu interconnect technology reliability beyond 90 nm-technology. For improved Cu interconnect electromigration reliability, either thick liner, large via size, permeable liner at Cu line/Cu via interface, Cu alloy interconnects, or an alteration of the Cu/dielectric or Cu/liner interfaces were reported [27]. The thick liner approaches offer reliable Cu interconnects at the expense of Cu line conductivity. Large vias provide a better connection between levels to give a longer electromigration lifetime. A large via needs a larger void to cause line failure and has a better chance of connecting exposed liners between levels when a void has formed at the via/line interface. However, the interconnection density as well as chip density would be adversely affected by the large via size design. A permeable liner at the Cu line/via interface can prolong the Cu electromigration lifetime, but it mainly relies on the line being connected to a large mass reservoir to replenish the drifted Cu mass [19,28,29]. These methods do not resolve the fundamental mass transport problem so a large variation in electromigration failure rates may occur from processing variability and chip design. The electromigration mass flow can be reduced using Cu alloy interconnections or modified Cu interfaces; however, the alloy approach increases the Cu resistivity. Therefore, the best method for maintaining high conductivity, high performance and reliability of interconnections is to alter or modify the Cu interface and fundamentally reduce Cu transport along interfaces. One has to choose a completely different approach to modify the various interfaces. For example, if the Cu/Ta liner interface is the dominant diffusion path, modification of the Cu/dielectric interface could not help to improve Cu interconnect lifetime. On the other hand, if Cu diffusion at the top Cu/dielectric interface dominates mass flow in Cu lines, modification of the Cu/dielectric interface could help to improve Cu interconnect lifetime, e.g. by capping the Cu surface with Pd [30], CoWP [30–33], CoWSn [30], ZrN [34], or Ta/TaN [35] or by Cu surface plasma-hydrogen [36–

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39] treatments. Metal caps on Cu lines can also be a good diffusion barrier such that the use of a high k dielectric cap on Cu in current interconnections would no longer be critical. Here, a dielectric stack consisting of a low k dielectric and a good dielectric etch stop material can be used. In this paper, we will review electromigration in Cu damascene lines capped with various layers, Cu alloy lines and the effects of Ta liner phase. The void location, via size and liner redundancy related to Cu lifetime distribution also will be presented.

2. Experiment Fig. 1(a) and (b) are the typical electromigration test structures. The test structures contain two wiring-levels with either (a) Mo/Cu via/Mu or (b) W line/W via/Cu M1/W via/W lines, where W line, Mu and Mo are the W, Cu underlying lines, and Cu overlying lines, respectively. The Cu M1 lines connect to W underlying lines through W vias and the Cu underlying lines Mu connect to Cu overlying lines Mo through Cu vias. The Cu via and Mo level are fabricated by dual-damascene processing and M1, W via/line are fabricated by single damascene processing. The W lines and W vias are built in SiNx/SiO2 dielectric layers. The M1, Mu and Mo Cu lines and Cu vias are embedded in a low dielectric constant material/amorphous a-SiCxNyHz. Some discussions of the Cu interconnects embedded in a SiNx/ SiO2 dielectric were also included. The final Cu lines were passivated with SiO2/SiNx, and Al(Cu) metallization was used to coat the bonding pads. However, samples with thin a-SiCxNyHz film or metal cap on top of Cu lines will also be tested. Cu line/via microstructures were analyzed by both focused ion beam (FIB) microscopy and transmission electron microscopy (TEM). The thickness and width of the metal lines and vias were measured from FIB, scanning electron microscopy (SEM), or TEM images. Energy dispersive X-ray spectroscopy (EDS) was used to analyze the elemental composition of the TEM samples. The crystallographic Ta phases and the Cu grain orientations were determined by X-ray diffraction (XRD). Void growth and extrusion of the tested lines were also examined by FIB and SEM on cross-sections

a

215

prepared by FIB. Other investigators have used transmission X-ray microscopy [40,41] or high-voltage (120 keV) SEM [42] to observe void size and growth. Rutherford back scattering (RBS) analysis was used to determine the composition of the CoWP metal layer. Electromigration stressing was performed by applying a dc current to the test lines. The samples were tested in a vacuum furnace with a forming gas (N2–5%H2) environment at 10
2 Torr or in air according to the sample structures. Failure times, s, were determined by the length of time required to increase the line resistance from the initial value R0 to DR/R0 = 1–50% depending on the failure criteria. The failure time distributions were analyzed as log-normal [43] or multi-log-normal distributions, depending on the test structures used. Samples were analyzed for void location and void morphology related to lifetime. The void growth rate was obtained from the slope of void length vs. time measurements.

3. Microstructure The Cu microstructure is one of the important factors in determining the Cu transport path. The grain size distribution, crystallographic texture, surface plane orientation, interface property, and impurity all influence the Cu diffusivity [44,45] and ultimately determine the preferred path. Variations of the local microstructure can change diffusivity of Cu and cause an electromigration flux divergence. The texture of lines can be controlled by the texture of the underlying Ti and TiN [24,46], TiW [24], or Ta [24,46,47]. A highly h1 1 1i textured Cu line showed improved electromigration resistance [24,48] in a one-level line structure, and formation of hillocks was also found to be correlated with (1 0 0) oriented grains surrounded by a least one high angle grain boundary [44]. The activation energy for surface diffusion on {1 1 1} surfaces is much lower than on {0 0 1} or {0 1 1} surfaces [49]. Texture components of h1 1 1i, h2 0 0i, random, h2 2 0i, and h5 1 1i in PVD Cu have been reported [50,51]. Since the electroplating technique has been chosen as the deposition process for Cu filling of damascene lines, grain growth, texture, and microstructure of electroplated Cu films have gained much attention in recent years [52–54]. A

b

Fig. 1. Schematic diagrams of the test structures: (a) Cu Mo/Cu via/Cu Mu two-level test structure and (b) W line/W via/Cu M1/W via/W line.

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Fig. 2. Plan view FIB images of Cu lines; (a)–(c) 2-, 0.8-, and 0.18-lm-wide Cu lines, respectively, taken at an ion beam angle of 10; (d) TEM cross-section image of a 0.1-lm-wide line/0.1-lm diameter Cu via.

bimodal grain size distribution, considerable random texture components, and a high degree of twinning have been found for electroplated Cu thin films [55]. Fig. 2(a)–(c) shows plan view FIB images of 2-, 0.8-, and 0.18-lm-wide electroplated Cu lines, respectively, taken at an ion beam angle of 10. Fig. 2(d) is a crosssection view TEM image of a 100 nm wide electroplated Cu dual-damascene line. In these images, large grains and twins are seen. The interfacial energies of a Cu twin boundary and a normal grain boundary are reported to be 44 erg/cm2 [56] and 650 erg/cm2 [57], respectively. The small interfacial energy at twin boundaries implies that Cu diffusion along a twin boundary should be close to Cu bulk diffusion. Thus, twin boundaries are not con-

sidered to be fast diffusion paths. Across the linewidth, polycrystalline grains intermixed with single-crystal grain segments were observed for the 2 lm wide lines, while bamboo-like grain structures were observed in the submicron Cu lines and vias. The bamboo-like and polycrystalline grain structures are defined as single grain per linewidth or per via and two or more grains per linewidth, respectively. All Cu grains in the Cu lines analyzed occupied the entire line thickness. The initial fine-grain structure of the Cu seed and electroplated Cu layers as shown in Fig. 3 are converted to large grains during abnormal grain growth, which can occur at room temperature or by annealing [52–54]. Fig. 3 shows a STEM cross-section of an as-plated, 0.7-lm-thick plated Cu film

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217

Fig. 3. Bright field STEM cross-section of the as-plated Cu microstructure. The sample was prepared by FIB and lift-out within 1.5 h of warming to room temperature [58].

[58]. The sample was prepared within 1.5 h of warming to room temperature, and the grains did not recrystallize during FIB milling. The cross-section in Fig. 3 shows that the plated film has multiple small grains stacked through the film thickness. A mean grain size and standard deviation of 0.05 ± 0.03 lm was calculated from a Gaussian fit to a log-normal distribution of grain areas assuming circular-shaped grains. Both twins and dislocations are visible in the as-plated grains. The barrier layer can be seen as the dark contrast material underneath the Cu film. However, the PVD Cu seed layer is not distinguishable from the plated Cu film. The transformation time from fine Cu grains to large grains is strongly dependent on deposition parameters such as plating current, bath chemistry, and layer thickness. It has been reported that plating Cu on a 0.15-lm-thick PVD Cu seed has to

be larger than the critical thickness of 0.25–0.35 lm for the abnormal grain growth to occur [54]. The large Cu grain sizes in the damascene lines and vias are due to the dual-damascene process which has a thick Cu film (overburden) over the trenches before CMP and thus abnormal grain growth in the electroplated Cu. The bamboo-like structure in the damascene line and the single crystal nature of Cu in vias are shown in Fig. 2(b)–(d). Fig. 4(a)–(c) are TEM cross-sectional images of M1 lines capped with SiCxHyNz, Ta/TaN and CoWP, respectively. All the cap layers are clearly shown. The solubility of Ta, Co and W in Cu is known to be small [59], therefore, the impact of these impurities on Cu conductivity is insignificant. Fig. 4(b) shows a Ta(24 nm)/ TaN(20 nm) bilayer film on top of a Cu line. The thickness of Ta at the bottom of the line was measured to be

Fig. 4. Cross-section TEM images of Cu damascene lines capped with (a) SiCxHyNz, (b) Ta/TaN and (c) CoWP, respectively.

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about 20 nm. The lower atomic density of the TaN layer compared to the Ta layer is seen in the TEM image. Fig. 4(c) shows a 9 nm thick CoWP film on top of a Cu line and the Cu line was completely encased in metallic thin film layers: the thin CoWP layer on the top surface and the Ta liner on the bottom and two sidewalls. Even though the two upper corners of the Cu line are voided, the CoWP film fully seals the Cu line surface. All images show that the Cu lines are completely encased with the metal liner and capped with either the dielectric barrier layer or the refractory metal layers even at the liner junctions.

4. Electromigration drift velocity The atom flux produced by an electromigration driving force Fe is given by Je = nvd, where n and vd are the atomic density and drift velocity, respectively. The drift velocity is expressed by the Nernst–Einstein: vd ¼ ðDeff =kT ÞF e ;

ð1Þ

where Fe is the electromigration driving force Fe = Z eqj, e is the absolute value of the electronic charge, Z is the apparent effective charge number, q is the metallic resistivity, Deff is the effective diffusivity of atoms diffusing through a metal line, T is the absolute temperature, and k is the Boltzmann constant. The quantity of Z represents the strength of the electromigration effect and ranges in value from 10
2 to 102 [60]. It is customary to divide Z into two parts, Z  ¼ Z el þ Z wd , where Z el arises from the direct force of the pure electrostatic nature and Z wd is the contribution from the so-called ‘‘electron wind’’ force [61] that arises from the momentum exchange between charge carriers and the diffusing atoms. The electron wind force is usually responsible for the observed electromigration in metal [60]. The effective diffusivity in a given line at one crosssection can be written as: X Deff ¼ nGB DGB þ ni Di ; ð2Þ where the subscripts GB and i refer to the grain boundary and the ith interface (atom diffusion along metal/ insulator or metal/metal interfaces), respectively; and nGB, DGB and ni, Di are the fraction of atoms and diffusivity in grain boundaries and the ith interface, respectively. The diffusivity D is expressed in terms of D0 exp(
Q/kT), where D0 and Q are the pre-factor and activation energy, respectively. In Eq. (1), diffusivity is the dominant factor for the mass transport. Only atoms diffusing along the fast diffusion paths will control the atomic movement. Several types of possible fast diffusion paths are considered: dislocations, the Cu/dielectric interface, the Cu/metal liner interface, free surfaces,

and grain boundaries. The Cu bulk diffusivity with a high activation energy of 2.2 eV [62] is the slowest and is many orders of magnitude less than the fast diffusion paths. For bulk diffusion, we can estimate that the time to grow a 0.1-lm void at 300 C using Eq. (1) with j = 2 · 106 A/cm2 and Z =
5 [63,64] is about 50,000 years. A range of activation energies for Cu dislocation, Cu/SiNx interface, free surface, and grain boundary diffusion have been reported as 1.53 eV [65], 0.8–1.1 eV [66–68], 0.5–2 eV [65,69–71], and 0.8–1 eV [72–75], respectively. Impurities on or in the fast path can also play an important role in determining the Cu diffusivity [72,73]. Sn, Pd and Zr in Cu were found to considerably slow down Cu grain boundary diffusion [74,76,77]. Dislocation pipe diffusion refers to atomic motion along dislocations. However, the cross-sectional area of a single dislocation is small, and the net diffusivity depends on the density of dislocations. Interfacial diffusion refers to atom motion along the interfaces such as between the metal/insulator (e.g. Cu/SiNx) or the metal/metal (e.g. Cu/Ta) and is highly dependent on the chemistry, bonding, impurity, and structure at the interfaces. The observations of a dominant fast diffusion path along Cu/SiNx [10,78], Cu/TaN [11], Cu/Ta [11– 13,16–19], and Cu/TiN [46] interfaces have been reported. These differences indicate that interface diffusion is related to the interface property and materials, which are very sensitive to the sample fabrication. For the Cu damascene test structures, the top surface of a line is covered by an insulator, typically silicon nitride, and the bottom and sides of the line are covered with a liner, such as Ta. The fast-diffusion paths are along grain boundaries and the Cu/silicon nitride and Cu/Ta interfaces. The effective diffusivity can be written as: [26] Z eff Deff ¼ Z I DI dI ð2=w þ 1=hÞ þ Z N DN dN ð1=hÞ þ Z GB DGB dGB =d;

ð3Þ

where h and w are the metal line height and width, respectively, the subscripts I, N, and GB refer to Cu/ Ta interface, Cu/silicon nitride interface, and grain boundary, respectively, d and D denote the effective width and diffusivity of the interfaces, respectively, and d is the grain size. For bamboo-like grain structures, the contribution of mass transport by electromigration along the grain boundary (GB) is negligible because of the absence of a continuous GB path and an electromigration driving force that is mostly perpendicular to the GBs. The drift velocity can be written as: vd ¼ dN ð1=hÞDN Z N eqj=ðkT Þ þ dI ð2=w þ 1=hÞ  DI Z I eqj=ðkT Þ.

ð4Þ

Eq. (4) states that the drift velocity in the bamboo-like grain damascene line is a function of the metal line thickness if the Cu/silicon nitride interface diffusion is

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dominant and is a function of metal line thickness and width if the Cu/Ta interface diffusion is dominant.

5. Mass flow and void growth For test structures of Fig. 1(b) type with completely blocking boundaries at both ends of the line, the boundary condition for the atomic Cu fluxes at the contact interface is: J Cu ðCuÞ
J B ðCuÞ ¼ J Cu ðCuÞ ¼ nvd ;

ð5Þ

where JCu(Cu) and JB(Cu) are the atomic Cu fluxes in the Cu lines and the blocking boundary, respectively, and JB(Cu) = 0 because no Cu can diffuse through the blocking boundary. Void growth, DL, at the cathode end of the line closely represents the mass flow and causes the conductor line resistance to increase by DR. The void growth rate is directly related to the electromigration drift velocity by DL/Dt = vd, and the lifetime s can be obtained as s = DLCr/vd, where DLcr is the critical void length for a specific change in resistance. In the case of partial blocking boundaries, such as thin liner at the Cu via/Cu line interface, voids and extrusions will not necessarily be formed at the via/line interface but will occur whenever there is an imbalance of Cu fluxes at a certain location, by the equation:


on J out
J in ¼ ; ot Dx

ð6Þ

where Jin and Jout represent the Cu flux entering and leaving at that location. The calculation of void or hillock growth rates in partially blocked boundary cases becomes rather complicated since it is difficult to estimate the drift velocity from void growth in this continuous equation. No void or extrusion can grow if Jin and Jout are equal. The void growth rate observed will not be the drift velocity.

6. Electromigration-induced backflow Under electromigration test conditions, two opposing transport mechanisms operate simultaneously: atom migration due to the electromigration force, and atom backflow due to an electromigration-induced stress gradient [79]. The stress gradient occurs because atoms which are driven out of the cathode end of the conductor cause tensile stress to form and the drifted atoms accumulate at the anode end causing an increase in the atomic density and compressive stress to form. This gradient results in a backflow of material (Blech effect) back toward the cathode [79]. Combining the electromigration force and backflow effects produces a net drift velocity:


vd ¼ ve
vb ¼

D kT



 DrX Z  eqj
; Dx

219

ð7Þ

where ve is the electromigration drift velocity and vb is the average mechanical backflow velocity. An important implication of this effect is that for sufficiently short lines or low current densities, the stress gradients can completely suppress mass transport. One can define a threshold value: a given j and a critical line length Lc (Dx in Eq. (7)) below which net mass transport vanishes (vd = 0), and jLc / Dr. Here, the critical void volume is proportional to jL2 [80]. The magnitude of the electromigration-induced stress Dr is dependent on the electromigration force. The electromigration-induced stress Dri in the line has to be less than the fracture strength Drc of the passivation layer and has a maximum value of Drc. In addition to the mechanical strength of the dielectric material, the anode end of the line has to connect to a complete blocking boundary to generate the shortlength effect. Electromigration induced mechanical backflow on lines has been reported to provide the threshold values of jLc to be 3000–7000 A/cm [68,81– 86]. These studies were carried out using a resistance incubation time in the calculations, therefore, the observations of the threshold values of jLc will be affected by the test structures employed, see Ref. [83] for the detailed discussions.

7. Fast interface diffusion path 7.1. Cu/dielectric or Cu/Ta interface The fast diffusion paths in Cu interconnections vary depending on the fabrication processes, deposition tool and materials used, and we have found that the Cu migration rate of Cu damascene interconnects can be either along the Cu/dielectric or Cu/liner interface, depending on the sample preparation. Fig. 5 shows the median lifetime, t50, as a function of line width at constant thickness at sample temperatures of 295 C. Two sets of samples were obtained from two wafers using two different PVD tools [27]. The tested samples from each wafer have the same metal line thickness and line/via overlapped area. In one case the lifetimes (symbols with squares) are nearly independent or increase slightly as line width decreases while in the second wafer lifetimes (symbols with triangles) decrease as line width decreases. A slight improvement in lifetime for the narrower lines in the first wafer is partially due to the possibility of a reduction in grain boundary contribution. This behavior is mostly consistent with a model that Cu atoms migrate along the top Cu/dielectric interface and the mass flow is proportional to thickness h only (the first term of the right hand side of Eq. (4)) [10,87,88]. On the other hand, the lifetimes from the

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7.2. Electromigration scaling rule for interconnections

100

If Cu diffusion at the top Cu/dielectric interface dominates the mass flow in Cu bamboo-like microstructure lines, then the lifetime, s, for samples with a Fig. 1(b) structure, can be simplified to:

80 t50 (h)

Cu/SiNx Cu/Liner

60

s ¼ DLCr =vd ¼ DLCr hkT =ðdN DN eZ  qjÞ;

40

20 0.2

0.4 0.6 0.8 LINE WIDTH (µm)

1.0

ð8Þ

where DLCr is the critical void length to cause line failure [10]. Therefore, the Cu lifetime will be independent on the metal line width, if the test lines have a similar h and DLCr. If DLCr is set equal to the via diameter, this is about the same as the line/via overlap length DLo and is assumed to be equal to linewidth w. The lifetime from Eq. (8) for the configuration of Fig. 1(b) would be proportional to DLCrh = wh, the line cross-sectional area. For every new generation of CMOS technology,

Fig. 5. Median lifetime vs. metal line width for varied liner deposition conditions and tools. The electron flow was from Cu via down to Cu line [27].

1

t50/t50(1.3x0.9)

second wafer drop as the line width decreases which is consistent with the fast diffusion path being along Cu/ liner interfaces. The drift velocity in this case is proportional to (2/w + 1/h) (the second term of the right hand side of Eq. (4)). In addition, a lower electromigration activation energy of 0.72 eV was obtained from the second wafer as compared to 0.9 eV from the first wafer. Fig. 6 shows the FIB image of the tested line from the second group, taken at an ion beam angle of 45. The void grew along the bottom Cu/Ta interface at a rapid rate. The exact reasons for the varied diffusion fast paths between these two sets of samples are not clear; we speculate that the high oxygen concentration in the Ta liner in the second group of samples during the liner and Cu seed depositions caused reduced adhesion and rapid diffusion.

Theory

0.1

0.01 0.0

0.2

0.4

0.6

∆Lcr h

0.8

1.0

1.2

(µm2)

Fig. 7. Normalized median lifetime vs. DLCrh for various Cu interconnect generations [89].

Fig. 6. FIB image of the electromigration-tested line at 295 C for 6 h. The image was taken at an ion beam angle of 45 [27].

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1.20 T =299ºC 90 nm wide line 1.15 R/Ro

the width and thickness of metal lines and via diameters are scaled down by about a factor of about 0.7. (The minimum gate length is also about 0.7 of the minimum metal line width in each generation, for example, 90 nm CMOS technology has a metal line width of 0.13 lm.) The ratio of the median lifetime t50 relative to 1 lm technology t50 (via diameter, or DLCr = 1.3 lm and h = 0.9 lm) for each CMOS generation from 65 nm to 1 lm technology is plotted in Fig. 7 as a function of DLCrh. This is an updated plot of Fig. 5 in Ref. [89], clearly showing a decrease in t50 with each CMOS generation. The solid line in Fig. 7 is the estimated curve according to Eq. (8) with no adjustable parameters. The experimental data points closely follow the theoretical curve generated by Eq. (8) which supports the validity of the model.

221

1.10

1.05

1.00 10

100

1000

Time (h) Fig. 8. Normalized line resistance as a function of time.

8. Line resistance and void growth 8.1. Mass flow from W via to Cu M1 and liner resistance The line resistance change as a function of current stress time in a metal line connected to blocking boundary using the test structure as shown in Fig. 1(b) will be presented in this section. Here the Cu flux divergence at the W contact interface is the dominant failure mode. In this structure, the void growth rate at the cathode end of the line is the electromigration drift velocity. The relationship between the rates of material depletion and the line resistance change, DL/Dt and DR/Dt, can be generally obtained as follows: DRðtÞ ¼ ðqTa DLÞ=ATa þ qCu ðL
DLÞ=ACu ;

ð9Þ

so that DR/Dt = (qTa/ATa
qCu/ACu) DL/Dt is proportional to vd, since DL/Dt = vd. The subscripts Ta and Cu refer to Ta liner and Cu conductor, respectively, q is the electrical resistivity, A is the cross-sectional area of the specific metal; L is the initial conductor length; and DL is the void growth length. The change in line

resistance is simply a linear function of the electromigration drift velocity. A 90 nm wide line resistance change curves as a function of time for a sample temperature of 299 C are shown in Fig. 8. The void formation in a damaged line is shown in Fig. 9, which is a cross-sectional view FIB of a tested line taken at ion beam angle of 45, illustrating the typical degradation mode of void growth at the cathode end of the line. The lifetimes are rather uniform, varying within 30% sample-to-sample (illustrating that the mass transport rate is an average measurement through a large number of grain surfaces). Initially, the line resistance changes slowly, followed by an abrupt step of resistance change and a period of rapid, constant resistance rise. The initial period of the slow resistance change rate for the resistance incubation time si  100 h was caused by void growth within the W/Cu overlap length (DLo) as indicated in Fig. 9, because a large voltage change will be sensitive only to a void that grows beyond the Cu/W overlap area. Therefore, DR(t)  0, if DL < (DLo). The abrupt line resistance step is believed to occur when the void grows just beyond the W stud. It corresponds to a change in

Fig. 9. FIB image of an electromigation damaged SiCxHyNz capped Cu line tested with 4 mA/lm2 at T = 299 C for 265 h. The critical void length is DLo + DLd where DLo and DLd are the Cu/W overlap length and void growth beyond DLo, respectively.

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the contact resistance between W studs/TaN/Ta liner/ Cu and W studs/TaN/Ta, and also to current flowing over a thinned liner region covering the step between the end of the W stud and the line. The final period of resistance change is attributed to void formation and growth where the current has to pass through the thin, high-resistance liner underlayer to connect the remaining Cu line to the W via. In this case, the exposed liner will be referred to as liner redundancy. For this structure, Eq. (9) should be modified to: DRðtÞ ¼ ðqTa DLd Þ=ATa þ qCu ½ðL
DLo Þ
DLd =ACu  ðqTa DLd Þ=ATa ; ð10Þ

250 200

Wafer T (ºC) j (mA/µm2) A 348 4 B 320 24

(a)

∆R (Ω)

(b)

(e)

150

(d)

(f)

100 50 (c)

0 0

50

100

150

200

250

Time (h)

Fig. 10. Test line resistances as a function of time for samples from wafer (A) and (B); dotted lines = wafer (A) and solid lines = wafer (B).

where DLd is the void length beyond DLo. Eq. (10) shows the relationship between the void growth DLd and line resistance change. It indicates that the change in line resistance is simply a linear function of the electromigration mass flow and liner resistivity and an inverse function of the liner cross-sectional area. Eq. (10) also shows that a larger liner area and/or lower liner resistivity would result in a slower resistance change rate and a longer lifetime for a higher % failure criterion even with an identical mass flow rate. Although a thicker liner with a lower liner resistance would result in a longer lifetime and a more reliable Cu interconnect, the nominal metal line resistance would increase. For the case of no liner redundancy, the exposed liner cannot support the applied current. A large resistance increase or even a melted liner will occur. In this case, the Cu lifetime will be strongly dependent on the void location and void growth mechanism such that a wider lifetime distribution is often observed. Some line resistance change curves DR = R
Ro as a function of time for a sample temperature of 348 C with j = 4 mA/lm2 from wafer (A) and 320 C with 24 mA/lm2 from wafer (B) are shown in Fig. 10. The liner thickness from the wafer (A) is about half that of wafer (B). The tested samples labeled (a)–(f) in Fig. 10 was terminated at 19 h, 62 h, 169 h, 232 h, 236 h and 248 h, respectively. The voids for the corresponding samples (a)–(f) are shown in Fig. 11(a)–(f), respectively. The observed lifetimes follow a log-normal distribution and have the values of deviation, r, around 0.75 and 0.25 for wafer (A) and (B), respectively. With this rapid increase in line resistance for wafer (A), the lifetime difference between DR/R0 = 1% and DR/R0 = 20% in most of the samples tested was small. However, for the thicker liner of wafer (B), there has been a gradual line resis-

Fig. 11. FIB images of electromigration tested Cu lines capped with SiCxHyNz connected to W vias; (a)–(c) and (d)–(f) are the samples tested at 348 C and 320 C, respectively. (a)–(f) correspond to the samples labeled (a) to (f) in Fig. 10, respectively.

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tance increase as shown in Fig. 10. Here the lifetime defined by time at DR/R0 = 1%, 20%, or 50% differed significantly. An abrupt increase in the line resistance change curve shown in Fig. 10 occurred in samples from wafer (A), indicating an unstable liner in those samples. Once the exposed liner had to carry the applied current, a large resistance jump occurred and the line failed. The sample (a) from wafer (A) had a small void size and a short lifetime. There was no tested line resistance change in sample (c) even after a test time which was 9· that of sample (a). This result was due to void growth occurring by the thinning down of multiple Cu grain surfaces, as shown in Fig. 11(c). Here, the majority of the current still flowed through the Cu grains, hence no significant tested line resistance change was observed. The Cu atoms migrated along the Cu/dielectric interface which was accommodated by either edge displacement or surface grain thinning mechanisms. The schematic diagrams in Fig. 12(a) and (b) illustrate Cu void growths by edge displacement and surface grain thinning, respectively. Edge displacement void growth occurs when the Cu atoms that are migrating along the top surface of the Cu line are replaced by Cu atoms diffusing from the bottom of the line along the void free surface, causing the void boundary to move in the direction of the electron flow. Cu void growth by surface grain thinning can be described as Cu atoms drifting along the Cu/ dielectric interface being fed by the thinning of a Cu grain or grains directly upstream. Here the surface

223

atoms on the upstream grain diffuse to the void boundary, and then move up the step to feed the atoms that flow at the Cu/dielectric interface. In this case the void appears stationary. The observed voids in Fig. 11(a) and (b) appear to be of the edge displacement type, although both edge displacement and surface grain thinning induced voids often occurred in fine, thin test line structures; therefore the observed mean value of DLCr at the resistance incubation time si is an average value of DLo mixed with the Cu grain size. If there is no liner redundancy in the samples, the variations in initial void location and void growth mechanisms can cause a wider lifetime distribution. The exposed redundant liner in wafer (B) withstood the applied current and allowed the void to continually grow to a large size. The additional time allowed the tested lines to have similar final void lengths and a tighter lifetime distribution was obtained since the lifetime distribution actually reflected the critical Cu void volume distribution. 8.2. Mass flow from Cu via up to Cu line Electromigration drift velocity should obey Eq. (1) and should not vary depending on the direction of mass flow. However, the void location and physical conditions of the liner in the vicinity of the Cu via/line contact can strongly influence the lifetime of the tested lines, even though the electromigration mass flow is the same in all the cases. Depending on the liner stability, the failure distribution can be represented by a tri-modal [90], a bimodal [18,66,91,92] or a single mode [27] function. When a void grows in the via bottom during electromigration testing, a thin liner at the via bottom sidewall cannot withstand the high current and causes a large

Cum. Failure Probability (%)

99 98 95 90 80 70 60 50 40 30 20

∆R/Ro > 20%

10 5

t50 (h) 132 866

2 1 2 10 Fig. 12. The schematic diagrams of void growth mechanisms: (a) edge displacement and (b) surface grain thinning. The direction of electron flow is from right to left. Arrows with the dotted lines show the migration of Cu atoms.

10

σ

o

T( C)

0.10 305 0.36 267

3

τ (h) Fig. 13. Cumulative % failure vs. s for Cu dual damascene line/ via on a log-normal scale using Fig. 1(a) test structure. Solid and dashed lines are the least-squares fits to the data [27].

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resistance increase or line open. A thick liner, however, can provide a path for stable current passage where a marked, sharp resistance increase will not occur when a void grows across the via or line. For example, at DR/R0 = 20% with a typical Cu line length of 400 lm, the test line would allow a via bottom void to grow into a line/via void before it reaches 20%. Fig. 13 shows a plot of cumulative percent failure as a function of log(s) using the test structure of Fig. 1(a) for electron flow from a wide Mu to via to a fine Mo, where Mo is the 0.22 lm wide test line. [27] Here, a linear behavior in the log-normal probability plot was observed that indicated a single failure mode. Fig. 14 is a cross-section FIB image which shows the microstructure of the Cu line/via/line [27]. In addition to a thick liner on the via sidewall, the Cu via embedded into Cu Mu is about 0.1 lm. For this structure, a bottom via void would

Fig. 14. FIB image of electromigration damaged Cu line/Cu via/Cu line [89].

not greatly raise the line resistance and the stable sidewall liner would allow a gradual resistance change even if the liner became exposed when a void spanned the entire line or via width. The lifetime was set at the time for the line resistance to increase by 20%, which allowed a 0.5 lm void length to grow. For this stable via liner case, the line resistance change as a function of current stress time would be similar to the results from the test line using Fig. 1(b), and the observation of a single lognormal distribution would not be surprising. 8.3. Mass flow from Cu via down to Cu line In this section we describe Cu mass flow from the Cu via down to the Cu line in which a multiple failure modal distribution has been reported [84,85]. The quality of the connecting liner redundancy between via and line on electromigration lifetime is critical to determine the lifetime distribution. Test lines from two different via sizes using the Fig. 1(a) test structure were used to elucidate the importance of this redundancy. The dielectric cap under the Cu via shown in Fig. 1(a) was removed during via etching. Fig. 15 shows a plot of the normalized line resistance as a function of time at a testing temperature of 295 C [27]. The data with connected open circles and with solid lines are the normalized 0.14 lm wide line resistances with Cu via diameters of 0.16 and 0.28 lm, respectively. Fig. 16 shows the median lifetime, t50, and the deviation r of the lifetime distribution using a log-normal function, as related to the DR/ R0 percent failure criteria. During the electromigration test the exposed liners connecting the Cu via/Mu are not always physically stable, especially for the case of

Fig. 15. Normalized test line resistance vs. time with a Fig. 1(a) test structure. Data with connected open circles and with solid lines are from samples with via diameters of 0.16 and 0.28 lm, respectively [89].

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growth times also resulted in a similar void size for all the samples so that a smaller r was obtained.

1000 0.28 µm 0.16 µm

8.4. Thin liner at bottom Cu via and Cu line interface

100

10

σ

0.28 µm 0.16 µm

1

σ 0.1 0

20

40

60

80

100

∆R/Ro (%)

Fig. 16. Plot of median lifetime t50 and deviation r vs. various percent failure criteria for two different via sizes. The data points are connected for clarity [89].

a smaller via size. An unstable liner connection causes a large resistance jump when the exposed liners have to carry all of the current as the void grows in the Mu line under the Cu via. Thus, for the unstable liner connection case, the void growth under the via resulted in a large resistance shift and the time differences between times for DR/R0 = 1% or 50% were small as can be seen in the data for the 0.16 lm via diameter in Fig. 15. Edge displacement and grain thinning voids under a via can vary considerably in terms of the time for the line resistance jump to occur in this test structure; a grain thinning type void under a via associated with smaller vias gives a shorter lifetime than an edge displacement void. Also, if the void growth is by surface thinning a Cu grain or grains away from the via, a longer lifetime will occur because a Cu grain is usually larger than the via size. Consequently, because of the mixed critical void size for failure a wider lifetime distribution (large value of r) was obtained for smaller vias, as shown in Fig. 16. For the case of a large via size (0.28 lm), one would expect about a factor of about two time delay for the initial line resistance jump as compared to the smaller via (0.16 lm) samples because the via diameter was increased by a factor of 1.8. In addition, a larger via would also give a larger bottom via-to-line liner connection which could be stable enough to carry the current as the liners are exposed. A gradual line resistance change was observed (Fig. 15) for 0.28 lm via diameter samples where the void could continue to grow without a sharp resistance increase. Fig. 16 clearly shows that longer t50 and tighter r were obtained for a wider via over the entire range of % DR/R0 failure criterion, even though for both via cases the mass transport rates and the fast interface diffusion path were the same. The longer void

Fig. 17 shows several normalized line resistance plots as a function of time for 0.27 lm wide lines with either Fig. 1(a) or (b) test structures stressed with a current density of 22 mA/lm2 at a sample temperature of 350 C. The dotted and solid curves represent the samples measured with the electron flow from dual-damascene Cu via down to a single-damascene Cu M1 and W via up to Cu M1, respectively. There was a marked difference in failure lifetimes between electron flow from the W via up to M1 and Cu via down to M1. The line resistance initially decreased slowly, then increased, followed by a period of rapid rise. A rather tight failure time distribution (t50 of 26 h and r of 0.3) was obtained in the case of W via to M1 electron flow. For the electron flow from Cu via to M1, a wide range of failure times was observed. Only 50% of the samples in this case had a similar lifetime of around 26 h, as in the W via to M1 case. The other 50% of the samples showed a much longer lifetime, some with no resistance increase even after 180 h. Similar long lifetime behavior was also observed in the case of mass flow from Cu via up to Cu Mo [19,29]. The observations of the short- and long-lifetime groups were for all sample temperatures investigated from 250 to 350 C. The drift velocity or mass flow of Cu in the Cu M1 line should be identical regardless of the direction of electron flow, and if either end of the M1 line was contacted to a completely blocking boundary, mass depletion at the cathode end and mass accumulation at the anode end of the line should occur. Thus, for the case of electron flow from a blocking

1.10 T = 350ºC Electron Flow W Via to M1 Cu Via to M1

1.08 1.06 R/Ro

t50(h)

t50

225

1.04 1.02 1.00 0.98

0

20

40

60

80 100 120 140 160 180 Time (h)

Fig. 17. Line resistance vs. time for Fig. 1(a)–(b) test structures at 350 C. Solid lines represent electron flow from W via to Cu lines; dotted lines represent electron flow from the Cu via to the Cu M1 line [28].

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boundary W CA to M1, the void growth rate in M1 near the W CA should follow Eq. (1). On the other hand, if the liner at the Cu via/Cu M1 interface was only a partial blocking boundary, then Eq. (6) should be used. The migration of Cu M1 beneath the Cu via liner could be replenished from Cu via/Mo Cu. Hence a very long lifetime would result. As this case illustrates, the exact condition of the liner at the Cu via and Cu line interface can strongly influence the lifetime of the tested lines, even though the electromigration drift velocities are the same in all cases. 8.5. Effects of liner phase The Ta liner phase has been reported to strongly influence the Cu lifetime and electromigration activation energy [22,23]. The Cu lines with a body centered cubic (b.c.c.) a-Ta liner have been shown to have a higher electromigration activation energy than Cu lines with a tetragonal b-Ta liner [22,23]. Since this effect should not be seen if the dominant fast diffusion path were at the Cu/dielectric interface, these experiments were repeated. Fig. 18 is a plot of void growth rate in Cu damascene lines as a function of various Ta phases at a sample temperature of 300 C and j = 24 mA/lm2. Void growth rates of 0.4–0.6 · 10
2 lm/h were measured as shown. The data were obtained from tested lines connected to a blocking boundary using Fig. 1(b) test structure. In this case, the void growth rate closely approximated the mass flow rate or drift velocity. The b.c.c-Ta and b-Ta phases in these samples were obtained by an adjustable sputter etching step between TaN and Ta depositions during metal liner processing. The Ta phase of the test samples were determined by XRD.

Void Growth Rate (10-3 µm/h)

8 7 6 5 4 3

α-Ta

β-Ta

α-Ta

C1

G0

G1

2 Wafer ID Fig. 18. Void growth rate vs. various wafer liner process conditions. The measured Ta phases determined by XRD are also shown.

The similar values of drift velocity in these samples suggest that the effective diffusivity of the Cu lines were about the same and were not influenced by the various Cu/Ta phase interfaces. In addition, similar values of electromigration activation energy QEM between 0.91 eV and 1.0 ± 0.04 eV for the Cu lines with a-, b-, or a + b-Ta liners were also obtained. Although QEM in the Cu lines of 0.70 eV [22] and 0.75 eV [23] for bTa liners and 0.84 eV [22] and 0.98 eV [23] for the aTa liners were reported, here the measured values for the samples with the b-, a- or a + b-Ta liners were about the same. The present work of similar activation energies and void growth rates extracted from the wafers with various Ta phases is consistent with the assumption that the dominant diffusion path in these Cu lines was along the Cu/dielectric interface. As long as the Cu/Ta interface diffusivity was lower than that at the Cu/dielectric interface, the electromigration behavior of these samples will be controlled by the diffusivity along the Cu/dielectric interface and variations along the slower Cu/Ta diffusion path cannot affect the overall Cu effective diffusivity. As a side comment, the chemical purity of the Ta surface prior to copper deposition can greatly vary the electromigration behavior at that interface and the intrinsic Cu/Ta interface diffusion may not present.

9. Reduced Cu mass flow 9.1. Alloy Cu lines with Sn impurity have been shown to have improved Cu electromigration lifetime and a reduced void growth rate measured from in situ [93] and ex situ [14] SEM techniques in Cu(Sn) compared to pure Cu lines. The effect of impurities Al [94], Sn [93,94], Mg or Zr [76] in Cu on the Cu electromigration void growth rate on unpassivated polycrystalline Cu lines is briefly reviewed in this section. The dominant Cu electromigration paths in these structures would be along the Cu grain boundaries and the free Cu surfaces. The drift velocity and line damage rate of Cu were greatly increased by adding Al [94] or Mg [76] and reduced with Sn and Zr solute additions [93,94,76]. The combination of a small Cu grain size in Cu(Mg) and the lack of a pinning effect of Cu by Mg along the fast diffusion paths resulted in enhancing the Cu line damage. The time for an equivalent resistance change DR corresponding to electromigration damage in pure Cu and Cu(Sn) alloys was progressively increased as a function of Sn content. The effect of Sn solute in bulk Cu is different from that in thin films. In bulk Cu(Sn) samples, Sn solute enhances Cu and Sn lattice diffusion [95], while solute Sn decreases Cu diffusion in Cu(Sn) grain boundaries of thin films [74]. These observed behaviors are similar to Pd

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in Cu(Pd) [77] and Au in Au(Ta) [96] studies. The observation of reduced Cu grain boundary diffusion during electromigration in Cu(Sn) alloys can be qualitatively interpreted in terms of the solute Sn reducing the grain boundary energy [97] and/or acting as a trapping site [98,99] for Cu. Both models predict D(Cu)/D(Cu(Sn))  1 + ZC0 exp(
(DE
TDS)/kT), where D(Cu) and D(Cu (Sn)) are the Cu diffusivities in pure Cu and Cu(Sn) alloy, C0 is the solute concentration, Z is the coordination number for the solute atom, and DE and DS are the corresponding binding energy and entropy for solute interaction in grain boundaries, respectively. The numbers of free Cu atoms or vacancies are drastically reduced in the fast paths because of the Sn–Cu atom or Sn–vacancy interactions, which depend on the diffusion mechanisms in the grain boundaries [100]. If we assume that the ratio of drift velocity for pure Cu to Cu(Sn) alloys is due to changes in effective diffusivity, then a binding energy DE on the order of 0.5 ± 0.3 eV between Sn–Cu atoms and/or Sn–vacancy at grain boundaries is obtained. A binding energy DE  0.5 eV is a similar magnitude as the increase in the activation energy [74] for grain boundary diffusion observed in Cu upon addition of 2 wt.% Sn. Improved Cu electromigration lifetimes in Cu lines incorporated with a Cu(1 wt.% Ti) or Cu(1 wt.% Sn) alloy seed layer was observed [101,102]. In the following discussion, the electromigration results for structures constructed with a Cu(2.5 wt.% Ti) seed layer in 0.22 lm wide dual-damascene lines are reported. Fig. 19 shows a plot of the test line resistance change curves as function of time for pure Cu and Cu(Ti) alloy interconnects at sample temperature of 305 C. The Cu(Ti) interconnections were produced by replacing the pure Cu seed with a thin Cu(2.5 wt.% Ti) alloy seed deposited on the line trenches/vias before the electro-

227

plated Cu processing step. The Ti concentrations in the Cu grains and surfaces were below the detection limit of EDS, but Ti was detected in the Ta liner. The direction of electron flow used in the samples in Fig. 19 was from the Cu via up to the Cu Mo line. A large resistance jump was observed after less than 20 h of current stress and a void size of 0.45 lm in the Cu line or at the line/via vicinity was observed for a 20% DR/R0 failure criterion. However, only a few Cu(Ti) lines failed after 2000 h of testing and the majority of the Cu(Ti) samples showed no resistance increase even after 2600 h. The electromigration activation energies for Cu and Cu(Ti) interconnects were found to be 0.9 eV and 1.3 eV, respectively, illustrating the possibility of improved chip lifetime. 9.2. Metal cap on the top Cu line surface Improved Cu electromigration lifetime was reported when testing Cu lines with thin (10–20 nm) surface layers of electroless CoWP [30–33], CoSnP [30], and Pd [30] or PVD Ta/TaN [35] and ZrN [34]. Fig. 20 shows a plot of normalized line resistance vs. time for Cu M1 lines capped with various overlayers with a Fig. 1(b) test structure [103]. The Cu lines with a SiCxHyNz cap were tested at 249 C and 333 C, with a Ta/TaN cap at 333 C, and with CoWP cap tested at 350 C. This plot shows that initially for the SiCxHyNz capped samples stress at 249 C, the line resistance changes slowly, followed by a period of rapid resistance rise. When stressed at 333 C, an abrupt line resistance increase occurred for the SiCxHyNz and Ta/TaN coated samples at times <20 h and over several hundred hours, respectively. The SiCxHyNz capped samples had to be tested at the lower temperature, 249 C, in order to obtain similar lifetimes to the Ta/TaN capped samples tested at 333 C. However, no significant resistance increase was

1.20 T = 305ºC Cu Via to Mo

1.20

T=333ºC o

1.15

1.10

1.10

Cu Seed

SiCxHyNz

T= 333ºC Ta/TaN

R/Ro

R/Ro

1.15

T= 249 C

SiCxHyNz

1.05

T=350ºC

1.05

CoWP Capped

1.00 0.95

1.00

Cu(2.5%Ti) Seed

0

1000

2000

3000

4000

TIME (h) Fig. 19. A plot of the normalized line resistance as a function of time for the samples with pure Cu and Cu(Ti) seed layers.

0

200

400

600 800 TIME (h)

1000

1200

Fig. 20. Test line resistance change vs. time for the SiCxHyNz, Ta/TaN and CoWP capped samples [103].

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observed for the CoWP capped samples even after testing at 350 C for over a thousand hours. The gradual line resistance increase over time in CoWP capped samples was due to Co bulk diffusion into the Cu grains causing reduced Cu conductivity [32]. The activation energy of Co diffusion in Cu lines was found to be 2.2 eV, and the solubility limit of Co in Cu was found to be 18e(
0.57 eV/kT) atomic percent [32]. Fig. 20 clearly shows that metal capped samples provide significant resistance to electromigration damage when compared to samples with a SiCxHyNz cap, and CoWP capped samples have longer lifetimes than Ta/TaN capped samples. Fig. 21(a)–(c) shows focused ion beam images taken at an ion beam angle of 45 for tested lines with SiCxHyNz, Ta/TaN, and CoWP caps stressed at 250 C, 377 C and 377 C with 35 mA/lm2 and lifetimes of 600 h, 62 h and 1034 h, respectively. From the sample temperatures and lifetimes, these images show that the void growth rates in the Cu lines were drastically reduced for the lines capped with Ta/TaN and further reduced for the lines capped with CoWP. From measurements of the void size shown in Fig. 21(c) and several additional FIB images of failures, a near constant void growth rate of 1.2 nm/h at 377 C was determined with an almost zero incubation time for void nucleation. In addition, unlike the usual void growth by either edge displacement and/or Cu grain thinning from the top sur-

face, the void growth was found to be initiated from the bottom Cu line/W via interface in the CoWP capped samples. The images in Fig. 21(c) suggest that the Cu atoms drifted along with the electric current field lines in the Cu grain implying that bulk diffusion could be the controlling diffusion mechanism. The activation energy for electromigration in Cu damascene bamboo-like lines with dielectric, Ta/TaN and CoWP caps was found to be 0.9–1.0 eV, 1.4 eV, 1.9–2.4 eV, respectively, suggesting that CoWP capping caused a great reduction in Cu interface diffusion [32]. However, the electromigration activation energy for 2-lm-wide dual-damascene CoWP capped polycrystalline lines was found to be 1.0 ± 0.1 eV [31]. In this case, the measured activation energy is in good agreement with the activation energy [72–74] of Cu grain boundary diffusion. The fact that similar lifetimes in the investigated temperatures were obtained for both bamboo-like and 2-lm-wide polycrystalline lines with a SiCxHy cap indicated that the dominant diffusion path in these lines was along the Cu/ SiCxHy interface, not the grain boundaries. The 2-lmwide CoWP line had an average grain size d of 1.2 lm, while the 0.28-lm-wide silicon nitride capped lines had a metal line thickness h of 0.25 lm. From this, we would expect a factor of roughly about 5· reduction in void growth rate from d/h in Eq. (3) if the dominant migration path were from the Cu/silicon nitride inter-

Fig. 21. FIB images of electromigration tested samples for (a) SiCxHyNz capped line at 250 C with a lifetime of 600 h, (b) Ta/TaN coated line at 377 C with s = 64 h and (c) CoWP capped line at 377 C with s = 1220 h [103].

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face for the 0.28-lm-wide line and from grain boundaries for the 2-lm-wide, CoWP capped line, even though similar activation energies were obtained in both cases. However, the existence of single-crystal grains capped with CoWP in the 2-lm-wide line would create a blocking path for grain boundary diffusion, which could further increase the lifetime for the samples with a CoWP cap. Therefore, one may expect more than a factor of 5 in the 2-lm-wide CoWP capped line samples as compared with the 0.28-lm-wide silicon nitride capped bamboo lines. This is consistent with the finding of a 10· improvement in the 2-lm-wide CoWP capped lines. The observed activation energy for the bamboo-like lines capped with CoWP was close to the value of 2.2 eV [62] for Cu bulk diffusion. From the electromigration data, it is not known if the diffusion path in the bamboo-like line structure capped with CoWP is along the Cu/Ta interface, Cu/CoWP interface, or in the bulk Cu. It should be considered that the activation energy for diffusion at interfaces at T > 350 C need only be greater than 1.8 eV for the bulk to be controlling, since the fraction of atoms at the interfaces is only about 1/100 of the atoms in the bulk Cu. This also suggests that the activation energy for Cu mass flow along the Cu/Ta sidewall/bottom liner interfaces must be at least as large as that found for the Cu/CoWP interface. The observation that the value of Q obtained for the CoWP capped samples is higher than that obtained from the Ta/TaN capped samples shows that the Cu/Ta interfaces of the sidewall and bottom liners maybe different than the Ta capped interface which showed a Q of 1.4 eV. The Cu/Ta liner sidewall/bottom interface was prepared by PVD without a vacuum break, while the top Cu line surface and Ta cap interface was prepared by PVD Ta deposition after Cu CMP. These data again suggest that slight variations in Ta/Cu preparation could cause drastically different interface diffusion and the Cu surface pretreatment before metal cap is a critical step in determining Cu/metal interface diffusivity. The details of the physical properties of the Cu/Ta interface related to the interface diffusivity remain an important and interesting subject to be studied. The existence of voids at the bottom of the via could suggest that diffusion at Cu–Ta interfaces or in Cu bulk was dominant, although this voiding could have been caused by topinterface Cu diffusion and vacancy migration to the via bottom (vacancy sink). The mechanism of reduction of the interface diffusion by substitution of Cu/metal for Cu/SiNx or Cu/amorphous SiCxHy interfaces is not totally understood, although it is tempting to speculate that the Cu migration is affected by the number of interfacial defects, the interface bond strength, and/or the surface migration energy of Cu atoms directly in contact with the cap material. Increased improvement in electromigration resistance is expected to translate to exceptional flexibility for the

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circuit designers, effectively removing electromigration as the limiting factor for use of high currents. The results of the tests further support the hypothesis that the interfaces of Cu with the dielectric cap are the major sources of electromigration and thus reliability degradation.

10. Conclusion Electromigration in Cu single- and/or dual-damascene lines was reviewed. The mass transport in Cu interconnects occurs mainly by interface diffusion. Fast diffusion along either the Cu/metal liner or Cu/dielectric interface has been reported, although the latter is significantly more prevalent. The results of electromigration test lines suggest that the fast diffusion path in Cu interconnects is very sensitive to the nature of the interface, which is dependent on the selected fabrication of materials and processes. The Cu void growth rate at the cathode end of a completely blocking boundary is related to 1/(metal line thickness) and is independent of the linewidth, when the top Cu interface diffusion is the dominant diffusion path. The diffusion of Cu at the top of a Cu damascene line was greatly reduced with the addition of a CoWP, Ta/TaN cap or the use of Cu(Ti) alloy seed. These capping and alloying processes can produce lines with extremely long electromigration lifetimes and, if implemented in chip manufacturing, electromigration damage may no longer be a limiting factor for the designed use current density in on-chip Cu interconnections. A drastic reduction of the void growth rate was found for a thin metal CoWP capping layer on to Cu line surfaces which suggests that fast diffusion in Cu lines is along the Cu/dielectric interface rather than the Cu/Ta interface. Primarily two void growth mechanisms, grain thinning and edge displacement, have been observed in Cu. The Cu lifetime distribution for via-to-line electron current flow will differ for the cases of via above and via below the Cu line which mainly result from the void growth characteristics. These differences can be seen particularly for the case of a via fully landed inside a line with electron flow from via to line and a blocking boundary at the bottom of the via. If there is a lack of connecting liner redundancy, grain thinning void growth can quickly separate the via from the line, which will then cause a sharp resistance change at early failure lifetimes. The Cu lifetimes are strongly influenced by the connecting liner redundancy in a level and between the levels since in most cases, the lifetimes are defined by the degree of the line resistance increase created from the exposed liner resistance. The lifetime distribution is mainly related to the spread in critical void lengths. For the case of Cu via/Cu line test structure, the lifetime distribution is compounded by the possibility of voiding within the via instead of the line. The Cu lifetime

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