- Email: [email protected]
Enhancement of adhesion strength of Cu layer with low dielectric constant SiC:H liners in Cu interconnects
Microelectronics Journal 36 (2005) 749–753 www.elsevier.com/locate/mejo
Enhancement of adhesion strength of Cu layer with low dielectric constant SiC:H liners in Cu interconnects Grace Wanga,b, S. Balakumara,*, S.C. Hweea, Rakesh Kumara, T. Harac a Institute of Microelectronics, 11 Science Park Road, Science Park II, Singapore 117685 Department of Electrical and Computer Engineering, National University of Singapore, Singapore c Hosei University, Tokyo, Japan
b
Received 2 August 2004; received in revised form 2 November 2004; accepted 9 November 2004 Available online 18 January 2005
Abstract One of the primary candidates for the liner/etch stop layer in damascene process is silicon nitride (Si3N4). However, silicon nitride has a high dielectric constant of 7.0. To reduce the effective dielectric constant in Copper (Cu) damascene structure, dielectric SiC:H (prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source) as the Cu diffusion barrier was studied. The dielectric constant of SiC:H used is 4.2. A systematic study was made on the properties of liner material and electro-chemically plated (ECP) Cu to enhance the adhesion strength in Cu/low-dielectric constant (k) multilevel interconnects. Though the effects of as Si3N4 the liner have been much studied in the past, less is known about the relation between adhesion strength of ECP Cu layer and physical vapor deposited (PVD) Cu ˚ . The annealing of Cu seed layer was carried out at 200 8C in N2 ambient for 30 min was carried out seeds, with seed thickness below 1000 A to study the impact on adhesion strength and the microstructure evolution on the adhesion between ECP Cu and its barrier layer. In the study, our claim that SiC:H barrier/etch stop layer is essential for replacing conventional Si3N4 layer in enhancing adhesion strength and interfacial bonding between Cu/dielectric interconnects. q 2004 Elsevier Ltd. All rights reserved. Keywords: Adhesion strength; Cu layer; Trimethylsilane; Cu diffusion liner
1. Introduction Cu is being extensively adopted in deep-submicron ultralarge scale-integration (ULSI) interconnection as it offers both higher conductivity and better electromigration resistance over Al alloys. However, many process integration issues exist, one of which is the rapid drift of Cu ions in SiO2 under the influence of an electric field. Cu diffusion in dielectric may give rise to an unanticipated yield or reliability problem. Hence, a diffusion drift barrier is necessary to prevent Cu movement into interlevel dielectric. The primary candidate for the liner/etch stop layer in damascene process is silicon nitride (Si3N4). However, silicon nitride has a high dielectric constant. To reduce the effective dielectric constant in the Cu damascene structure,
* Corresponding author. Tel.: C65 770 59 22; fax: C65 677 319 14. E-mail address: [email protected] (S. Balakumar). 0026-2692/$ - see front matter q 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2004.11.010
SiC:H which is prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source, has been studied as the dielectric copper diffusion barrier [1–3]. Owing to the mechanical properties of low-k materials, peeling and delamination of the dielectric film and Cu lines is one of the most critical challenges in developing a production-worthy chemical mechanical planarization (CMP) process for the integration of the Cu damascene process. In this paper, the mechanism of the translation of etch-stop stress to the occurrence of delamination at the Cu/low k interface is briefly discussed. Si3N4 and SiC:H used as liners for interconnect integration will be compared. In order to integrate Cu into interconnects, the mechanism of micro-structural evolution in the Cu seed layer as a result of stress accumulation with the use of various diffusion barrier materials must be understood, and delamination between Cu and dielectric film must be suppressed by enhancing the adaptability to CMP
750
G. Wang et al. / Microelectronics Journal 36 (2005) 749–753
conditions. In this paper, the role of diffusion liner material on the enhancement of the adhesion strength of Cu seed to the underlying layers is also studied. 2. Experimental procedures Samples were prepared on (100)-oriented 8 00 Si wafers ˚ SiO2 film deposited by plasma enhanced that had a 5000 A ˚ chemical vapor deposition (PECVD), followed by 500 A ˚ diffusion barrier material (SiNx, or SiC:N), 5000 A SiOC, ˚ Ta barrier layer and Cu seed layer of 500 A ˚ were then 250 A deposited using self-ionized metal plasma (SIP) technique at room temperature without breaking vacuum. The seed layer showed a very strong (111) texture with no traceable existence of (200) texture as evidenced in previous works [4]. Electro-chemically plated of (ECP) 0.6 mm Cu layer is then performed on the Cu seed layer at room temperature. The wafers were then ramped up to annealing temperatures of 200 8C in pure N2 atmosphere at a ramp rate of 10 8C per min. Wafers were annealed for 30 min and cooled to room temperature to capture the film texture at each annealing temperature. The sheet resistance of the seed layer was measured by the four-point probe method using a 49-point scan on a Prometrix Omni map resistance measurement system. The Cu texture was characterized using X-ray diffraction (XRD) for crystallographic orientation, and atomic force microscopy (AFM) for surface morphology and roughness. The adhesion strength of the seed layer was determined by CSEM scanning micro-scratch tester (MST) under a progressive application of a unidirectional 0–30 N load. Film stress was determined by a KLA Tencor FLX2320 Thin Film Stress Measurement Instrument.
3. Results and discussion 3.1. XRD and texture studies of Cu seed layer Fig. 1 shows the comparison of Cu (111) intensity for the Cu seed layers when plated on two different diffusion barrier
materials. More grain growth in the (111) orientation was generally observed for Cu seed layer deposited on SiC:H liner, as compared to a reduced (111) orientation in Si3N4 material. A 123% enhancement in (111) was found when the thin seed layer was deposited on the low stress SiC:H liner. Texture develops as a consequence of the nucleation and the grain growth competition between the grains in strongly influenced by stress conditions developed on the Cu layer [5]. In this study, the (111) texture of Cu film is important in determining the reliability of the Cu interconnects [6,7]. Cu films having higher (111) texture indicated a better Cu/ barrier interface and a better film texture occurring simultaneously on a Cu interconnect [7]. The predominant mechanism determining grain orientation is surface energy minimization in low stress Cu films, while the grain orientation is influenced by strain energy minimization for films with high initial stress state [5]. Surface energy minimization usually results in a (111) out of plane oriented grain structure. A small weakening of the (111) texture in the film on high stress barrier layers was observed. The relative peak intensities of the (111) peaks from Fig. 1 indicate that the film texture is weaker when Cu is plated on SiNx bearing higher film stress. The greater the mismatch within the barrier layers and at the interface, the higher the stresses in the Cu film resulted and this has been verified against previously reported result [7]. There is an increase in strain energy of Cu deposited on high stress Si3N4 because of this greater mismatch, and hence (200) out of plane becomes the preferred grain structure due to strain energy minimization criterion. Lower stress on the barrier film enhances interaction between the Cu film and the underlying dielectric. The minimization of the interfacial energy can take place on the (111) planes, resulting in an enhancement of (111) nucleation, and a reduction of random orientations. It has also been reported that the fiber texture measurements confirm the strength of Cu bond [8]. This being the case, it further confirms that the adhesion strength at the Cu interface is strongest with SiC:H as the liner, in comparison to Si3N4 barrier.
˚ Cu seed layers deposited on Si3N4 and SiC:H Cu diffusion liners. Fig. 1. XRD results of (111) peak of 500 A
G. Wang et al. / Microelectronics Journal 36 (2005) 749–753
751
3.2. Grain size and surface roughness of Cu seed layer Agglomeration of Cu seed on the diffusion barrier materials was investigated using AFM analysis of an array of blanket wafers. The Cu seed layers were generally smooth and continuous on SiC:H materials as shown in Fig. 2a. The surface roughness (RMS) of the seed layer is 2.19 nm. However, the surface roughness of seed layer on nitride layer is 2.46 nm. Cu layer tended to ball up and form islands on the Ta barriers. The grain size and surface roughness were investigated in details. For Cu seed plated on Si3N4 layer, the roughness increased by 12.5%. This indicates that Cu/dielectric bonding was weakest and Cu atoms were free to diffuse, in favor of strain energy minimization, to form large islands. Cu/dielectric bonding which is slightly stronger on SiC:H, is strong enough at
˚ Cu seed layers on Si3N4 and Fig. 2. (a) AFM surface topography for 500 A SiC:H Cu diffusion liners. (b) AFM surface topography of ECP Cu on ˚ Cu seeds for Si3N4 and SiC:H Cu diffusion liners. 500 A
Fig. 3. Variation of average Cu seed and ECP Cu layer grain size.
the binding interface to hold Cu atoms in position during anneal, resulting in an almost continuous seed layer after anneal. In Fig. 2b, a reverse trend was observed when the ECP Cu was deposited. The surface roughness on SiC:H was significantly enhanced as a result of extensive agglomeration. The surface non-homogeneity, attributed to grain growth and elimination of grain boundaries as grains recrystallized at higher anneal temperature, was evident on the low stress barrier. Bimodal grain growth was observed on the SiC:H material, where growth of subpopulation of grains is favored, such that a few grains grow at the expense of a static matrix of parent grains. For the abnormally growing grains, there is a noticeable variation in the standard deviation. As illustrated in Fig. 3, grain size of the ECP Cu is larger on SiC:H barrier. The grain size of Cu ECP on SiC:H barrier is 1.04 mm, whereas it is 0.77 mm on Si3N4 barrier. Grain growth could be attributed to the overall stress affecting the properties of the layers [8]. Recrystallization was restrained by the stress imposed on Cu layer, thus, bimodal grain growth was limited in the Cu seed on Si3N4 barrier. We verified from the experiments that grain growth against the development of tensile stress was due to the reduction of
Fig. 4. Variation of average Cu seed and ECP Cu RMS roughness on Si3N4 and SiC:H liners.
752
G. Wang et al. / Microelectronics Journal 36 (2005) 749–753
Fig. 5. Sheet resistance as a function of liner for Cu seed and ECP Cu layer.
grain-boundary energy. And the grain-boundary energy was large enough to overcome the increase in strain energy and accumulated film stress during the grain growth. Fig. 4 shows that film roughness develops as a result of Cu agglomeration. Low stress Cu layer permits easy agglomeration of Cu. A very rough surface was observed in the layer deposited on nitride barrier because of the weak Cu interfacial bonding, which explained the large island formation. The roughness of Cu seed varied from 2.46 nm on nitride layer to 1.94 nm on a low stressed SiC:H layer. A more uniform grain feature was supported by the lower RMS roughness value of the Cu seed layer. Agglomeration changed the Cu film into a discontinuous layer on a low stress Cu layer deposited on SiC:H, as illustrated in Fig. 4. The effect of film stress accumulated from the diffusion barrier corresponded with the extent of grain growth on Cu layer. It has been verified here that, the low stress thin Cu layer is formed as a result of the Cu agglomeration.
3.3. Sheet resistance in Cu seed layer Resistivity of Cu layer can also be controlled by the (111) orientation. As shown in Fig. 5, the resistance decreased on Cu seed deposited on low stress SiC:H layer. Despite the larger Cu islands formed on nitride barrier, and resulting larger grains formation, voids formation due to the higher surface to bulk ratio in the thin Cu seed was inevitable and this accounted for its increased resistance. The increase in resistance was most likely due to poor Cu/barrier layer interfacial bonding which was further worsened by voids formation. With reference to Figs. 3 and 5, the faster the grains growth, the more resistance dropped and this agreed with reported studies [6]. Grain growth also led to a decrease in density of grain boundary which was responsible for higher resistance [9]. The decrease in resistance could also be explained by a decrease in the concentration of defects like vacancies and voids. In addition, ECP Cu layer is annealed to enhance
Fig. 6. Correlation between adhesion strength and stress in the Cu seed layer and ECP Cu layer.
G. Wang et al. / Microelectronics Journal 36 (2005) 749–753
grain growth and to release the stress. Grain is grown rapidly in the low stress layer. This result depicts clearly that stress and grain size of ECP layer is affected by the stress accumulated from the underlying layer of diffusion barrier. Finally, the improvement in the texture could also lead to a decrease in resistance because the misalignment between adjacent grains decreased. The reduction in grain intensity and hence grain boundaries by the formation of larger grains probably reduced the void-liked defects in the Cu seed and thus lowered its resistance. 3.4. Adhesion strength of Cu seed layers Enhancement of adhesion strength was essential for Cu interconnections, particularly after annealing to achieve higher removal rate in the CMP process [10,11]. The variation of adhesion strength with diffusion barrier on Cu seed and ECP Cu is shown in Fig. 6. It was evident that stress largely affected the layer properties and adhesion strength of Cu seed layer [12]. Much lower stress and higher adhesion strength can be attained in layers on SiC:H liner barrier, as shown in Fig. 6. The strength decreased from a normalized value of 1.0 on Cu seed deposited on SiC:H liner, as compared to 0.51 on Si3N4. The adhesion strength in a high stress layer decreased markedly. Tensile stress of Cu seed layer may increase as a result of island formation due to Cu atoms migration, because the film volume shrinks as the grain boundary area reduces. Since much lower adhesion strength is obtained in Cu seed on Si3N4 liner material, peeling and delamination is expected to occur frequently during the CMP. Delamination could be caused by the highly stressed Cu seed layer [13,14], as a result of larger thermal mismatches between Cu and its underlying layers. Difference in thermal coefficients of expansion between Cu and its underlying layers built up with increasing annealing temperature, resulting in a larger stress build-up on the Cu layer. Preparation of a low stress seed is required before electroplating. It has been shown from Fig. 5 that a low stress and low resistivity Cu layer can be electroplated from a low stress seed. Very strong adhesion was attained when SiC:H was used as the diffusion barrier. Thus, enhancement of the critical pressure that can be applied to the Cu layer can be realized with increasing adhesion strength and decreasing stress in the Cu layer.
4. Conclusions An understanding of the degradation of adhesion strength at the Cu/barrier interfaces and Cu layer properties with Cu diffusion barrier layer was studied. This paper described the adhesion strength and stress of Cu layers in relation to
753
delamination during CMP of Cu interconnections. The subsequent plated Cu seed and ECP Cu layer on underlying SiC:H liner resulted in the lowest stress which is highly desirable from a reliability point of view. In addition, the minimal agglomeration of Cu seed on this barrier material indicates a strong bonding exists between Cu/low-k dielectric at the interface. This should enhance adhesion and minimize electromigration of Cu interconnection. The lower degree of Cu seed agglomeration suggests that the use of SiC:H, in comparison to primary liner candidate, Si3N4, may be more highly desirable, and it is highly recommended for the Cu interconnection as a diffusion barrier and etch-stop layer. On the whole, a lower dielectric constant SiC:H whose coefficient of thermal expansion matched closely to the underlying and overlying layers in Cu interconnects was essential for enhancing adhesion strength and interfacial bonding for the overall integrity of the Cu metallization structure. Acknowledgements This work was funded under IME project IME/03-440001. References [1] M.J. Loboda, J.A. Seifferly, C.M. Grove, R.F. Schneider, Materials Research Society Symposium Proceedings V447 (1997) 145–151. [2] P. Xu, K. Huang, A. Patel, S. Rathi, B. Tang, J. Ferguson, J. Huang, C. Ngai, International Interconnection Technology Conference 99 (1999) 109–112. [3] S.G. Lee, Y.J. Kim, S.P. Lee, H.S. Oh, S.J. Lee, M. Kim, J.H. Kim, H.J. Shin, J.G. Hong, H.D. Lee, H.K. Kang, Japan Journal of Applied Physics V40 (2001) 2663–2668. [4] H. Lee, S.D. Lopatin, S.S. Wong, MRS Fall Meeting, Symposium A, Paper A1.9 Boston (1998). [5] L. Graham, T. Ritxdorf, Semiconductor Fabtech Edition (2001) 279– 282. [6] T. Muppidi, D.P. Field, J. Sanchez, Barrier layer, geometric and alloying effects on the microstructure and texture of copper thin films and damascene lines for interconnect applications (Pending submission). [7] L. Graham, T. Ritxdorf, Semiconductor Fabtech Edition (2001) 279– 282. [8] T. Hara, Y. Shimura, Proceedings of 20th VMIC Conference (2003) 303–306. [9] Q.T. Jiang, R. Faust, H.R. Lam, J. Mucha, IEEE IITC 99-125-127 (1999). [10] C.H. Seah, S. Miradha, L.H. Chan, Journal of Vacuum Science Technology A 17 (4) (1999) 1963–1967. [11] T. Hara, Y. Shimura, Proceedings of 20th VMIC Conference (2003) 303–306. [12] T. Hara, H. Toida, Y. Shimura, Electrochemical and Solid State Letters 6 (7) (2003) G98–G100. [13] T. Hara, Y. Shimura, H. Toida, Electrochemical and Solid State Letters 6 (7) (2003) C97–C99. [14] T. Hara, K. Sakata, Electrochemical and Solid State Letters (2001) C81–C84.
Enhancement of adhesion strength of Cu layer with low dielectric constant SiC:H liners in Cu interconnects Grace Wanga,b, S. Balakumara,*, S.C. Hweea, Rakesh Kumara, T. Harac a Institute of Microelectronics, 11 Science Park Road, Science Park II, Singapore 117685 Department of Electrical and Computer Engineering, National University of Singapore, Singapore c Hosei University, Tokyo, Japan
b
Received 2 August 2004; received in revised form 2 November 2004; accepted 9 November 2004 Available online 18 January 2005
Abstract One of the primary candidates for the liner/etch stop layer in damascene process is silicon nitride (Si3N4). However, silicon nitride has a high dielectric constant of 7.0. To reduce the effective dielectric constant in Copper (Cu) damascene structure, dielectric SiC:H (prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source) as the Cu diffusion barrier was studied. The dielectric constant of SiC:H used is 4.2. A systematic study was made on the properties of liner material and electro-chemically plated (ECP) Cu to enhance the adhesion strength in Cu/low-dielectric constant (k) multilevel interconnects. Though the effects of as Si3N4 the liner have been much studied in the past, less is known about the relation between adhesion strength of ECP Cu layer and physical vapor deposited (PVD) Cu ˚ . The annealing of Cu seed layer was carried out at 200 8C in N2 ambient for 30 min was carried out seeds, with seed thickness below 1000 A to study the impact on adhesion strength and the microstructure evolution on the adhesion between ECP Cu and its barrier layer. In the study, our claim that SiC:H barrier/etch stop layer is essential for replacing conventional Si3N4 layer in enhancing adhesion strength and interfacial bonding between Cu/dielectric interconnects. q 2004 Elsevier Ltd. All rights reserved. Keywords: Adhesion strength; Cu layer; Trimethylsilane; Cu diffusion liner
1. Introduction Cu is being extensively adopted in deep-submicron ultralarge scale-integration (ULSI) interconnection as it offers both higher conductivity and better electromigration resistance over Al alloys. However, many process integration issues exist, one of which is the rapid drift of Cu ions in SiO2 under the influence of an electric field. Cu diffusion in dielectric may give rise to an unanticipated yield or reliability problem. Hence, a diffusion drift barrier is necessary to prevent Cu movement into interlevel dielectric. The primary candidate for the liner/etch stop layer in damascene process is silicon nitride (Si3N4). However, silicon nitride has a high dielectric constant. To reduce the effective dielectric constant in the Cu damascene structure,
* Corresponding author. Tel.: C65 770 59 22; fax: C65 677 319 14. E-mail address: [email protected] (S. Balakumar). 0026-2692/$ - see front matter q 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2004.11.010
SiC:H which is prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source, has been studied as the dielectric copper diffusion barrier [1–3]. Owing to the mechanical properties of low-k materials, peeling and delamination of the dielectric film and Cu lines is one of the most critical challenges in developing a production-worthy chemical mechanical planarization (CMP) process for the integration of the Cu damascene process. In this paper, the mechanism of the translation of etch-stop stress to the occurrence of delamination at the Cu/low k interface is briefly discussed. Si3N4 and SiC:H used as liners for interconnect integration will be compared. In order to integrate Cu into interconnects, the mechanism of micro-structural evolution in the Cu seed layer as a result of stress accumulation with the use of various diffusion barrier materials must be understood, and delamination between Cu and dielectric film must be suppressed by enhancing the adaptability to CMP
750
G. Wang et al. / Microelectronics Journal 36 (2005) 749–753
conditions. In this paper, the role of diffusion liner material on the enhancement of the adhesion strength of Cu seed to the underlying layers is also studied. 2. Experimental procedures Samples were prepared on (100)-oriented 8 00 Si wafers ˚ SiO2 film deposited by plasma enhanced that had a 5000 A ˚ chemical vapor deposition (PECVD), followed by 500 A ˚ diffusion barrier material (SiNx, or SiC:N), 5000 A SiOC, ˚ Ta barrier layer and Cu seed layer of 500 A ˚ were then 250 A deposited using self-ionized metal plasma (SIP) technique at room temperature without breaking vacuum. The seed layer showed a very strong (111) texture with no traceable existence of (200) texture as evidenced in previous works [4]. Electro-chemically plated of (ECP) 0.6 mm Cu layer is then performed on the Cu seed layer at room temperature. The wafers were then ramped up to annealing temperatures of 200 8C in pure N2 atmosphere at a ramp rate of 10 8C per min. Wafers were annealed for 30 min and cooled to room temperature to capture the film texture at each annealing temperature. The sheet resistance of the seed layer was measured by the four-point probe method using a 49-point scan on a Prometrix Omni map resistance measurement system. The Cu texture was characterized using X-ray diffraction (XRD) for crystallographic orientation, and atomic force microscopy (AFM) for surface morphology and roughness. The adhesion strength of the seed layer was determined by CSEM scanning micro-scratch tester (MST) under a progressive application of a unidirectional 0–30 N load. Film stress was determined by a KLA Tencor FLX2320 Thin Film Stress Measurement Instrument.
3. Results and discussion 3.1. XRD and texture studies of Cu seed layer Fig. 1 shows the comparison of Cu (111) intensity for the Cu seed layers when plated on two different diffusion barrier
materials. More grain growth in the (111) orientation was generally observed for Cu seed layer deposited on SiC:H liner, as compared to a reduced (111) orientation in Si3N4 material. A 123% enhancement in (111) was found when the thin seed layer was deposited on the low stress SiC:H liner. Texture develops as a consequence of the nucleation and the grain growth competition between the grains in strongly influenced by stress conditions developed on the Cu layer [5]. In this study, the (111) texture of Cu film is important in determining the reliability of the Cu interconnects [6,7]. Cu films having higher (111) texture indicated a better Cu/ barrier interface and a better film texture occurring simultaneously on a Cu interconnect [7]. The predominant mechanism determining grain orientation is surface energy minimization in low stress Cu films, while the grain orientation is influenced by strain energy minimization for films with high initial stress state [5]. Surface energy minimization usually results in a (111) out of plane oriented grain structure. A small weakening of the (111) texture in the film on high stress barrier layers was observed. The relative peak intensities of the (111) peaks from Fig. 1 indicate that the film texture is weaker when Cu is plated on SiNx bearing higher film stress. The greater the mismatch within the barrier layers and at the interface, the higher the stresses in the Cu film resulted and this has been verified against previously reported result [7]. There is an increase in strain energy of Cu deposited on high stress Si3N4 because of this greater mismatch, and hence (200) out of plane becomes the preferred grain structure due to strain energy minimization criterion. Lower stress on the barrier film enhances interaction between the Cu film and the underlying dielectric. The minimization of the interfacial energy can take place on the (111) planes, resulting in an enhancement of (111) nucleation, and a reduction of random orientations. It has also been reported that the fiber texture measurements confirm the strength of Cu bond [8]. This being the case, it further confirms that the adhesion strength at the Cu interface is strongest with SiC:H as the liner, in comparison to Si3N4 barrier.
˚ Cu seed layers deposited on Si3N4 and SiC:H Cu diffusion liners. Fig. 1. XRD results of (111) peak of 500 A
G. Wang et al. / Microelectronics Journal 36 (2005) 749–753
751
3.2. Grain size and surface roughness of Cu seed layer Agglomeration of Cu seed on the diffusion barrier materials was investigated using AFM analysis of an array of blanket wafers. The Cu seed layers were generally smooth and continuous on SiC:H materials as shown in Fig. 2a. The surface roughness (RMS) of the seed layer is 2.19 nm. However, the surface roughness of seed layer on nitride layer is 2.46 nm. Cu layer tended to ball up and form islands on the Ta barriers. The grain size and surface roughness were investigated in details. For Cu seed plated on Si3N4 layer, the roughness increased by 12.5%. This indicates that Cu/dielectric bonding was weakest and Cu atoms were free to diffuse, in favor of strain energy minimization, to form large islands. Cu/dielectric bonding which is slightly stronger on SiC:H, is strong enough at
˚ Cu seed layers on Si3N4 and Fig. 2. (a) AFM surface topography for 500 A SiC:H Cu diffusion liners. (b) AFM surface topography of ECP Cu on ˚ Cu seeds for Si3N4 and SiC:H Cu diffusion liners. 500 A
Fig. 3. Variation of average Cu seed and ECP Cu layer grain size.
the binding interface to hold Cu atoms in position during anneal, resulting in an almost continuous seed layer after anneal. In Fig. 2b, a reverse trend was observed when the ECP Cu was deposited. The surface roughness on SiC:H was significantly enhanced as a result of extensive agglomeration. The surface non-homogeneity, attributed to grain growth and elimination of grain boundaries as grains recrystallized at higher anneal temperature, was evident on the low stress barrier. Bimodal grain growth was observed on the SiC:H material, where growth of subpopulation of grains is favored, such that a few grains grow at the expense of a static matrix of parent grains. For the abnormally growing grains, there is a noticeable variation in the standard deviation. As illustrated in Fig. 3, grain size of the ECP Cu is larger on SiC:H barrier. The grain size of Cu ECP on SiC:H barrier is 1.04 mm, whereas it is 0.77 mm on Si3N4 barrier. Grain growth could be attributed to the overall stress affecting the properties of the layers [8]. Recrystallization was restrained by the stress imposed on Cu layer, thus, bimodal grain growth was limited in the Cu seed on Si3N4 barrier. We verified from the experiments that grain growth against the development of tensile stress was due to the reduction of
Fig. 4. Variation of average Cu seed and ECP Cu RMS roughness on Si3N4 and SiC:H liners.
752
G. Wang et al. / Microelectronics Journal 36 (2005) 749–753
Fig. 5. Sheet resistance as a function of liner for Cu seed and ECP Cu layer.
grain-boundary energy. And the grain-boundary energy was large enough to overcome the increase in strain energy and accumulated film stress during the grain growth. Fig. 4 shows that film roughness develops as a result of Cu agglomeration. Low stress Cu layer permits easy agglomeration of Cu. A very rough surface was observed in the layer deposited on nitride barrier because of the weak Cu interfacial bonding, which explained the large island formation. The roughness of Cu seed varied from 2.46 nm on nitride layer to 1.94 nm on a low stressed SiC:H layer. A more uniform grain feature was supported by the lower RMS roughness value of the Cu seed layer. Agglomeration changed the Cu film into a discontinuous layer on a low stress Cu layer deposited on SiC:H, as illustrated in Fig. 4. The effect of film stress accumulated from the diffusion barrier corresponded with the extent of grain growth on Cu layer. It has been verified here that, the low stress thin Cu layer is formed as a result of the Cu agglomeration.
3.3. Sheet resistance in Cu seed layer Resistivity of Cu layer can also be controlled by the (111) orientation. As shown in Fig. 5, the resistance decreased on Cu seed deposited on low stress SiC:H layer. Despite the larger Cu islands formed on nitride barrier, and resulting larger grains formation, voids formation due to the higher surface to bulk ratio in the thin Cu seed was inevitable and this accounted for its increased resistance. The increase in resistance was most likely due to poor Cu/barrier layer interfacial bonding which was further worsened by voids formation. With reference to Figs. 3 and 5, the faster the grains growth, the more resistance dropped and this agreed with reported studies [6]. Grain growth also led to a decrease in density of grain boundary which was responsible for higher resistance [9]. The decrease in resistance could also be explained by a decrease in the concentration of defects like vacancies and voids. In addition, ECP Cu layer is annealed to enhance
Fig. 6. Correlation between adhesion strength and stress in the Cu seed layer and ECP Cu layer.
G. Wang et al. / Microelectronics Journal 36 (2005) 749–753
grain growth and to release the stress. Grain is grown rapidly in the low stress layer. This result depicts clearly that stress and grain size of ECP layer is affected by the stress accumulated from the underlying layer of diffusion barrier. Finally, the improvement in the texture could also lead to a decrease in resistance because the misalignment between adjacent grains decreased. The reduction in grain intensity and hence grain boundaries by the formation of larger grains probably reduced the void-liked defects in the Cu seed and thus lowered its resistance. 3.4. Adhesion strength of Cu seed layers Enhancement of adhesion strength was essential for Cu interconnections, particularly after annealing to achieve higher removal rate in the CMP process [10,11]. The variation of adhesion strength with diffusion barrier on Cu seed and ECP Cu is shown in Fig. 6. It was evident that stress largely affected the layer properties and adhesion strength of Cu seed layer [12]. Much lower stress and higher adhesion strength can be attained in layers on SiC:H liner barrier, as shown in Fig. 6. The strength decreased from a normalized value of 1.0 on Cu seed deposited on SiC:H liner, as compared to 0.51 on Si3N4. The adhesion strength in a high stress layer decreased markedly. Tensile stress of Cu seed layer may increase as a result of island formation due to Cu atoms migration, because the film volume shrinks as the grain boundary area reduces. Since much lower adhesion strength is obtained in Cu seed on Si3N4 liner material, peeling and delamination is expected to occur frequently during the CMP. Delamination could be caused by the highly stressed Cu seed layer [13,14], as a result of larger thermal mismatches between Cu and its underlying layers. Difference in thermal coefficients of expansion between Cu and its underlying layers built up with increasing annealing temperature, resulting in a larger stress build-up on the Cu layer. Preparation of a low stress seed is required before electroplating. It has been shown from Fig. 5 that a low stress and low resistivity Cu layer can be electroplated from a low stress seed. Very strong adhesion was attained when SiC:H was used as the diffusion barrier. Thus, enhancement of the critical pressure that can be applied to the Cu layer can be realized with increasing adhesion strength and decreasing stress in the Cu layer.
4. Conclusions An understanding of the degradation of adhesion strength at the Cu/barrier interfaces and Cu layer properties with Cu diffusion barrier layer was studied. This paper described the adhesion strength and stress of Cu layers in relation to
753
delamination during CMP of Cu interconnections. The subsequent plated Cu seed and ECP Cu layer on underlying SiC:H liner resulted in the lowest stress which is highly desirable from a reliability point of view. In addition, the minimal agglomeration of Cu seed on this barrier material indicates a strong bonding exists between Cu/low-k dielectric at the interface. This should enhance adhesion and minimize electromigration of Cu interconnection. The lower degree of Cu seed agglomeration suggests that the use of SiC:H, in comparison to primary liner candidate, Si3N4, may be more highly desirable, and it is highly recommended for the Cu interconnection as a diffusion barrier and etch-stop layer. On the whole, a lower dielectric constant SiC:H whose coefficient of thermal expansion matched closely to the underlying and overlying layers in Cu interconnects was essential for enhancing adhesion strength and interfacial bonding for the overall integrity of the Cu metallization structure. Acknowledgements This work was funded under IME project IME/03-440001. References [1] M.J. Loboda, J.A. Seifferly, C.M. Grove, R.F. Schneider, Materials Research Society Symposium Proceedings V447 (1997) 145–151. [2] P. Xu, K. Huang, A. Patel, S. Rathi, B. Tang, J. Ferguson, J. Huang, C. Ngai, International Interconnection Technology Conference 99 (1999) 109–112. [3] S.G. Lee, Y.J. Kim, S.P. Lee, H.S. Oh, S.J. Lee, M. Kim, J.H. Kim, H.J. Shin, J.G. Hong, H.D. Lee, H.K. Kang, Japan Journal of Applied Physics V40 (2001) 2663–2668. [4] H. Lee, S.D. Lopatin, S.S. Wong, MRS Fall Meeting, Symposium A, Paper A1.9 Boston (1998). [5] L. Graham, T. Ritxdorf, Semiconductor Fabtech Edition (2001) 279– 282. [6] T. Muppidi, D.P. Field, J. Sanchez, Barrier layer, geometric and alloying effects on the microstructure and texture of copper thin films and damascene lines for interconnect applications (Pending submission). [7] L. Graham, T. Ritxdorf, Semiconductor Fabtech Edition (2001) 279– 282. [8] T. Hara, Y. Shimura, Proceedings of 20th VMIC Conference (2003) 303–306. [9] Q.T. Jiang, R. Faust, H.R. Lam, J. Mucha, IEEE IITC 99-125-127 (1999). [10] C.H. Seah, S. Miradha, L.H. Chan, Journal of Vacuum Science Technology A 17 (4) (1999) 1963–1967. [11] T. Hara, Y. Shimura, Proceedings of 20th VMIC Conference (2003) 303–306. [12] T. Hara, H. Toida, Y. Shimura, Electrochemical and Solid State Letters 6 (7) (2003) G98–G100. [13] T. Hara, Y. Shimura, H. Toida, Electrochemical and Solid State Letters 6 (7) (2003) C97–C99. [14] T. Hara, K. Sakata, Electrochemical and Solid State Letters (2001) C81–C84.