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Effects of Cu surface roughness on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40 nm technology node and beyond
Microelectronic Engineering 92 (2012) 115–118
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Effects of Cu surface roughness on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40 nm technology node and beyond W.C. Lin ⇑, Jack Lin, T.C. Tsai, C.M. Hsu, C.C. Liu, J.F. Lin, C.C. Hwang, J.Y. Wu United Microelectronics Corp., Advanced Technology Development Division, No. 18, Nanke 2nd Rd., Tainan Science Park, Taiwan, ROC
a r t i c l e
i n f o
Article history: Available online 24 April 2011 Keyword: Cu surface roughness on TDDB influence by CMP
a b s t r a c t The time-dependent dielectric breakdown (TDDB) reliability performance of back-end-of-line (BEOL) structures has been demonstrated to obviously correlate with the surface roughness of Cu metal line. Larger Cu surface roughness could induce the cracking of metal capping layer and the degradation of TDDB. More ultra-low k (ULK) polishing amount and higher de-ionized water (DIW) dilute ratio post-Cu chemical mechanical polishing (Cu–CMP) chemical cleaning process have been developed to reduce Cu surface roughness for better TDDB performance read-out. An optimized post-cleaning process with adjusted brush gap condition has been demonstrated to eliminate microscratch level with the improvements of the yield of Cu wide line serpent open test structures and TDDB performance at 28 nm technology node. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction The Cu damascene with direct polished porous type ultra-low k (ULK) interconnects have been introduced to realize the high performance of the resistance–capacitance (RC) delay for 45 nm technology node and beyond. However, the reliability issues of the backend-of-line (BEOL) structures, especially for time-dependent dielectric breakdown (TDDB), have also become drastically important because of the incorporation of ULK dielectric materials in Cu interconnects. Furthermore, the interface integrity among the low-k dielectric, the Cu metal surface and the diffusion capping layer has also been pointed out to be the key factor to impact the TDDB performance because of the minimized feature size and the relative fragile ULK film properties. Lots of research articles have discussed how the dielectric geometry factors such as metal line width, line edge roughness and the electric field factors, to affect the TDDB lift-time [1–4]. The cleaning chemical solution types post-copper chemical mechanical polishing (Cu–CMP) have been derived to significantly influence the TDDB performance [5–7]. The time delay between CMP and barrier deposition has also shown an important role in TDDB [8,9]. Inappropriate Cu metal-to-metal lines spacing control across whole wafers could normally induce the varied TDDB reliability performance [10]. Fig. 1 shows the early failure sites of TDDB test usually found at the wafer edge areas with narrowed ULK isolation spacing between Cu lines. On the other hand, the Cu roughness and microscratches of polished surface are believed to play a crucial role to influence the TDDB as device scaling down to be sub-45 nm [11–14]. In this paper, the effects of the Cu surface ⇑ Corresponding author. Tel.: +886 6 5054888x8613257; fax: +886 6 5050960. E-mail address: [email protected] (W.C. Lin). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.04.057
roughness on TDDB and the process optimization of Cu–CMP for the reduction of Cu surface roughness have been evaluated to meet the process requirement of 28 nm technology node. 2. Experimental Three hundred millimeters Cu damascene interconnect structures were constructed by 40/28 nm metal hard mask/trench first scheme with ULK dielectric film (k value 2.5), physical vapor deposition (PVD) Cu barrier (Ta/TaN) and seed layers, Cu electroplating, Cu–CMP and nitrogen doped silicon carbide (SiCN) dielectric barrier layer. The Cu–CMP process was carrier out a rotary type polisher with three polishing platens. Two different kinds of colloidal silica based slurries were utilized to polish off the excess Cu film on platen one and platen two with hard pad and the Cu barrier/metal hard mask/ULK layers on platen three with soft pad, respectively. Alkaline based post-clean chemical solution was applied in brush clean steps to clean the polished wafers. The Cu surface roughness was characterized by high-resolution atomic force profiler on 50 50 lm Cu pad area and inspected by top viewed scanning electron microscopy (SEM) micrographs on Cu dense line structures after pattern wafer polishing and cleaning. The ULK thickness post-Cu–CMP was measured by KLA-F5x thin film measurement system. The defect inspection of the Cu roughness was conducted on KLA-Tencor 2815. Breakdown behavior, including voltage rapid dielectric breakdown (VRDB) and TDDB tests, were probed on a combed type test structure comprised of three Cu and one top Al interconnect layers. The TDDB test structure is subjected to a wafer-level constant voltage test at a temperature of 125 °C and positive bias voltage ranging from 19 to 28 V. The failure location was detected by optical beam induced resistance
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Fig. 1. (a and b) Time-dependent dielectric breakdown (TDDB) early failure sites were found at the wafer edge dies with narrowed metal line spacing conditions.
Fig. 3. Effects of the Cu surface roughness on voltage rapid dielectric breakdown (VRDB) performance.
change (OBIRCH) and then applied transmission electron microscopy (TEM) to do the failure mode analysis. 3. Results and discussion 3.1. Correlation between TDDB and Cu surface roughness Figs. 2–4 show the dense metal lines with smaller Cu surface roughness condition can result in the better performance of VRDB and TDDB performance. The top viewed SEM micrographs can quickly do qualitative judgment on the Cu surface roughness, as indicated in Fig. 2. Figs. 3 and 4 demonstrate the VRDB and TDDB performance can be significantly improved as the average Cu surface roughness reduced from 6.4 to 3.7 Å, respectively. More smooth Cu surface condition derives the better TDDB reliability performance. Obvious film cracking of the metal capping layer at the top corner of Cu lines and the Cu penetration phenomenon
Fig. 4. Effects of the Cu surface roughness on TDDB performance.
Fig. 5. Cracking of the metal capping layer was found at the top corner of Cu line induced by poor Cu surface roughness conditions.
Fig. 6. Top viewed SEM micrographs of Cu surface roughness for different remaining ULK thicknesses.
Fig. 2. SEM top viewed images for (a) bad and (b) good Cu surface roughness conditions.
on the top surface of the ULK film at the TDDB test failure areas are shown in Fig. 5. More roughing Cu surface condition could induce the cracking of the metal capping film because of poor step coverage of capping film. This film cracking area will become a
W.C. Lin et al. / Microelectronic Engineering 92 (2012) 115–118
117
Fig. 7. ULK removal amount thickness as a function of direct ULK polishing time. Fig. 11. Effects of the Cu surface roughness on the yield of defect density (D.D.).
3.2. Effects of the ULK film polishing amount on TDDB
Fig. 8. Bad die ratio of the Cu surface roughness as a function of removal amount of ULK layer.
Figs. 6–9 show more direct ULK removal amount can significantly eliminate Cu surface roughness and improve TDDB performance. An appropriate removal amount of ULK layer is needed for TDDB reliability improvement. The Cu line roughness decreases as increasing polishing amount of ULK film, as derived in Fig. 6. More ULK polishing condition on soft pad could overcome the deeper Cu line microscratch and roughness profile post polishing off the excess Cu film on hard pad. Figs. 7 and 8 indicate the ULK polishing rate was changed to be lower with better Cu surface roughness as polishing into the region of ULK film with lower k-value. Lower bad die ratio (BD%) of Cu surface roughness is strongly correlated to the more ULK polishing amount due to the benefit of soft pad, as demonstrated in Fig. 8. Fig. 9 shows the T63.2% of TDDB life time, stressed at 23 and 25 V test conditions, decreases as increasing remaining ULK thickness post Cu–CMP process. 3.3. Effect of post clean chemical DIW dilute ratio (D.R.) on TDDB Figs. 10–12 indicate more DIW dilute ratio of post-cleaning chemical solution is helpful to improve TDDB and the yield of the defect density (D.D.). The Cu surface roughness decreases with
Fig. 9. T 63.2% TDDB life time at 23 and 25 V test conditions as a function of remaining ULK thickness.
week point to create the diffusion path of Cu ions and result in the Cu bridge issue post-TDDB test due to Cu penetration into the interface between ULK and capping layer. Therefore, how to eliminate Cu surface roughness is very crucial to improve the TDDB reliability performance for direct polishing ULK dielectric Cu interconnects.
Fig. 12. Effects of the DIW dilute ratio on TDDB performance.
Fig. 10. Top viewed SEM micrographs of the Cu surface roughness for different DIW dilute ratios of cleaning chemical solution.
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Fig. 13. The defect dies percentage of the Cu microscratch and fall on particle for different brush gap cleaning conditions at 28 nm products.
microscratch and surface roughness at 28 nm technology node. An optimized post cleaning process with adjusted brush gap condition has been developed to effectively reduce microscratch level without suffering fall on particle performance, as shown in Fig. 13. Fig. 14 indicates the failure count of the M2 Cu line serpent open can be dramatically reduced at wide metal areas. The rootcause of upper metal line broken issue is induced by the microscratch created at underneath metal layer. The microscratch of metal lines could result in the depth of focus (DOF) limitation of lithography process on upper Cu metal areas. A promising TDDB performance can be demonstrated for an optimized brush gap condition, as demonstrated in Fig. 15. These results indicate not only Cu surface roughness, but also microscratch can significantly impact the reliability performance of TDDB. 4. Conclusions
Fig. 14. Effects of the brush gap condition on the failure count of the metal two Cu lines open.
The correlation of TDDB reliability failure with the microscratches and Cu surface roughness generated post-Cu–CMP process were identified in the study. The microscratch and larger Cu surface roughness could induce the film cracking of the SiCN capping layers. The Cu-ion migration phenomenon due to the cracking of capping layer results in the degradation of TDDB lifetime. The poor Cu surface roughness can be recovered by polishing more ULK film and optimized post-Cu–CMP brush cleaning conditions. Reducing post-clean chemical etch rate with higher DIW dilute ratio can effective eliminate Cu surface roughness. An optimized brush gap chemical cleaning condition without fall on particle concern is not only for reducing the Cu surface roughness with TDDB improvement but also for minimizing the microscratches with metal line open reduction. The reduction of microscratch can dramatically retard the failure count of the metal line open on wide metal areas. The Cu line broken issue is easily induced by the microscratch created at underneath metal layer due to the DOF limitation of the lithography process on upper Cu metal areas. References
Fig. 15. Effects of the brush gap condition on TDDB performance.
[1] [2] [3] [4] [5]
increasing the DIW dilute ratio of cleaning chemical solution, as shown in Fig. 10. The graining boundaries of the Cu lines would be attacked to result in poor Cu surface roughness as implementing a higher concentration of cleaning chemical solution to remove the fall on particles. Fig. 11 demonstrates the yield of the defect density is in inverse proportion to the degree of Cu line roughness. Better TDDB performance is improved again as reducing Cu surface roughness with more DIW dilute ratio, as demonstrated in Fig. 12. Actually, increasing DIW dilute ratio could impact the cleaning efficiency of the fall on particles with the residues of the slurry abrasives, inhibitors and byproducts. Therefore, how to overall optimize the brushing condition with appropriate concentration of the cleaning chemical is very important for a robust Cu–CMP process development. 3.4. Effect of cleaning brush gap on TDDB Figs. 13–15 demonstrate the brush gap during post Cu–CMP cleaning plays a crucial rule to influence the performance of Cu
[6] [7] [8] [9] [10] [11] [12]
[13] [14]
J.Y. Kim, E.T. Ogawa, Joe W. McPherson, IEEE IRPS Proceedings (2007) 399. F. Chen, M. Shinosky, IEEE Transactions on Electron Devices (2009) 2. G.S. Haase, IEEE IRPS Proceedings (2008) 556. M. Vilmay, D. Roy, C. Monget, F. Volpi, J. Chaix, IEEE Transactions on Device and Materials Reliability (2009) 120. C.L. Hsu, K.T. Lu, W.C. Lin, J.C. Lin, C.H. Chen, T.C. Tsai, Climbing Huang, J.Y. Wu, D.C. Perng, IEEE IRPS Proceedings (2010) 918. J. Noguchi, N. Konishi, Y. Yamada, IEEE Transactions on Electron Devices (2005) 934. M.N. Chang, Robin C.J. Wang, C.C. Chiu, Wu. Kenneth, IEEE IRPS Proceedings (2009) 619. J. Noguchi, N. Miura, M. Kubo, T. Tamaru, H. Yamaguchi, N. Hamada, K. Makabe, R. Tsuneda, K. Takeda, IEEE IRPS Proceedings (2003) 287. K. Jow, G.B. Alers, M. Sanganeria, G. Harm, H. Fu, X. Tang, G. Kooi, G.W. Ray, M. Danek, IEEE IRPS Proceedings (2003) 598. F. Chen, P. McLaughlin, J. Gambino, E. Wu, J. Demarest, D. Meatyard, M. Shinosky, IEEE IRPS Proceedings (2007) 382. C.L. Hsu, Welch Lin, C.W. Hsu, J.C. Lin, T.C. Tsai, C.C. Huang, J.Y. Wu, ESC Transactions (2010) 99. L. Arnaud, D. Galpin, S. Chhun, C. Monget, E. Richard, D. Roy, C. Besset, M. Vilmay, L. Doyen, P. Waltz, E. Petitprez, F. Terrier, G. Imbert, Y. Le Friec, IEEE IITC Proceedings (2009) 179. W. Liu, Y.K. Lim, F. Zhang, W.Y. Zhang, C.Q. Chen, B.C. Zhang, J.B. Tan, D.K. Sohn, L.C. Hsia, IEEE IRPS Proceedings (2009) 613. N. Heylen, E. Camerotto, H. Volders, Y. Travaly, G. Vereecke, G.P. Beyer, Z. Tokei, IEEE IITC Proceedings (2010) 1.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Effects of Cu surface roughness on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40 nm technology node and beyond W.C. Lin ⇑, Jack Lin, T.C. Tsai, C.M. Hsu, C.C. Liu, J.F. Lin, C.C. Hwang, J.Y. Wu United Microelectronics Corp., Advanced Technology Development Division, No. 18, Nanke 2nd Rd., Tainan Science Park, Taiwan, ROC
a r t i c l e
i n f o
Article history: Available online 24 April 2011 Keyword: Cu surface roughness on TDDB influence by CMP
a b s t r a c t The time-dependent dielectric breakdown (TDDB) reliability performance of back-end-of-line (BEOL) structures has been demonstrated to obviously correlate with the surface roughness of Cu metal line. Larger Cu surface roughness could induce the cracking of metal capping layer and the degradation of TDDB. More ultra-low k (ULK) polishing amount and higher de-ionized water (DIW) dilute ratio post-Cu chemical mechanical polishing (Cu–CMP) chemical cleaning process have been developed to reduce Cu surface roughness for better TDDB performance read-out. An optimized post-cleaning process with adjusted brush gap condition has been demonstrated to eliminate microscratch level with the improvements of the yield of Cu wide line serpent open test structures and TDDB performance at 28 nm technology node. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction The Cu damascene with direct polished porous type ultra-low k (ULK) interconnects have been introduced to realize the high performance of the resistance–capacitance (RC) delay for 45 nm technology node and beyond. However, the reliability issues of the backend-of-line (BEOL) structures, especially for time-dependent dielectric breakdown (TDDB), have also become drastically important because of the incorporation of ULK dielectric materials in Cu interconnects. Furthermore, the interface integrity among the low-k dielectric, the Cu metal surface and the diffusion capping layer has also been pointed out to be the key factor to impact the TDDB performance because of the minimized feature size and the relative fragile ULK film properties. Lots of research articles have discussed how the dielectric geometry factors such as metal line width, line edge roughness and the electric field factors, to affect the TDDB lift-time [1–4]. The cleaning chemical solution types post-copper chemical mechanical polishing (Cu–CMP) have been derived to significantly influence the TDDB performance [5–7]. The time delay between CMP and barrier deposition has also shown an important role in TDDB [8,9]. Inappropriate Cu metal-to-metal lines spacing control across whole wafers could normally induce the varied TDDB reliability performance [10]. Fig. 1 shows the early failure sites of TDDB test usually found at the wafer edge areas with narrowed ULK isolation spacing between Cu lines. On the other hand, the Cu roughness and microscratches of polished surface are believed to play a crucial role to influence the TDDB as device scaling down to be sub-45 nm [11–14]. In this paper, the effects of the Cu surface ⇑ Corresponding author. Tel.: +886 6 5054888x8613257; fax: +886 6 5050960. E-mail address: [email protected] (W.C. Lin). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.04.057
roughness on TDDB and the process optimization of Cu–CMP for the reduction of Cu surface roughness have been evaluated to meet the process requirement of 28 nm technology node. 2. Experimental Three hundred millimeters Cu damascene interconnect structures were constructed by 40/28 nm metal hard mask/trench first scheme with ULK dielectric film (k value 2.5), physical vapor deposition (PVD) Cu barrier (Ta/TaN) and seed layers, Cu electroplating, Cu–CMP and nitrogen doped silicon carbide (SiCN) dielectric barrier layer. The Cu–CMP process was carrier out a rotary type polisher with three polishing platens. Two different kinds of colloidal silica based slurries were utilized to polish off the excess Cu film on platen one and platen two with hard pad and the Cu barrier/metal hard mask/ULK layers on platen three with soft pad, respectively. Alkaline based post-clean chemical solution was applied in brush clean steps to clean the polished wafers. The Cu surface roughness was characterized by high-resolution atomic force profiler on 50 50 lm Cu pad area and inspected by top viewed scanning electron microscopy (SEM) micrographs on Cu dense line structures after pattern wafer polishing and cleaning. The ULK thickness post-Cu–CMP was measured by KLA-F5x thin film measurement system. The defect inspection of the Cu roughness was conducted on KLA-Tencor 2815. Breakdown behavior, including voltage rapid dielectric breakdown (VRDB) and TDDB tests, were probed on a combed type test structure comprised of three Cu and one top Al interconnect layers. The TDDB test structure is subjected to a wafer-level constant voltage test at a temperature of 125 °C and positive bias voltage ranging from 19 to 28 V. The failure location was detected by optical beam induced resistance
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Fig. 1. (a and b) Time-dependent dielectric breakdown (TDDB) early failure sites were found at the wafer edge dies with narrowed metal line spacing conditions.
Fig. 3. Effects of the Cu surface roughness on voltage rapid dielectric breakdown (VRDB) performance.
change (OBIRCH) and then applied transmission electron microscopy (TEM) to do the failure mode analysis. 3. Results and discussion 3.1. Correlation between TDDB and Cu surface roughness Figs. 2–4 show the dense metal lines with smaller Cu surface roughness condition can result in the better performance of VRDB and TDDB performance. The top viewed SEM micrographs can quickly do qualitative judgment on the Cu surface roughness, as indicated in Fig. 2. Figs. 3 and 4 demonstrate the VRDB and TDDB performance can be significantly improved as the average Cu surface roughness reduced from 6.4 to 3.7 Å, respectively. More smooth Cu surface condition derives the better TDDB reliability performance. Obvious film cracking of the metal capping layer at the top corner of Cu lines and the Cu penetration phenomenon
Fig. 4. Effects of the Cu surface roughness on TDDB performance.
Fig. 5. Cracking of the metal capping layer was found at the top corner of Cu line induced by poor Cu surface roughness conditions.
Fig. 6. Top viewed SEM micrographs of Cu surface roughness for different remaining ULK thicknesses.
Fig. 2. SEM top viewed images for (a) bad and (b) good Cu surface roughness conditions.
on the top surface of the ULK film at the TDDB test failure areas are shown in Fig. 5. More roughing Cu surface condition could induce the cracking of the metal capping film because of poor step coverage of capping film. This film cracking area will become a
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Fig. 7. ULK removal amount thickness as a function of direct ULK polishing time. Fig. 11. Effects of the Cu surface roughness on the yield of defect density (D.D.).
3.2. Effects of the ULK film polishing amount on TDDB
Fig. 8. Bad die ratio of the Cu surface roughness as a function of removal amount of ULK layer.
Figs. 6–9 show more direct ULK removal amount can significantly eliminate Cu surface roughness and improve TDDB performance. An appropriate removal amount of ULK layer is needed for TDDB reliability improvement. The Cu line roughness decreases as increasing polishing amount of ULK film, as derived in Fig. 6. More ULK polishing condition on soft pad could overcome the deeper Cu line microscratch and roughness profile post polishing off the excess Cu film on hard pad. Figs. 7 and 8 indicate the ULK polishing rate was changed to be lower with better Cu surface roughness as polishing into the region of ULK film with lower k-value. Lower bad die ratio (BD%) of Cu surface roughness is strongly correlated to the more ULK polishing amount due to the benefit of soft pad, as demonstrated in Fig. 8. Fig. 9 shows the T63.2% of TDDB life time, stressed at 23 and 25 V test conditions, decreases as increasing remaining ULK thickness post Cu–CMP process. 3.3. Effect of post clean chemical DIW dilute ratio (D.R.) on TDDB Figs. 10–12 indicate more DIW dilute ratio of post-cleaning chemical solution is helpful to improve TDDB and the yield of the defect density (D.D.). The Cu surface roughness decreases with
Fig. 9. T 63.2% TDDB life time at 23 and 25 V test conditions as a function of remaining ULK thickness.
week point to create the diffusion path of Cu ions and result in the Cu bridge issue post-TDDB test due to Cu penetration into the interface between ULK and capping layer. Therefore, how to eliminate Cu surface roughness is very crucial to improve the TDDB reliability performance for direct polishing ULK dielectric Cu interconnects.
Fig. 12. Effects of the DIW dilute ratio on TDDB performance.
Fig. 10. Top viewed SEM micrographs of the Cu surface roughness for different DIW dilute ratios of cleaning chemical solution.
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Fig. 13. The defect dies percentage of the Cu microscratch and fall on particle for different brush gap cleaning conditions at 28 nm products.
microscratch and surface roughness at 28 nm technology node. An optimized post cleaning process with adjusted brush gap condition has been developed to effectively reduce microscratch level without suffering fall on particle performance, as shown in Fig. 13. Fig. 14 indicates the failure count of the M2 Cu line serpent open can be dramatically reduced at wide metal areas. The rootcause of upper metal line broken issue is induced by the microscratch created at underneath metal layer. The microscratch of metal lines could result in the depth of focus (DOF) limitation of lithography process on upper Cu metal areas. A promising TDDB performance can be demonstrated for an optimized brush gap condition, as demonstrated in Fig. 15. These results indicate not only Cu surface roughness, but also microscratch can significantly impact the reliability performance of TDDB. 4. Conclusions
Fig. 14. Effects of the brush gap condition on the failure count of the metal two Cu lines open.
The correlation of TDDB reliability failure with the microscratches and Cu surface roughness generated post-Cu–CMP process were identified in the study. The microscratch and larger Cu surface roughness could induce the film cracking of the SiCN capping layers. The Cu-ion migration phenomenon due to the cracking of capping layer results in the degradation of TDDB lifetime. The poor Cu surface roughness can be recovered by polishing more ULK film and optimized post-Cu–CMP brush cleaning conditions. Reducing post-clean chemical etch rate with higher DIW dilute ratio can effective eliminate Cu surface roughness. An optimized brush gap chemical cleaning condition without fall on particle concern is not only for reducing the Cu surface roughness with TDDB improvement but also for minimizing the microscratches with metal line open reduction. The reduction of microscratch can dramatically retard the failure count of the metal line open on wide metal areas. The Cu line broken issue is easily induced by the microscratch created at underneath metal layer due to the DOF limitation of the lithography process on upper Cu metal areas. References
Fig. 15. Effects of the brush gap condition on TDDB performance.
[1] [2] [3] [4] [5]
increasing the DIW dilute ratio of cleaning chemical solution, as shown in Fig. 10. The graining boundaries of the Cu lines would be attacked to result in poor Cu surface roughness as implementing a higher concentration of cleaning chemical solution to remove the fall on particles. Fig. 11 demonstrates the yield of the defect density is in inverse proportion to the degree of Cu line roughness. Better TDDB performance is improved again as reducing Cu surface roughness with more DIW dilute ratio, as demonstrated in Fig. 12. Actually, increasing DIW dilute ratio could impact the cleaning efficiency of the fall on particles with the residues of the slurry abrasives, inhibitors and byproducts. Therefore, how to overall optimize the brushing condition with appropriate concentration of the cleaning chemical is very important for a robust Cu–CMP process development. 3.4. Effect of cleaning brush gap on TDDB Figs. 13–15 demonstrate the brush gap during post Cu–CMP cleaning plays a crucial rule to influence the performance of Cu
[6] [7] [8] [9] [10] [11] [12]
[13] [14]
J.Y. Kim, E.T. Ogawa, Joe W. McPherson, IEEE IRPS Proceedings (2007) 399. F. Chen, M. Shinosky, IEEE Transactions on Electron Devices (2009) 2. G.S. Haase, IEEE IRPS Proceedings (2008) 556. M. Vilmay, D. Roy, C. Monget, F. Volpi, J. Chaix, IEEE Transactions on Device and Materials Reliability (2009) 120. C.L. Hsu, K.T. Lu, W.C. Lin, J.C. Lin, C.H. Chen, T.C. Tsai, Climbing Huang, J.Y. Wu, D.C. Perng, IEEE IRPS Proceedings (2010) 918. J. Noguchi, N. Konishi, Y. Yamada, IEEE Transactions on Electron Devices (2005) 934. M.N. Chang, Robin C.J. Wang, C.C. Chiu, Wu. Kenneth, IEEE IRPS Proceedings (2009) 619. J. Noguchi, N. Miura, M. Kubo, T. Tamaru, H. Yamaguchi, N. Hamada, K. Makabe, R. Tsuneda, K. Takeda, IEEE IRPS Proceedings (2003) 287. K. Jow, G.B. Alers, M. Sanganeria, G. Harm, H. Fu, X. Tang, G. Kooi, G.W. Ray, M. Danek, IEEE IRPS Proceedings (2003) 598. F. Chen, P. McLaughlin, J. Gambino, E. Wu, J. Demarest, D. Meatyard, M. Shinosky, IEEE IRPS Proceedings (2007) 382. C.L. Hsu, Welch Lin, C.W. Hsu, J.C. Lin, T.C. Tsai, C.C. Huang, J.Y. Wu, ESC Transactions (2010) 99. L. Arnaud, D. Galpin, S. Chhun, C. Monget, E. Richard, D. Roy, C. Besset, M. Vilmay, L. Doyen, P. Waltz, E. Petitprez, F. Terrier, G. Imbert, Y. Le Friec, IEEE IITC Proceedings (2009) 179. W. Liu, Y.K. Lim, F. Zhang, W.Y. Zhang, C.Q. Chen, B.C. Zhang, J.B. Tan, D.K. Sohn, L.C. Hsia, IEEE IRPS Proceedings (2009) 613. N. Heylen, E. Camerotto, H. Volders, Y. Travaly, G. Vereecke, G.P. Beyer, Z. Tokei, IEEE IITC Proceedings (2010) 1.