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Electromigration performance of Through Silicon Via (TSV) – A modeling approach
Microelectronics Reliability 50 (2010) 1336–1340
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Electromigration performance of Through Silicon Via (TSV) – A modeling approach Y.C. Tan a,*, C.M. Tan a, X.W. Zhang b, T.C. Chai b, D.Q. Yu b a b
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore Institute of Microelectronics, ASTAR (Agency for Science, Technology, and Research) 11 Science Park Road, Singapore Science Park II, Singapore 117685, Singapore
a r t i c l e
i n f o
Article history: Received 2 July 2010 Accepted 14 July 2010 Available online 13 August 2010
a b s t r a c t The electromigration (EM) performance of Through Silicon Via (TSV) in silicon interposer application are studied using Finite Element (FE) modeling. It is found that thermo-mechanical stress is the dominant contribution factor to EM performance in TSV instead of the current density. The predicted failure site is dependent on the process technology, and exhibits asymmetric behavior if different process is used between the top and bottom metallization of a TSV. Modeling is also done for two different coverage patterns of top metallization, namely (i) the metal line covers the via completely, and (ii) the metal line only extends to the centre of the via, covering half of the via. The simulation results of the latter model show the existence of a second EM failure site and worse EM performance is expected. This additional possible EM failure site is further confirmed through dynamic simulation of void growth. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Through Silicon Via (TSV) is one of the key enabling technology for 3-D IC integration as 2-D miniaturizing is reaching its physical limit. EM study of TSV is rarely reported due possibly to the belief that the current density in the via is much smaller than that in interconnect metallization, and hence EM will occur in the lines first before the TSV starts to suffer from EM failure. However, it is found recently that the driving forces for EM in ULSI Cu interconnects is not solely the current density, but temperature gradient and its resulting thermo-mechanical stress gradient are as significant [1]. In view of the high thermo-mechanical stress in the TSV as has been well studied [2–4], it is worthwhile to look at the EM performance of TSV. The objective of this work is to provide a study on the EM reliability of TSV in interposer application using Finite Element modeling (FEM) to identify possible EM locations. The method of using FEM to compute the Atomic Flux Divergences (AFD) as a merit for EM performance has been well established in EM modeling of ULSI interconnects [1,5].
2. Model description A FE model (see Fig. 1) is built on an actual TSV structure in interposer fabricated by IME-Singapore, ASTAR. 3D 8-node hexahedral elements are used for better accuracy of the thermomechanical solutions [6]. Modeling is performed only on half the actual structure by virtue of plane symmetry of the cross-section. * Corresponding author. Tel.: +65 97833464. E-mail address: [email protected] (Y.C. Tan). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.024
The relevant properties of the materials used in TSV modelling are shown in Table 1. Simulation methodology is similar to previous works [1,5] in the area of EM modeling of ULSI interconnects. It involves two coupled-field analyses using ANSYSÒ consisting of: (i) direct coupledfield thermal-electric analysis, and (ii) coupling the thermal result from the previous analysis to perform structural–thermal analysis. In the first analysis, the bottom surface of the substrate is held at 200 °C with uniform current density of 1.5 MA/cm2 and 0.6 MA/ cm2 for top and bottom metallization respectively. The difference in uniform current density is due to different cross-section areas of the top and bottom metallizations. A load transfer coupled analysis is then performed where nodal temperature solution of the first analysis is applied as body load to solve for the structural– thermal analysis. The substrate bottom is assumed to have zero displacement and only in-plane displacements are allowed for the four vertical sides. Stress free temperature (SFT) of the interposer is assumed to be 125 °C [3]. User sub-routines were developed to calculate the resultant AFD due to the three driving forces identified for EM modeling [1,5], namely, electron wind force induced migration (EWM), temperature gradient induced migration (TM), and thermo-mechanical stress gradient induced migration (SM). Ref. [5] also describes the detailed formulations of AFD equations. It has been shown that AFD simulations can predict EM failure locations in ULSI interconnects accurately [1,5]. In this work, simulations are applied on three different TSV models which will be described in the following sections. The main purpose is to study the effect of EM on TSV and the dependence of EM severity on TSV structure design. Manual convergence check is also performed in Model 1 to determine suitability of mesh density. The same element size is then applied for all models
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involving tungsten-filled TSV and Aluminium top metallization, it is reported that some degree of Al migration is observed experimentally [11]. Our simulation results also show that EM can indeed occur in the described TSV application (see Section 2). The possible sites of EM failure due to voiding are located near the interface of the TSV and top/bottom metallizations, which will be shown in detail in the following sections. 3.1. Model 1 Model 1 refers to the TSV structure depicted in Fig. 1. M1 and M2 tests follow the standard convention of EM test for ULSI interconnection. EM is found to be more severe in M2 test than M1 test based on the values of the total AFDs at locations A and B as shown in Fig. 3. Table 2 shows the individual contribution of the three driving forces on AFD in Model 1. One can see from Table 2 that SM contributes to more than 85% to the total AFD as compared to just 8% contribution from the EWM at the locations of maximum
Fig. 1. Schematic of TSV in Si interposer from IME.
Table 1 Material properties used for simulations [7–10]. Material
E (GPa)
CTE (ppm/°C)
Poisson ratio
Cu Ta Ti SiO2 SiN Si BCB Epoxy
110 186 116 71.4 220 130 2.9 3.6
18 6.3 9.4 0.68 3.2 2.6 50 46.2
0.34 0.34 0.36 0.16 0.27 0.28 0.33 0.37
Fig. 2. Hydrostatic stress and temperature vs. element size. Absolute values of hydrostatic stress are shown in graph as negative stress values are obtained due to simulated temperature higher than SFT (125 °C).
throughout the study to ensure consistency and allow for comparison. Fig. 2 shows a plot of both hydrostatic stress and temperature read off at the location of maximum AFD vs. element size used in the mesh. These parameters are observed to converge at the chosen mesh density.
Fig. 3. Plot of resultant AFD in Model 1. (a) M2 Test, (b) M1 test and only the bottom metallization is shown. Location A and B shows the respective local maxima of AFD (units: atoms/lm3 s).
Table 2 Breakdown of resultant AFD contributions from three driving forces at local maximum.
3. Results As TSVs are much larger than the adjacent metallizations compared to a typical Cu low-k line via structure, it is generally believed that EM is not important for TSVs. In a recent assessment
AFD contribution (%)
M2 test M1 test
EWM
TM
SM
7.5 8
4.3 3.5
88.2 88.5
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Y.C. Tan et al. / Microelectronics Reliability 50 (2010) 1336–1340
AFD. Several works [3,12–14] on thermo-mechanical simulations and X-ray diffraction experiments of TSV structures under temperature cycling have reported high localized stress/strain at these corners where the via meets the pad. The presence of these high localized stress/strain is thus expected to have an adverse effect on the EM performance of TSV. SM is heavily dependent on the stress gradient generated by the coupled thermo-mechanical stress, and thus reducing the thermal gradient will lower the total AFD at these high AFD locations, enhancing the EM performance of TSV. 3.2. Model 2 Model 2 is modified from Model 1 by having its die attach and heat sink move to the top side of the TSVs. This is to simulate the flipping of the silicon interposer between the chip side and the substrate side. Fig. 4 shows the respective temperature gradient distribution in Models 1 and 2 respectively. It is observed that temperature changes most rapidly at the locations of current crowding because this current crowding causes severe localized joule heating and act as micro-heat source. As copper is a good thermal conductor, high thermal gradient is thus resulted in these locations. When comparing the temperature gradient plots in Models 1 and 2, we see that the maximum temperature gradient is reduced by half after the interposer is ‘‘flipped” between the chip side and the substrate side. Also, the corresponding temperature gradient distribution in the metallization of the top side has better unifor-
Fig. 4. Plot of thermal gradient for (a) Model 1, (b) Model 2 (units: K/lm).
Table 3 Comparison of AFD at local maximum with heat sink at opposite side. AFD (atoms/lm3 s)
M2 test M1 test
Decrease
Model 1
Model 2
0.245E12 0.236E11
0.173E11 0.256E10
14x 9.2x
mity. This may be due to the better heat dissipation because the heat sink is now on the side of the top metallization as opposed to the previous model where the heat sink is on the side of the bottom metallization. From Table 3, it is shown that the maximum AFD for both M2 and M1 tests decrease significantly from its previous values. This means that any effort to relieve thermo-mechanical stress in the TSV offers the advantage of achieving better EM performance and higher thermo-mechanical reliability at the same time. Even
Fig. 5. Comparison of top metallization coverage pattern.
Fig. 6. Plot of resultant AFD for M2 test for Model 3 (units: atoms/lm3 s).
Y.C. Tan et al. / Microelectronics Reliability 50 (2010) 1336–1340
1339
though lowering the current density can reduce the AFD through lowered EWM, its effect is far less than that by reducing the thermo-mechanical stress.
Experimental studies of TSV electromigration will be carried out in future. Samples are being fabricated, and the results will be reported elsewhere in future.
3.3. Model 3
4. Conclusions
Model 3 is modified from Model 2 by having a different coverage pattern for the top metallization. The top metal line covers the via completely in Model 2 whereas the metal line covers only half the via in Model 3. Fig. 5 shows a schematic of such a metallization coverage when viewed from the top. The maximum AFD for M1 stress in this model is found to be of the same order as in that of Model 2; however, the maximum AFD for M2 stress in Model 3 is almost twice of that in Model 2 at the same location. Furthermore, we can also see in Fig. 6 that a possible second EM failure site (location D) behind location A exists, and high AFD occurs at this location D which is the interface between the end of the line and the via. A dynamic simulation of void growth which is similar to [5,15] is performed and its progression is shown in Fig 7. One can see that the AFD at this location is sufficiently high to allow simultaneous growing of voids, and the voids at both locations A and D will grow and finally merge together to form a larger void. In other words, in view of the higher AFD value at location A and the existence of additional location D near the vicinity of location A, worse EM performance can be expected for Model 3.
EM modeling has been done on TSV in Si interposer using FEA. The important results are summarized below: 1. EM can indeed occur in TSV. 2. Thermo-mechanical stress is the dominant factor for EM in the studied application. By reducing the temperature gradient at high AFD locations, the AFD can be reduced significantly. As such, efforts to improve thermo-mechanical reliability of TSVs through reducing the thermo-mechanical stress can also aid in improving its EM reliability. 3. Maximum AFD locations and values can be very different for the different metallization scheme and the geometrical dimensions. The failure modes of EM failure in TSV are distributed in a strongly asymmetrical manner on the top side and the bottom side of the metallizations. 4. Worse EM performance can be expected for metallization that extends to cover only half the via, as compared to one that covers the via fully. This is because TSV with partially covered via has higher AFD at the location of maximum AFD and the coexistence of an additional nearby location with sufficiently high AFD that can cause voids to grow concurrently at the two locations and merge subsequently, resulting in an earlier failure. This implies that proper design of the coverage pattern can be helpful in improving the EM performance of a TSV structure.
Acknowledgements The author wishes to acknowledge financial support awarded by Singapore Economic Development Board (EDB) and Systems on Silicon Manufacturing Co. (SSMC) to pursue a higher degree under the Joint Industry Postgraduate Program. References
Fig. 7. Void growth after (a) 5th loop, and (b) 8th loop of iteration (units: atoms/ lm3 s).
[1] Roy A, Tan CM. Probing into the asymmetric nature of electromigration performance of submicron interconnect via structure. Thin Solid Films 2007;515:3867–74. [2] Ranganathan N, Prasad K, Balasubramanian N, Pey KL. A study of thermomechanical stress and its impact on through-silicon via. J Micromech Microeng 2008;18:075018 [13pp]. [3] Cheryl S. Selvanayagam, Lau John H, Zhang XW, Seah SKW, Vaidyanathan K, Chai TC. Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps. In: Proc 58th ECTC; 2008. p. 1073– 81. [4] Dixit Pradeep, Sun YF, Miao JM, Pang John HL, Chatterjee Ritwik, Tummalaa RR. Numerical and experimental investigation of thermomechanical deformation in high-aspect-ratio electroplated through-silicon vias. J Electrochem Soc 2008;155:H981–6. [5] Dalleau D, Weide-Zaage K. Three-dimensional voids simulation in chip metallization structures. Microelectron Reliab 2001;41:1625–30. [6] Wang E, Nelson T, Rauch R. Back to elements – tetrahedra vs. hexahedra. In: 2004 International ANSYS conference; 2004. [7] Navas Khan, Vempati Srinivasa Rao, Lim S, Ho SW, Vincent Lee, Zhang XW et al. Development of 3D silicon module with TSV for system in packaging. In: Proc 58th ECTC; 2008. p. 550–5. [8] Pecht MG, Agarwal R, McCluskey P, Dishongh T, Javadpour S, Mahajan R. In: Electronic packaging materials and their properties. CRC Press; 1999. [9] Chung DDL. In: Materials for electronic packaging. Butterworth-Heinemann; 1995. [10] Ong J, Zhang X, Kripesh V, Lim YK, Yeo D, Chan KC et al. Structural design and optimization of 65 nm Cu/low-k flipchip package. In: 9th EPTC; 2007. p. 488– 92. [11] Joseph AJ, Gillis JD, Doherty M, Lindgren PJ, Previti-Kelly RA, Malladi RM, et al. Through-silicon vias enable next-generation SiGe power amplifiers for wireless communications. IBM J Res Dev 2008;52(6):635–48.
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[12] Wolf MJ, Dretschkow T, Wunderle B, Jürgensen N, Engelmann G, Ehrmann O et al. High aspect ratio TSV copper filling with different seed layers. In: Proc 58th ECTC; 2008. p. 563–70. [13] Shen LC, Chien CW, Jaung JY, Hung YP, Lo WC, Hsu CK, et al. A clamped through silicon via (TSV) interconnection for stacked chip bonding using metal cap on pad and metal column forming in via. 58th ECTC; 2008. p. 544–9.
[14] Liu X, Chen Q, Dixit P, Chatterjee R, Tummala RR, Sitaraman SK. Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV). 59th ECTC; 2009. p. 624–9. [15] Tan CM, Hou Y, Li W. Revisit to the finite element modeling of electromigration for narrow interconnects. J Appl Phys 2007;102:033705-1–5-7.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Electromigration performance of Through Silicon Via (TSV) – A modeling approach Y.C. Tan a,*, C.M. Tan a, X.W. Zhang b, T.C. Chai b, D.Q. Yu b a b
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore Institute of Microelectronics, ASTAR (Agency for Science, Technology, and Research) 11 Science Park Road, Singapore Science Park II, Singapore 117685, Singapore
a r t i c l e
i n f o
Article history: Received 2 July 2010 Accepted 14 July 2010 Available online 13 August 2010
a b s t r a c t The electromigration (EM) performance of Through Silicon Via (TSV) in silicon interposer application are studied using Finite Element (FE) modeling. It is found that thermo-mechanical stress is the dominant contribution factor to EM performance in TSV instead of the current density. The predicted failure site is dependent on the process technology, and exhibits asymmetric behavior if different process is used between the top and bottom metallization of a TSV. Modeling is also done for two different coverage patterns of top metallization, namely (i) the metal line covers the via completely, and (ii) the metal line only extends to the centre of the via, covering half of the via. The simulation results of the latter model show the existence of a second EM failure site and worse EM performance is expected. This additional possible EM failure site is further confirmed through dynamic simulation of void growth. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Through Silicon Via (TSV) is one of the key enabling technology for 3-D IC integration as 2-D miniaturizing is reaching its physical limit. EM study of TSV is rarely reported due possibly to the belief that the current density in the via is much smaller than that in interconnect metallization, and hence EM will occur in the lines first before the TSV starts to suffer from EM failure. However, it is found recently that the driving forces for EM in ULSI Cu interconnects is not solely the current density, but temperature gradient and its resulting thermo-mechanical stress gradient are as significant [1]. In view of the high thermo-mechanical stress in the TSV as has been well studied [2–4], it is worthwhile to look at the EM performance of TSV. The objective of this work is to provide a study on the EM reliability of TSV in interposer application using Finite Element modeling (FEM) to identify possible EM locations. The method of using FEM to compute the Atomic Flux Divergences (AFD) as a merit for EM performance has been well established in EM modeling of ULSI interconnects [1,5].
2. Model description A FE model (see Fig. 1) is built on an actual TSV structure in interposer fabricated by IME-Singapore, ASTAR. 3D 8-node hexahedral elements are used for better accuracy of the thermomechanical solutions [6]. Modeling is performed only on half the actual structure by virtue of plane symmetry of the cross-section. * Corresponding author. Tel.: +65 97833464. E-mail address: [email protected] (Y.C. Tan). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.024
The relevant properties of the materials used in TSV modelling are shown in Table 1. Simulation methodology is similar to previous works [1,5] in the area of EM modeling of ULSI interconnects. It involves two coupled-field analyses using ANSYSÒ consisting of: (i) direct coupledfield thermal-electric analysis, and (ii) coupling the thermal result from the previous analysis to perform structural–thermal analysis. In the first analysis, the bottom surface of the substrate is held at 200 °C with uniform current density of 1.5 MA/cm2 and 0.6 MA/ cm2 for top and bottom metallization respectively. The difference in uniform current density is due to different cross-section areas of the top and bottom metallizations. A load transfer coupled analysis is then performed where nodal temperature solution of the first analysis is applied as body load to solve for the structural– thermal analysis. The substrate bottom is assumed to have zero displacement and only in-plane displacements are allowed for the four vertical sides. Stress free temperature (SFT) of the interposer is assumed to be 125 °C [3]. User sub-routines were developed to calculate the resultant AFD due to the three driving forces identified for EM modeling [1,5], namely, electron wind force induced migration (EWM), temperature gradient induced migration (TM), and thermo-mechanical stress gradient induced migration (SM). Ref. [5] also describes the detailed formulations of AFD equations. It has been shown that AFD simulations can predict EM failure locations in ULSI interconnects accurately [1,5]. In this work, simulations are applied on three different TSV models which will be described in the following sections. The main purpose is to study the effect of EM on TSV and the dependence of EM severity on TSV structure design. Manual convergence check is also performed in Model 1 to determine suitability of mesh density. The same element size is then applied for all models
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Y.C. Tan et al. / Microelectronics Reliability 50 (2010) 1336–1340
involving tungsten-filled TSV and Aluminium top metallization, it is reported that some degree of Al migration is observed experimentally [11]. Our simulation results also show that EM can indeed occur in the described TSV application (see Section 2). The possible sites of EM failure due to voiding are located near the interface of the TSV and top/bottom metallizations, which will be shown in detail in the following sections. 3.1. Model 1 Model 1 refers to the TSV structure depicted in Fig. 1. M1 and M2 tests follow the standard convention of EM test for ULSI interconnection. EM is found to be more severe in M2 test than M1 test based on the values of the total AFDs at locations A and B as shown in Fig. 3. Table 2 shows the individual contribution of the three driving forces on AFD in Model 1. One can see from Table 2 that SM contributes to more than 85% to the total AFD as compared to just 8% contribution from the EWM at the locations of maximum
Fig. 1. Schematic of TSV in Si interposer from IME.
Table 1 Material properties used for simulations [7–10]. Material
E (GPa)
CTE (ppm/°C)
Poisson ratio
Cu Ta Ti SiO2 SiN Si BCB Epoxy
110 186 116 71.4 220 130 2.9 3.6
18 6.3 9.4 0.68 3.2 2.6 50 46.2
0.34 0.34 0.36 0.16 0.27 0.28 0.33 0.37
Fig. 2. Hydrostatic stress and temperature vs. element size. Absolute values of hydrostatic stress are shown in graph as negative stress values are obtained due to simulated temperature higher than SFT (125 °C).
throughout the study to ensure consistency and allow for comparison. Fig. 2 shows a plot of both hydrostatic stress and temperature read off at the location of maximum AFD vs. element size used in the mesh. These parameters are observed to converge at the chosen mesh density.
Fig. 3. Plot of resultant AFD in Model 1. (a) M2 Test, (b) M1 test and only the bottom metallization is shown. Location A and B shows the respective local maxima of AFD (units: atoms/lm3 s).
Table 2 Breakdown of resultant AFD contributions from three driving forces at local maximum.
3. Results As TSVs are much larger than the adjacent metallizations compared to a typical Cu low-k line via structure, it is generally believed that EM is not important for TSVs. In a recent assessment
AFD contribution (%)
M2 test M1 test
EWM
TM
SM
7.5 8
4.3 3.5
88.2 88.5
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AFD. Several works [3,12–14] on thermo-mechanical simulations and X-ray diffraction experiments of TSV structures under temperature cycling have reported high localized stress/strain at these corners where the via meets the pad. The presence of these high localized stress/strain is thus expected to have an adverse effect on the EM performance of TSV. SM is heavily dependent on the stress gradient generated by the coupled thermo-mechanical stress, and thus reducing the thermal gradient will lower the total AFD at these high AFD locations, enhancing the EM performance of TSV. 3.2. Model 2 Model 2 is modified from Model 1 by having its die attach and heat sink move to the top side of the TSVs. This is to simulate the flipping of the silicon interposer between the chip side and the substrate side. Fig. 4 shows the respective temperature gradient distribution in Models 1 and 2 respectively. It is observed that temperature changes most rapidly at the locations of current crowding because this current crowding causes severe localized joule heating and act as micro-heat source. As copper is a good thermal conductor, high thermal gradient is thus resulted in these locations. When comparing the temperature gradient plots in Models 1 and 2, we see that the maximum temperature gradient is reduced by half after the interposer is ‘‘flipped” between the chip side and the substrate side. Also, the corresponding temperature gradient distribution in the metallization of the top side has better unifor-
Fig. 4. Plot of thermal gradient for (a) Model 1, (b) Model 2 (units: K/lm).
Table 3 Comparison of AFD at local maximum with heat sink at opposite side. AFD (atoms/lm3 s)
M2 test M1 test
Decrease
Model 1
Model 2
0.245E12 0.236E11
0.173E11 0.256E10
14x 9.2x
mity. This may be due to the better heat dissipation because the heat sink is now on the side of the top metallization as opposed to the previous model where the heat sink is on the side of the bottom metallization. From Table 3, it is shown that the maximum AFD for both M2 and M1 tests decrease significantly from its previous values. This means that any effort to relieve thermo-mechanical stress in the TSV offers the advantage of achieving better EM performance and higher thermo-mechanical reliability at the same time. Even
Fig. 5. Comparison of top metallization coverage pattern.
Fig. 6. Plot of resultant AFD for M2 test for Model 3 (units: atoms/lm3 s).
Y.C. Tan et al. / Microelectronics Reliability 50 (2010) 1336–1340
1339
though lowering the current density can reduce the AFD through lowered EWM, its effect is far less than that by reducing the thermo-mechanical stress.
Experimental studies of TSV electromigration will be carried out in future. Samples are being fabricated, and the results will be reported elsewhere in future.
3.3. Model 3
4. Conclusions
Model 3 is modified from Model 2 by having a different coverage pattern for the top metallization. The top metal line covers the via completely in Model 2 whereas the metal line covers only half the via in Model 3. Fig. 5 shows a schematic of such a metallization coverage when viewed from the top. The maximum AFD for M1 stress in this model is found to be of the same order as in that of Model 2; however, the maximum AFD for M2 stress in Model 3 is almost twice of that in Model 2 at the same location. Furthermore, we can also see in Fig. 6 that a possible second EM failure site (location D) behind location A exists, and high AFD occurs at this location D which is the interface between the end of the line and the via. A dynamic simulation of void growth which is similar to [5,15] is performed and its progression is shown in Fig 7. One can see that the AFD at this location is sufficiently high to allow simultaneous growing of voids, and the voids at both locations A and D will grow and finally merge together to form a larger void. In other words, in view of the higher AFD value at location A and the existence of additional location D near the vicinity of location A, worse EM performance can be expected for Model 3.
EM modeling has been done on TSV in Si interposer using FEA. The important results are summarized below: 1. EM can indeed occur in TSV. 2. Thermo-mechanical stress is the dominant factor for EM in the studied application. By reducing the temperature gradient at high AFD locations, the AFD can be reduced significantly. As such, efforts to improve thermo-mechanical reliability of TSVs through reducing the thermo-mechanical stress can also aid in improving its EM reliability. 3. Maximum AFD locations and values can be very different for the different metallization scheme and the geometrical dimensions. The failure modes of EM failure in TSV are distributed in a strongly asymmetrical manner on the top side and the bottom side of the metallizations. 4. Worse EM performance can be expected for metallization that extends to cover only half the via, as compared to one that covers the via fully. This is because TSV with partially covered via has higher AFD at the location of maximum AFD and the coexistence of an additional nearby location with sufficiently high AFD that can cause voids to grow concurrently at the two locations and merge subsequently, resulting in an earlier failure. This implies that proper design of the coverage pattern can be helpful in improving the EM performance of a TSV structure.
Acknowledgements The author wishes to acknowledge financial support awarded by Singapore Economic Development Board (EDB) and Systems on Silicon Manufacturing Co. (SSMC) to pursue a higher degree under the Joint Industry Postgraduate Program. References
Fig. 7. Void growth after (a) 5th loop, and (b) 8th loop of iteration (units: atoms/ lm3 s).
[1] Roy A, Tan CM. Probing into the asymmetric nature of electromigration performance of submicron interconnect via structure. Thin Solid Films 2007;515:3867–74. [2] Ranganathan N, Prasad K, Balasubramanian N, Pey KL. A study of thermomechanical stress and its impact on through-silicon via. J Micromech Microeng 2008;18:075018 [13pp]. [3] Cheryl S. Selvanayagam, Lau John H, Zhang XW, Seah SKW, Vaidyanathan K, Chai TC. Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps. In: Proc 58th ECTC; 2008. p. 1073– 81. [4] Dixit Pradeep, Sun YF, Miao JM, Pang John HL, Chatterjee Ritwik, Tummalaa RR. Numerical and experimental investigation of thermomechanical deformation in high-aspect-ratio electroplated through-silicon vias. J Electrochem Soc 2008;155:H981–6. [5] Dalleau D, Weide-Zaage K. Three-dimensional voids simulation in chip metallization structures. Microelectron Reliab 2001;41:1625–30. [6] Wang E, Nelson T, Rauch R. Back to elements – tetrahedra vs. hexahedra. In: 2004 International ANSYS conference; 2004. [7] Navas Khan, Vempati Srinivasa Rao, Lim S, Ho SW, Vincent Lee, Zhang XW et al. Development of 3D silicon module with TSV for system in packaging. In: Proc 58th ECTC; 2008. p. 550–5. [8] Pecht MG, Agarwal R, McCluskey P, Dishongh T, Javadpour S, Mahajan R. In: Electronic packaging materials and their properties. CRC Press; 1999. [9] Chung DDL. In: Materials for electronic packaging. Butterworth-Heinemann; 1995. [10] Ong J, Zhang X, Kripesh V, Lim YK, Yeo D, Chan KC et al. Structural design and optimization of 65 nm Cu/low-k flipchip package. In: 9th EPTC; 2007. p. 488– 92. [11] Joseph AJ, Gillis JD, Doherty M, Lindgren PJ, Previti-Kelly RA, Malladi RM, et al. Through-silicon vias enable next-generation SiGe power amplifiers for wireless communications. IBM J Res Dev 2008;52(6):635–48.
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[12] Wolf MJ, Dretschkow T, Wunderle B, Jürgensen N, Engelmann G, Ehrmann O et al. High aspect ratio TSV copper filling with different seed layers. In: Proc 58th ECTC; 2008. p. 563–70. [13] Shen LC, Chien CW, Jaung JY, Hung YP, Lo WC, Hsu CK, et al. A clamped through silicon via (TSV) interconnection for stacked chip bonding using metal cap on pad and metal column forming in via. 58th ECTC; 2008. p. 544–9.
[14] Liu X, Chen Q, Dixit P, Chatterjee R, Tummala RR, Sitaraman SK. Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV). 59th ECTC; 2009. p. 624–9. [15] Tan CM, Hou Y, Li W. Revisit to the finite element modeling of electromigration for narrow interconnects. J Appl Phys 2007;102:033705-1–5-7.